From nobody Tue Apr 7 01:05:29 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D44D301016; Tue, 17 Mar 2026 14:41:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758507; cv=none; b=fcpJ/ugDF1SjmIDAWgroQq4grELA39hE6/lEH2QaYKZRe6+1F/eW92dURIyXonLS23JvnGZSdGrDc2EGaqDMqHV1HXFMqlB0fYakjjG9h+UomKTJLrVlZO1zg1Z17XHJ0KmX2QoUsSm8OeoxtrrTojCCDD4kgPfDIpnum31P/2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758507; c=relaxed/simple; bh=mpRF6/ZMq8597i+VUc08asvo+Ot1zx64wsFXj7PTaeA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V6AqTxXD6j+JeT5roha7jr3acha01TSf57RSIpg4zzVf6BioVPqfwrNjSUgg+4tLViWrCNxQSXT81ua2299SZLK2kxZrAM/R0snUonBLi+93+6EUuSLVtdvFD7j3P1fsRdHagSogDxitVFQQVzzIIPvRZjre3zdS0LseX9vCM2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ccz2JNVj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ccz2JNVj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5724C19424; Tue, 17 Mar 2026 14:41:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773758507; bh=mpRF6/ZMq8597i+VUc08asvo+Ot1zx64wsFXj7PTaeA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ccz2JNVjpu8nJ+BA5B/kwIk/XTMUNnsSLEpi7Bl0+OCdUfEenjJiH+1UwL0zHWQlN hcYBBY2/ECbaDgdmaa8Njk0t/UmULIUkr257yCiCsjQABa85zrSb7sYxONfzxFG4nO 5QgcaVWSjqieU+22Kg9FsxoKZs7vOPQpoVqIlqd5VipbEA9HDCmkvU1NWOulX3YoV+ Kd+MOM+d8p1PyHYinMQyJEVIBHfTv7a52MxWsE7Wp/tmk+CqrehCHyxaRPP4DKR8vk Qrau++0Twnm3bIvtFC7fKGx24hSKE3ShE655e7d+g9aVYqqgFprTjZsU+PilfFK/zA vm4qnbLP1BiVg== From: Konrad Dybcio Date: Tue, 17 Mar 2026 15:41:18 +0100 Subject: [PATCH 5/6] arm64: dts: qcom: sm8650: Fix GIC_ITS range length Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-topic-its_range_fixup-v1-5-49be8076adb1@oss.qualcomm.com> References: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> In-Reply-To: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tengfei Fan , Dmitry Baryshkov , Jingyi Wang , Luca Weiss , Vinod Koul , Dmitry Baryshkov , Sai Prakash Ranjan , Neil Armstrong , Abel Vesa , Raviteja Laggyshetty , Melody Olvera , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773758475; l=791; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=2Dgx7t26voHa3kgEypA8ZzM17S/HyzhvBSzcqSNxZyo=; b=CgoHUrPKYExQ1jeu/3exYB535PhLmUwW/HjTHwLVdqS8hA+ArTqfj1X4Gjh/EaUcYVUZL1fYr 1TQrzqOfwZ/AAd1yQKm5NYcNKdugDnafEIgfMWY7w5zAdA0WbJeFyLK X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Currently, the GITS_SGIR register is cut off. Fix it up. Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 357e43b90740..e411f5b770d1 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -7219,7 +7219,7 @@ ppi_cluster2: interrupt-partition-2 { =20 gic_its: msi-controller@17140000 { compatible =3D "arm,gic-v3-its"; - reg =3D <0 0x17140000 0 0x20000>; + reg =3D <0 0x17140000 0 0x40000>; =20 msi-controller; #msi-cells =3D <1>; --=20 2.53.0