From nobody Tue Apr 7 01:05:08 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ECA73EB80A; Tue, 17 Mar 2026 14:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758502; cv=none; b=g6NNy0FmrrsAPHETUkeK0BAfHmRHvpXT4u6NOd1dIBKkfDzzVLDabLPiuKq0VdxOyz0QlzSjzBRu74HL3yG5YfjkPUpkYzunKiRImtSVEVXFmdh1RA+kLSOsK97SOjG4CPZPmLYk1Ez/7GGHUqZ2TgNO0l1UmpXVvKJrNaVVguM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758502; c=relaxed/simple; bh=VguNReQz0nW/u9xO2S9/pIFo3Y7Onnyt4xDFGA5dLGY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XYySo5BUO+LfOerWGyz8Dczpoqv/6RDCKCLrf3Ix9N9OlZEEZ3GYCu03A+0akMrLptU19sRoluxvhdLJCZ1bjqBwWP4IMvaIB84POPti++eUxMZsFD4fizWeaz6oKG1upFL8oTn13TedsulmG9G5qw6XRiyF1MU3SCHq9HF3r3w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WcUnntg7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WcUnntg7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC175C2BCB0; Tue, 17 Mar 2026 14:41:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773758502; bh=VguNReQz0nW/u9xO2S9/pIFo3Y7Onnyt4xDFGA5dLGY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WcUnntg7H2NMyZHTDQxKq9Mlir6dbEWassSoYfl/9mHaaMy14dd56xoJgdfBqcKFw d2qlNJt/qOdL+phb3je/g/nh3oRzApLUKB2+9Jknmp9bfCcKpy+TRaDBZgMZzXYzyM y2IlPsfsGyygok3PSZB3kZ9l/5AEhLv7OXRGL8K0hBCJ9KbjdCTW7sI3nglZADzVDy VwmKoEBh756Qd8uBSmegV33c0aMaN6F0nDfEeAbkTFUINXQPro+0cjK4zpne8+uGp3 PH2LUC8Lc0eOYjqu/SXe3AzcbCek8wr6onNVrr67xAqDRlUGKofHeiyu22Am7BofSh 60GPHT7nyO6mQ== From: Konrad Dybcio Date: Tue, 17 Mar 2026 15:41:17 +0100 Subject: [PATCH 4/6] arm64: dts: qcom: sm8550: Fix GIC_ITS range length Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-topic-its_range_fixup-v1-4-49be8076adb1@oss.qualcomm.com> References: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> In-Reply-To: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tengfei Fan , Dmitry Baryshkov , Jingyi Wang , Luca Weiss , Vinod Koul , Dmitry Baryshkov , Sai Prakash Ranjan , Neil Armstrong , Abel Vesa , Raviteja Laggyshetty , Melody Olvera , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773758475; l=793; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=lgf0qVgrgdEc34dWC0C3bqqV8w4w1NxbIBjbxxWx8/M=; b=1jxYbl77xvGWpr2bKJymGxVgJyWMsVqd2zwYTDPAHd7WfhSUCOgVcmdqgPJUp6apvgDyPNosy S55YkQVEQJJC8y0nxKbypNJJ7NNjoohw7avsf8NhbHJyvkhgfjqOOA9 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Currently, the GITS_SGIR register is cut off. Fix it up. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412d..0fc86967bbeb 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5274,7 +5274,7 @@ ppi_cluster3: interrupt-partition-3 { =20 gic_its: msi-controller@17140000 { compatible =3D "arm,gic-v3-its"; - reg =3D <0 0x17140000 0 0x20000>; + reg =3D <0 0x17140000 0 0x40000>; msi-controller; #msi-cells =3D <1>; }; --=20 2.53.0