From nobody Tue Apr 7 01:05:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A5373E8683; Tue, 17 Mar 2026 14:41:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758492; cv=none; b=HtVDmzN8OteCRJ9NVF1XIw5HJCITjHMzBLqJ9eBOwUkRbsN/9+lrbTygSbznd4i94Sd7b3n5LMnaiprYVCpylLvTNPSb0jrguYFQrDeNxWP1BLj6Coc4gJex0K4Xi5vOoZglK+D2d+b7sGKkVNRvAdpFQ4uW2rRYmAGGRpfdHlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758492; c=relaxed/simple; bh=dZyi8aJaXqtR/ot1ORt6HlY0Ip6jwoOIidfODrIOwss=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DPNWpIy+3xixWR6sgu02kIpOI0d7FQ+cKvAOl4MghGifHHAqrYlX1qLfXYI7cEUBr2S1e9kBwitnpJnCJjQDfLD3IPEJRjbM3tQN7gPopml29eEA1Np3F2gXl2wIa2pz5Oz6U+5K1mpJBwKn/yuHova8paC75ik0YhYdquO5Pbo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KkE6Ja/W; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KkE6Ja/W" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F725C19424; Tue, 17 Mar 2026 14:41:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773758491; bh=dZyi8aJaXqtR/ot1ORt6HlY0Ip6jwoOIidfODrIOwss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KkE6Ja/WiS29KJLVnGkI2OceQirO1q0Qgu8hNcMmMvbMKyMbx5ih10J9nnGR0CJV3 Z2dgpr13ML1zQBUeM2cfjn8HXtTtoRW8Z5FZsnfG9l1Bvg+FcUmAI/Q0ndArwZoIVb acfbv04NStWQLd9tPXwh/c1IZrnK6bWMqG6I1+9JZDhVLeGJ0MyXhb7FGSwJiefCUn S86HHT4kiT7kVHImA+QFzcVErbSnhv+JsMjCa7HDDBzSj4tje+C9rUJn9KpUKKHY/d P0RTqcbhkSynTE/2a78gAnmmvNzqn1Ai59MVJ74kRAYasvGJAj9r37gIdV1Zp4InKI SdZxNikYE+g8Q== From: Konrad Dybcio Date: Tue, 17 Mar 2026 15:41:15 +0100 Subject: [PATCH 2/6] arm64: dts: qcom: milos: Fix GIC_ITS range length Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-topic-its_range_fixup-v1-2-49be8076adb1@oss.qualcomm.com> References: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> In-Reply-To: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tengfei Fan , Dmitry Baryshkov , Jingyi Wang , Luca Weiss , Vinod Koul , Dmitry Baryshkov , Sai Prakash Ranjan , Neil Armstrong , Abel Vesa , Raviteja Laggyshetty , Melody Olvera , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773758475; l=793; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=7g69GUVaZMAOA7HXfOnKUbAu1o/HUL2Ti6Lbhkg3OW8=; b=YVhj60riGGS+JQw8xNXBMxwHLUs2/f+vwwUwFjPA51++MYzuwXuCxwBh428voIEZd+fKl9f8O xxVMg/lv412A3NCYvUIyQcYH/MUlIOnU+Bys3aq92z3HkYxgUHsjOAE X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Currently, the GITS_SGIR register is cut off. Fix it up. Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index e1a51d43943f..084be5316e0d 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1911,7 +1911,7 @@ ppi_cluster1: interrupt-partition-1 { =20 gic_its: msi-controller@17140000 { compatible =3D "arm,gic-v3-its"; - reg =3D <0x0 0x17140000 0x0 0x20000>; + reg =3D <0x0 0x17140000 0x0 0x40000>; =20 msi-controller; #msi-cells =3D <1>; --=20 2.53.0