From nobody Tue Apr 7 01:05:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34C7A3EC2F8; Tue, 17 Mar 2026 14:41:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758487; cv=none; b=mE0EJyWZ90TqWRmkkGvvO4TIRd5E2t2XjJtK83m81cQdWNIs7IMlhjcSn7t6jxzF/skAYm4Rr8ehgZRcnFlKXDd7+rQTClsSJA3Lcsb0ufGfpwMev0F1WfBFDKTFATs8efoNSUcPWlxBtB3CUFI7PT9jKRh6FLE6ryTebUwEqtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773758487; c=relaxed/simple; bh=k7nHZzZufqsYwm4qn2gQPm3HsosqnZMcJUouIGo4gxc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pacQJ7peDBWToRW0/CEZe1m3mlVcCAHGTdYch+kIbG6Y4ppJxbWsIwE1JyN8Pd+zNYyGvmJmSmEbJBMwljRVF+DhjCgzjQt9v4SnZvMXkpAa6E5pC5Bdu/0ACuZ8o160//hoWWiXZaCkhmHiSOnqvZVnXhnh5hGEGp+dxw46fVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p7hGVevM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p7hGVevM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 12AA0C4CEF7; Tue, 17 Mar 2026 14:41:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773758486; bh=k7nHZzZufqsYwm4qn2gQPm3HsosqnZMcJUouIGo4gxc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=p7hGVevMiO5BzL/snJgSH5+1aeCDyIrJwxYtR6W8IuQUEg23trHTRNi7wt3NGQiCP SVmd0rdRWErc5pLpOT8kcjw0xLwnrOCQWqe5Q0WH+UgmwApsIHfJMaUpzyZ6mmw8Vf cP2JojB2aigW/bk5bENg09PSx+lLJqpp0RWeYbe5S3Jq9pUaaXPA4CU9kpVD30JYlr 1+PaKj6UAg5yl5DSOul8il4KX6DU3LO4XnCsZ/da8c0oOJHMx0BRxUyE2hRw1bAEI+ vUWYpF5K5Eqy7nA2aGTDYlrUAhYQes3ewq0UwUIrrQZbWI7LGkhulJOigKMw4/kwrU VZrycg5qGRzzA== From: Konrad Dybcio Date: Tue, 17 Mar 2026 15:41:14 +0100 Subject: [PATCH 1/6] arm64: dts: qcom: kaanapali: Fix GIC_ITS range length Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-topic-its_range_fixup-v1-1-49be8076adb1@oss.qualcomm.com> References: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> In-Reply-To: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tengfei Fan , Dmitry Baryshkov , Jingyi Wang , Luca Weiss , Vinod Koul , Dmitry Baryshkov , Sai Prakash Ranjan , Neil Armstrong , Abel Vesa , Raviteja Laggyshetty , Melody Olvera , Taniya Das Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773758475; l=814; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=ov4JGQYUDS+7Tz5X0bnk6/rOwa2yospE72rnBNVtDkM=; b=bUtJEV/6diiMyj0tbZKIxrdrbRFP33tkhYDOI7Q8QN1BdqONs/0XJ935ydSkVugajh+KzK/1v MuprYFe3Bw3CAFZyLxsEFspwbcMgTmxO/KaM+A+sgUKCUYQOsPghkCV X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Currently, the GITS_SGIR register is cut off. Fix it up. Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 9ef57ad0ca71..9be86479ceef 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -1239,7 +1239,7 @@ intc: interrupt-controller@17000000 { =20 gic_its: msi-controller@17040000 { compatible =3D "arm,gic-v3-its"; - reg =3D <0x0 0x17040000 0x0 0x20000>; + reg =3D <0x0 0x17040000 0x0 0x40000>; =20 msi-controller; #msi-cells =3D <1>; --=20 2.53.0