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Tue, 17 Mar 2026 02:21:22 -0700 (PDT) Received: from hu-hdev-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35badbcdaa6sm2331968a91.15.2026.03.17.02.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 02:21:21 -0700 (PDT) From: Harshal Dev Date: Tue, 17 Mar 2026 14:50:40 +0530 Subject: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-qcom_ice_power_and_clk_vote-v3-1-53371dbabd6a@oss.qualcomm.com> References: <20260317-qcom_ice_power_and_clk_vote-v3-0-53371dbabd6a@oss.qualcomm.com> In-Reply-To: <20260317-qcom_ice_power_and_clk_vote-v3-0-53371dbabd6a@oss.qualcomm.com> To: Herbert Xu , "David S. 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When the 'clk_ignore_unused' flag is not passed on the kernel command line occasional unclocked ICE hardware register access are observed when the kernel disables the unused 'iface' clock before ICE can probe. On the other hand, when the 'pd_ignore_unused' flag is not passed on the command line, clock 'stuck' issues are observed if the power-domain required by ICE hardware is unused and thus disabled before ICE probe could happen. To avoid these scenarios, the 'iface' clock and the associated power-domain should be specified in the ICE device tree node and enabled by ICE. Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engi= ne") Signed-off-by: Harshal Dev --- .../bindings/crypto/qcom,inline-crypto-engine.yaml | 16 ++++++++++++= +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-en= gine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-eng= ine.yaml index 876bf90ed96e..99c541e7fa8c 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml @@ -30,6 +30,16 @@ properties: maxItems: 1 =20 clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: iface + + power-domains: maxItems: 1 =20 operating-points-v2: true @@ -52,7 +62,11 @@ examples: compatible =3D "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg =3D <0x01d88000 0x8000>; - clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names =3D "core", + "iface"; + power-domains =3D <&gcc UFS_PHY_GDSC>; =20 operating-points-v2 =3D <&ice_opp_table>; =20 --=20 2.34.1