From nobody Tue Apr 7 01:18:30 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [91.198.224.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2C5136655E for ; Tue, 17 Mar 2026 10:31:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.198.224.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743463; cv=none; b=iB2FK17z5oElZbVBv/2lM/SxnQYYek4K4xM/4Sdu2Bksgef2ge32hglTvHVRwkBF35cbTcb3GqcrXCTw3VR6ckxGxTbTvNRYHSzTQ9Zmq3+2gKeiMvsuuuT3KDrUd4JBDqyzwLfuruAhqLLN/QiwhdAfRwRRZGJd4vTAkDQsWGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773743463; c=relaxed/simple; bh=x0G6kbp3HPUk+Ad9f2NmimHwiVEP6L9O7uku31wgrpk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:Cc; b=Y4bZRJMbbPoNYkYtPetbYloE14Hy+ayHtDSvspzCbTV7NXAULwbLey1byoKAlfpt7p/TPvEjpByMhFgEffZTNoFiUZvWjljQ45gDVztGaRSF+8Md6kFEOkB+LEErgdtsYdU6foK5J/ZoKQ2c8C+xfBohHrtndh8idh7HLhlfHVY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de; spf=pass smtp.mailfrom=dev.tdt.de; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b=kpK5HHp0; arc=none smtp.client-ip=91.198.224.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b="kpK5HHp0" Received: from [194.37.255.9] (helo=mxout.expurgate.net) by relay.expurgate.net with smtp (Exim 4.92) (envelope-from ) id 1w2RQC-00C6xZ-Fk; Tue, 17 Mar 2026 11:13:08 +0100 Received: from [195.243.126.94] (helo=securemail.tdt.de) by relay.expurgate.net with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1w2RQB-004Sa5-H4; Tue, 17 Mar 2026 11:13:07 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de; s=z1-selector1; t=1773742387; bh=zg7zDCV4smsRlNBf4AysL3MRNisHZBZ6g50pqPBg2Cc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kpK5HHp0ZRWnffKtIEVl4U7riPagMcVn6Seqd/a9fZ71MYWn3U4jzXa1AUWVVlURD 8alSGb+BZSqbgCgq22p8ihX8Vjgt8izWMU+1iigJtD1HZYzHMhN6I3rbJ2c3iaTjLn GHK5MBrXBWFpS7dzMvkNrxWz3KiDw85XfNUumTQJHlYrgC4iQWpcoolS4M5X1Ki9N6 1bgFdS4nfz6pyrzN6rrepw763kgWDStOKaWikGpVk4P2alTtw+s47ZX1UISQ+qJCZY qwug9z61V9UeqXkjifEJWuvzGWCZMLzsszXkk2vqVlcEKGKjF4Wbt/hI5ZH6Wud1Ws s2sg7Kv95JWpA== Received: from securemail.tdt.de (localhost [127.0.0.1]) by securemail.tdt.de (Postfix) with ESMTP id EA11A240036; Tue, 17 Mar 2026 11:13:06 +0100 (CET) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id D33C9240042; Tue, 17 Mar 2026 11:13:06 +0100 (CET) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id B927B237A2; Tue, 17 Mar 2026 11:13:06 +0100 (CET) From: Florian Eckert Date: Tue, 17 Mar 2026 11:12:49 +0100 Subject: [PATCH 1/5] PCI: intel-gw: Move interrupt enable to own function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260317-pcie-intel-gw-v1-1-7fe13726ad4f@dev.tdt.de> References: <20260317-pcie-intel-gw-v1-0-7fe13726ad4f@dev.tdt.de> In-Reply-To: <20260317-pcie-intel-gw-v1-0-7fe13726ad4f@dev.tdt.de> To: Chuanhua Lei , Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Florian Eckert X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773742386; l=1433; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=x0G6kbp3HPUk+Ad9f2NmimHwiVEP6L9O7uku31wgrpk=; b=lc0Wvl8sgOs/PsbxjJyrN1Y3aozSx5CPTx8DLq93DyQRSGetDxaL0vAjQyymOoMWZHFTX4nqS zew5Rr1x3MeDsCPNony/5UrTN/+RhgTDn1hakTj+oJc3La/mRjWT9KP X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-ID: 151534::1773742388-EF518769-1310CEAB/0/0 X-purgate-type: clean X-purgate: clean To improve the readability of the code, move the interrupt enable instructions to a separate function. That is already done for the disable interrupt instruction. Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index c21906eced61896c8a8307dbd6b72d229f9a5c5f..3a85bd0ef1b7f9414ce19fe56d8= 2a78e34e9b648 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -196,6 +196,13 @@ static void intel_pcie_device_rst_deassert(struct inte= l_pcie *pcie) gpiod_set_value_cansleep(pcie->reset_gpio, 0); } =20 +static void intel_pcie_core_irq_enable(struct intel_pcie *pcie) +{ + pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); + pcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT); + pcie_app_wr(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT); +} + static void intel_pcie_core_irq_disable(struct intel_pcie *pcie) { pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); @@ -317,9 +324,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) if (ret) goto app_init_err; =20 - /* Enable integrated interrupts */ - pcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT, - PCIE_APP_IRN_INT); + intel_pcie_core_irq_enable(pcie); =20 return 0; =20 --=20 2.47.3