From nobody Mon Apr 6 21:35:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D22BB343D75; Tue, 17 Mar 2026 20:10:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773778250; cv=none; b=uk1MpqsdjQ4dk2dlLX62KZO1LWELdfYzm/Y7LS4gp8Tbu4ANutWWAG4nfZY+ElX9KcQ3AGftqxzMClnX8RTSV+B3gZiwCMgYKJ5XbvGHn6XsbGM89VM1bR0UV2mOjG8d3Co6JJlvpQaVo/LL4EbQPKdTS1iEmcGfCnqpupbKerE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773778250; c=relaxed/simple; bh=7Zrl9LgYU0uG/gkxxnGX7IO3muYoRFeqnMe61ZFmuCU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V2ME1piyz0coFQMUfg64JCq80bEE963cZZI8OOYeWkKB42RwhlHdn0AkqaHhfGB3BnPT2L8J7Bz5rD1TyG69leJR7BdlwVTFEb7Y5eP+3uw73pd/on70I7AWevgEytKGjjzq5IoQJNb2pPIfi81hns6S3eptFTaCuTeEIlgHdfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p07fQCxg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p07fQCxg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 21E0AC2BC9E; Tue, 17 Mar 2026 20:10:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773778250; bh=7Zrl9LgYU0uG/gkxxnGX7IO3muYoRFeqnMe61ZFmuCU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=p07fQCxg4S+U5yHyWpNKZl9U3S/0MeN9FcokzC5bmJX9a8YQskZFgQm8lhGxnHvZN B4SpUx6XFiPVmom8rSVyV/1P5Koj/rwedg1+RMWV8hnb3tsbTOmfztG/Q+nzvOECGp gF7wTNOPYHZrImi5kOancgY9HsC8lnXIcQK1U/WkjFMpqGstnk8lkOqBgpl7HznElQ 496KMJYOjW+SaWWi9EWVNHxVTjbsUFTqtQPaBIbalLw0BBt6UGgS44QdoG/uVIk2kt m7W4OIs9MBFoOmwJnbLjm/1rUxUElKRBIfKspbqL8LvDgS3ZAbPZWq0qEcX9QNGc6r 1N+jR9BFSLuEg== From: Mark Brown Date: Tue, 17 Mar 2026 20:10:34 +0000 Subject: [PATCH v5 1/5] KVM: selftests: arm64: Report set_id_reg reads of test registers as tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-kvm-arm64-set-id-regs-aarch64-v5-1-a60f2b956e22@kernel.org> References: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> In-Reply-To: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> To: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , Oliver Upton Cc: Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-e1b5b X-Developer-Signature: v=1; a=openpgp-sha256; l=4884; i=broonie@kernel.org; h=from:subject:message-id; bh=7Zrl9LgYU0uG/gkxxnGX7IO3muYoRFeqnMe61ZFmuCU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpubVBro/nqiAFxzKpMCOZkVUat/glwgDw34yd6 jursV9v/duJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCabm1QQAKCRAk1otyXVSH 0IBEB/9tJbIt82LV8zE/rZKljkthE8uq3ahj5zOPG/SEXT5923bGRTWe6zttdbAmZgo8KIC2KaS sz2O23s+6+RP+tfL3W7nNzGqGu4w/CNGwgqn5K5wWov/h5d4PamprN2y4Hc9Wl4m4AzBLuR8weL /tbW7QDwYbNJ9R3y0N8tu0Nh/bqybeM7vQMB7g/qo8mEwgyMPNDab137R9ePvh7qvCofAPI5UTf DCpFT/BBI2eWHz49mOMw0uYZiTdkz4f/WmC6W8pnfAjP9CAXZzE5e8FV0fLYz22l2LSmeCwfoYi 5nYKqs9p7DGlsoxLw8EKCOD/NNMlP24/2p7zHpOpFwD+DC2h X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Currently when we run guest code to validate that the values we wrote to the registers are seen by the guest we assert that these values match using a KVM selftests level assert, resulting in unclear diagnostics if the test fails. Replace this assert with reporting a kselftest test per register. In order to support getting the names of the registers we repaint the array of ID_ registers to store the names and open code the rest. Reviewed-by: Ben Horgan Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 74 +++++++++++++++++++--= ---- 1 file changed, 57 insertions(+), 17 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 73de5be58bab..75f23371d97d 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -40,6 +40,7 @@ struct reg_ftr_bits { }; =20 struct test_feature_reg { + const char *name; uint32_t reg; const struct reg_ftr_bits *ftr_bits; }; @@ -217,24 +218,25 @@ static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[= ] =3D { =20 #define TEST_REG(id, table) \ { \ - .reg =3D id, \ + .name =3D #id, \ + .reg =3D SYS_ ## id, \ .ftr_bits =3D &((table)[0]), \ } =20 static struct test_feature_reg test_regs[] =3D { - TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), - TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1), - TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), - TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), - TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), - TEST_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1), - TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), - TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), - TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), - TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), - TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), - TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1), - TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), + TEST_REG(ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1), + TEST_REG(ID_DFR0_EL1, ftr_id_dfr0_el1), + TEST_REG(ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1), + TEST_REG(ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1), + TEST_REG(ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1), + TEST_REG(ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1), + TEST_REG(ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1), + TEST_REG(ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1), + TEST_REG(ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1), + TEST_REG(ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), + TEST_REG(ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), + TEST_REG(ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1), + TEST_REG(ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), }; =20 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0); @@ -264,6 +266,34 @@ static void guest_code(void) GUEST_DONE(); } =20 +#define GUEST_READ_TEST (ARRAY_SIZE(test_regs) + 6) + +static const char *get_reg_name(u64 id) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(test_regs); i++) + if (test_regs[i].reg =3D=3D id) + return test_regs[i].name; + + switch (id) { + case SYS_MPIDR_EL1: + return "MPIDR_EL1"; + case SYS_CLIDR_EL1: + return "CLIDR_EL1"; + case SYS_CTR_EL0: + return "CTR_EL0"; + case SYS_MIDR_EL1: + return "MIDR_EL1"; + case SYS_REVIDR_EL1: + return "REVIDR_EL1"; + case SYS_AIDR_EL1: + return "AIDR_EL1"; + default: + TEST_FAIL("Unknown register"); + } +} + /* Return a safe value to a given ftr_bits an ftr value */ uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) { @@ -638,6 +668,8 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu) { bool done =3D false; struct ucall uc; + uint64_t reg_id, expected_val, guest_val; + bool match; =20 while (!done) { vcpu_run(vcpu); @@ -648,8 +680,16 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu) break; case UCALL_SYNC: /* Make sure the written values are seen by guest */ - TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])], - uc.args[3]); + reg_id =3D uc.args[2]; + guest_val =3D uc.args[3]; + expected_val =3D test_reg_vals[encoding_to_range_idx(reg_id)]; + match =3D expected_val =3D=3D guest_val; + if (!match) + ksft_print_msg("%lx !=3D %lx\n", + expected_val, guest_val); + ksft_test_result(match, + "%s value seen in guest\n", + get_reg_name(reg_id)); break; case UCALL_DONE: done =3D true; @@ -789,7 +829,7 @@ int main(void) =20 ksft_print_header(); =20 - test_cnt =3D 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST; + test_cnt =3D 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST + GUEST_READ_TEST; for (i =3D 0; i < ARRAY_SIZE(test_regs); i++) for (j =3D 0; test_regs[i].ftr_bits[j].type !=3D FTR_END; j++) test_cnt++; --=20 2.47.3 From nobody Mon Apr 6 21:35:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B642337F8A8; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vEC5qbo6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF32DC4CEF7; Tue, 17 Mar 2026 20:10:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773778253; bh=kFeKoFDmekxxcafvujeqVbvYB0xH3vg3F9QRQrkEoOE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vEC5qbo6U6FpH2KAtG9ztjEoqKsccUXFiwJQ5ufPj6QHIsvmD0Aw0f/31CIH2stGd VjgtaqM5HiAb3SZBTZlbuI85y1QdVIST6+Shv73n1owHIQSYSbmvNAoQgY9LMAj8Gt /WtwCHuSEjcWuN7dkk7eVnd4GF8t6dIumVOlcoy57eezyFVgu6thVv5QUEB0GpOQAf BFnVWL0ZFF0UKnEFh2zaODre/F2C48aBKiZqJZgwiCzw/fhWevZKGTc/ppCgn6ziH/ ed/moA+4ztWJke3fBaS7ATs9OfjB9dsIy71NYwguzGvHMj5Bf8451MCJ+/0NoswSZx nsRP8JQbjsCTg== From: Mark Brown Date: Tue, 17 Mar 2026 20:10:35 +0000 Subject: [PATCH v5 2/5] KVM: selftests: arm64: Report register reset tests individually Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-kvm-arm64-set-id-regs-aarch64-v5-2-a60f2b956e22@kernel.org> References: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> In-Reply-To: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> To: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , Oliver Upton Cc: Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-e1b5b X-Developer-Signature: v=1; a=openpgp-sha256; l=2248; i=broonie@kernel.org; h=from:subject:message-id; bh=kFeKoFDmekxxcafvujeqVbvYB0xH3vg3F9QRQrkEoOE=; b=kA0DAAoBJNaLcl1Uh9AByyZiAGm5tUGgGcVX2IzCqGQdpFqqfPs4PTc8/c20iS58WDLQyFAC4 IkBMwQAAQoAHRYhBK3maKpnVxi1n+Kf6iTWi3JdVIfQBQJpubVBAAoJECTWi3JdVIfQJvYIAIKM Gwp4XdxPZ7J5pq7cW6MgthHq/HwyKfkJgBu/c6vGZVADnsf40qXyX1qM4httVOeCLZOTZppMQ8r PqrXWvttHaAdizNUlJR7HDQn0CSJkHvs2bYNPsdWjl1uW7/LPxlOhmxepTZX7b52qW5XUaPTxET Nmri8Ng8IoLtNMLYQhz1YjQ63gTs3uE7dYWsg3mvAYTmvMLcN91zW1LuVGFMdQoo0Q7+WOG6566 RVayZ8XtOgEZaCIJTO/nMVH/5RI8cgPTKu2Kqoq4gsvC5VFCYNLyXFTuwkTF4E0q122NSVmE3BK yfIC/EniKBF4nssSHEpOmdX0c1Mv8ZkIpmuNnPs= X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB set_id_regs tests that registers have their values preserved over reset. Currently it reports all registers in a single test with an instantly fatal assert which isn't great for diagnostics, it's hard to tell which register failed or if it's just one register. Change this to report each register as a separate test so that it's clear from the program output which registers have problems. Reviewed-by: Ben Horgan Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 75f23371d97d..1072ee125b05 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -778,11 +778,18 @@ static void test_assert_id_reg_unchanged(struct kvm_v= cpu *vcpu, uint32_t encodin { size_t idx =3D encoding_to_range_idx(encoding); uint64_t observed; + bool pass; =20 observed =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); - TEST_ASSERT_EQ(test_reg_vals[idx], observed); + pass =3D test_reg_vals[idx] =3D=3D observed; + if (!pass) + ksft_print_msg("%lx !=3D %lx\n", test_reg_vals[idx], observed); + ksft_test_result(pass, "%s unchanged by reset\n", + get_reg_name(encoding)); } =20 +#define ID_REG_RESET_UNCHANGED_TEST (ARRAY_SIZE(test_regs) + 6) + static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu) { /* @@ -800,8 +807,6 @@ static void test_reset_preserves_id_regs(struct kvm_vcp= u *vcpu) test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1); test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1); test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1); - - ksft_test_result_pass("%s\n", __func__); } =20 int main(void) @@ -829,7 +834,8 @@ int main(void) =20 ksft_print_header(); =20 - test_cnt =3D 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST + GUEST_READ_TEST; + test_cnt =3D 2 + MPAM_IDREG_TEST + MTE_IDREG_TEST + GUEST_READ_TEST + + ID_REG_RESET_UNCHANGED_TEST; for (i =3D 0; i < ARRAY_SIZE(test_regs); i++) for (j =3D 0; test_regs[i].ftr_bits[j].type !=3D FTR_END; j++) test_cnt++; --=20 2.47.3 From nobody Mon Apr 6 21:35:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735AB37C0FD; Tue, 17 Mar 2026 20:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 17 Mar 2026 20:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773778256; bh=6dDHuW+3JnPVTu+x6wcXrghvQBtRlj+/DG5vIrcHhF0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=r8zwYHlWLq50rhjhW4gRhHpvC6j9uoEMuetvW66QuY4uJhw+oQWzarWgow6TdIKkp 47q7DWk71OZbur8024d0l/r+XwDQj6nMqe4FF+DjT4eWJhA3qdj/591fVYADMNhoGZ CXX0VriJnH8TS2JtmJ7afjQ9Td671HpV6TGxw0WZpPi/lQGOhLbCVhXVB3AiNhPYR1 cD2sFvGb+/vfWRAMG8ROkOlMa60WFFpMil116pMHUlx0PF8x5WU+vMfzX2S2VkUQAZ 0bFJp4/bQRiTOgb+0BlTgnz4mE+QgDcDexuSjTDm4ES41LeAFFQoTZWdgFwmjrTgKA obcv1SlDudtjg== From: Mark Brown Date: Tue, 17 Mar 2026 20:10:36 +0000 Subject: [PATCH v5 3/5] KVM: selftests: arm64: Make set_id_regs bitfield validatity checks non-fatal Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-kvm-arm64-set-id-regs-aarch64-v5-3-a60f2b956e22@kernel.org> References: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> In-Reply-To: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> To: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , Oliver Upton Cc: Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-e1b5b X-Developer-Signature: v=1; a=openpgp-sha256; l=3569; i=broonie@kernel.org; h=from:subject:message-id; bh=6dDHuW+3JnPVTu+x6wcXrghvQBtRlj+/DG5vIrcHhF0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpubVCSsYWqCVjfFXLy7wmXi50Yj6eGPMcyp20C ireXYfKlqeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCabm1QgAKCRAk1otyXVSH 0NrGB/0cfYW+8CKzBzLbLRFTdwiSb6WRYo46e0wJg5AslfCe5ynXSkB8QYazMrCWwf8+iCY8N6x BGd56olXlpcaOV1JPaw+rV8qU3G+tueMAtQ/tVyeEuBy4aobYh+3lD4zWOXlx13tED4hAly7qZh M5H7e5r8hnNZlCqA6VwmbqBZvBNOEjXF9m9QA/UTnG1QJ9S69D4F+xAXqM9RdSaiAqKW0Y+tYkP aIksmpENsuUO2Mo9+tXOHvYqlGbRtC3ucGauYZqIeDX8IyqGBJ40uQqU+Zrrn7FVbwURZad2mKN nS4+IdzIqws37C0NOfgWv0gqMg35DxYSSeSj0jJOBp40HPv4 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Currently when set_id_regs encounters a problem checking validation of writes to feature registers it uses an immediately fatal assert to report the problem. This is not idiomatic for kselftest, and it is also not great for usability. The affected bitfield is not clearly reported and further tests do not have their results reported. Switch to using standard kselftest result reporting for the two asserts we do, these are non-fatal asserts so allow the program to continue and the test names include the affected field. Reviewed-by: Ben Horgan Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 1072ee125b05..60e7f0c1bc26 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -408,6 +408,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *v= cpu, uint64_t reg, uint8_t shift =3D ftr_bits->shift; uint64_t mask =3D ftr_bits->mask; uint64_t val, new_val, ftr; + bool match; =20 val =3D vcpu_get_reg(vcpu, reg); ftr =3D (val & mask) >> shift; @@ -420,7 +421,10 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *= vcpu, uint64_t reg, =20 vcpu_set_reg(vcpu, reg, val); new_val =3D vcpu_get_reg(vcpu, reg); - TEST_ASSERT_EQ(new_val, val); + match =3D new_val =3D=3D val; + if (!match) + ksft_print_msg("%lx !=3D %lx\n", new_val, val); + ksft_test_result(match, "%s valid write succeeded\n", ftr_bits->name); =20 return new_val; } @@ -432,6 +436,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, ui= nt64_t reg, uint64_t mask =3D ftr_bits->mask; uint64_t val, old_val, ftr; int r; + bool match; =20 val =3D vcpu_get_reg(vcpu, reg); ftr =3D (val & mask) >> shift; @@ -448,7 +453,10 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, u= int64_t reg, "Unexpected KVM_SET_ONE_REG error: r=3D%d, errno=3D%d", r, errno); =20 val =3D vcpu_get_reg(vcpu, reg); - TEST_ASSERT_EQ(val, old_val); + match =3D val =3D=3D old_val; + if (!match) + ksft_print_msg("%lx !=3D %lx\n", val, old_val); + ksft_test_result(match, "%s invalid write rejected\n", ftr_bits->name); } =20 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE]; @@ -488,7 +496,11 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu,= bool aarch64_only) for (int j =3D 0; ftr_bits[j].type !=3D FTR_END; j++) { /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ if (aarch64_only && sys_reg_CRm(reg_id) < 4) { - ksft_test_result_skip("%s on AARCH64 only system\n", + ksft_print_msg("%s on AARCH64 only system\n", + ftr_bits[j].name); + ksft_test_result_skip("%s invalid write rejected\n", + ftr_bits[j].name); + ksft_test_result_skip("%s valid write succeeded\n", ftr_bits[j].name); continue; } @@ -500,8 +512,6 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, = bool aarch64_only) =20 test_reg_vals[idx] =3D test_reg_set_success(vcpu, reg, &ftr_bits[j]); - - ksft_test_result_pass("%s\n", ftr_bits[j].name); } } } @@ -838,7 +848,7 @@ int main(void) ID_REG_RESET_UNCHANGED_TEST; for (i =3D 0; i < ARRAY_SIZE(test_regs); i++) for (j =3D 0; test_regs[i].ftr_bits[j].type !=3D FTR_END; j++) - test_cnt++; + test_cnt +=3D 2; =20 ksft_set_plan(test_cnt); =20 --=20 2.47.3 From nobody Mon Apr 6 21:35:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61BF63644BF; Tue, 17 Mar 2026 20:10:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 17 Mar 2026 20:10:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773778259; bh=qjkFp7iedLQabJArWZg6nyU9Z143fBvz+MFdJAqkGlM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tqJUDj6rO/LGK7GVYF+91XYOBql5Ztf6MyAdEfZQHE2CfI4D8sdlJIj5mYnyIg2Gl +Mc98qAmeEIC8uuVLY0C19YePAD4n+MlZdbgLLaiZG9TqsZHoB/fwkuQNlxvVcD+gO Ms5EOxgQd70CnBg3b+eSsrMP1MJXwQD+0DfywB8DRiPKJzJ8bnAcnI4c2AIo9246TR oYL4u0FK3FvoIfYMpHb/OotVImaavNY7vcD11+a05se7TGmGgHwwv0TktDaN0+q/9K xfX7HNZy1xd+g+9eQBe7o7EfZiB4p0b5FYp9lViMqIfaIo8q2FiPkwzbfyLNIS3h/f 1YXRJkpJ90nRw== From: Mark Brown Date: Tue, 17 Mar 2026 20:10:37 +0000 Subject: [PATCH v5 4/5] KVM: selftests: arm64: Skip all 32 bit IDs when set_id_regs is aarch64 only Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-kvm-arm64-set-id-regs-aarch64-v5-4-a60f2b956e22@kernel.org> References: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> In-Reply-To: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> To: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , Oliver Upton Cc: Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-e1b5b X-Developer-Signature: v=1; a=openpgp-sha256; l=4946; i=broonie@kernel.org; h=from:subject:message-id; bh=qjkFp7iedLQabJArWZg6nyU9Z143fBvz+MFdJAqkGlM=; b=owEBbAGT/pANAwAKASTWi3JdVIfQAcsmYgBpubVDktHRSlwlVT903e0/pOLpvx0ys9JhXg47v QuIf/MPKsyJATIEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCabm1QwAKCRAk1otyXVSH 0M11B/iz341VPB5PCi1SkyWMy1du5Nzj1+xuY1MbAO3o/MONJUl3IYIhre4IAW3FhH4kxe4SDzk iFATSQ9Ofau1hWnSFoudpMr5CrFmvj4Srume0rj66N32aGKHjUqQSrBEc06HDv1Jrfkf8jZM+tY g44gZnXuP5PDlMcpz0r1ddVpYrNDxXKoCuKPxKV1wAETKGRW7X039LirzhM+yPsU6LIOmE7R0cG GJ6cwou0h8OjHEbnDqXUU+tfWOitz/BSfw02hU5tOJQnpbF5+wl2W4ylz8ceohER70A0hWkOG2L Hf4T2uCCvDe1MaXiYT1KwXrIR+YOr2Iq58SNmz8okW47X78= X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB On an aarch64 only system the 32 bit ID registers have UNDEFINED values. As a result set_id_regs skips tests for setting fields in these registers when testing an aarch64 only guest. This has the side effect of meaning that we don't record an expected value for these registers, meaning that when the subsequent tests for values being visible in guests and preserved over reset check the value they can spuriously fail. This can be seen by running on an emulated system with both NV and 32 bit enabled, NV will result in the guests created by the test program being 64 bit only but the 32 bit ID registers will have values. Also skip those tests that use the values set in the field setting tests for aarch64 only guests in order to avoid these spurious failures. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 49 ++++++++++++++++++---= ---- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 60e7f0c1bc26..127defebb35a 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -294,6 +294,13 @@ static const char *get_reg_name(u64 id) } } =20 +static inline bool is_aarch32_id_reg(u64 id) +{ + return (sys_reg_Op0(id) =3D=3D 3 && sys_reg_Op1(id) =3D=3D 0 && + sys_reg_CRn(id) =3D=3D 0 && sys_reg_CRm(id) >=3D 1 && + sys_reg_CRm(id) <=3D 3); +} + /* Return a safe value to a given ftr_bits an ftr value */ uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr) { @@ -674,7 +681,7 @@ static void test_user_set_mte_reg(struct kvm_vcpu *vcpu) ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n"); } =20 -static void test_guest_reg_read(struct kvm_vcpu *vcpu) +static void test_guest_reg_read(struct kvm_vcpu *vcpu, bool aarch64_only) { bool done =3D false; struct ucall uc; @@ -693,6 +700,13 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu) reg_id =3D uc.args[2]; guest_val =3D uc.args[3]; expected_val =3D test_reg_vals[encoding_to_range_idx(reg_id)]; + + if (aarch64_only && is_aarch32_id_reg(reg_id)) { + ksft_test_result_skip("%s value seen in guest\n", + get_reg_name(reg_id)); + break; + } + match =3D expected_val =3D=3D guest_val; if (!match) ksft_print_msg("%lx !=3D %lx\n", @@ -784,12 +798,19 @@ static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu= *vcpu) ksft_test_result_pass("%s\n", __func__); } =20 -static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t e= ncoding) +static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t e= ncoding, + bool aarch64_only) { size_t idx =3D encoding_to_range_idx(encoding); uint64_t observed; bool pass; =20 + if (aarch64_only && is_aarch32_id_reg(encoding)) { + ksft_test_result_skip("%s unchanged by reset\n", + get_reg_name(encoding)); + return; + } + observed =3D vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding)); pass =3D test_reg_vals[idx] =3D=3D observed; if (!pass) @@ -800,7 +821,8 @@ static void test_assert_id_reg_unchanged(struct kvm_vcp= u *vcpu, uint32_t encodin =20 #define ID_REG_RESET_UNCHANGED_TEST (ARRAY_SIZE(test_regs) + 6) =20 -static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu) +static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu, + bool aarch64_only) { /* * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an @@ -809,14 +831,15 @@ static void test_reset_preserves_id_regs(struct kvm_v= cpu *vcpu) aarch64_vcpu_setup(vcpu, NULL); =20 for (int i =3D 0; i < ARRAY_SIZE(test_regs); i++) - test_assert_id_reg_unchanged(vcpu, test_regs[i].reg); - - test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1); - test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1); - test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0); - test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1); - test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1); - test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1); + test_assert_id_reg_unchanged(vcpu, test_regs[i].reg, + aarch64_only); + + test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1, aarch64_only); + test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1, aarch64_only); + test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0, aarch64_only); + test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1, aarch64_only); + test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1, aarch64_only); + test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1, aarch64_only); } =20 int main(void) @@ -858,9 +881,9 @@ int main(void) test_user_set_mpam_reg(vcpu); test_user_set_mte_reg(vcpu); =20 - test_guest_reg_read(vcpu); + test_guest_reg_read(vcpu, aarch64_only); =20 - test_reset_preserves_id_regs(vcpu); + test_reset_preserves_id_regs(vcpu, aarch64_only); =20 kvm_vm_free(vm); =20 --=20 2.47.3 From nobody Mon Apr 6 21:35:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 463F737B00F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tlJk2j2M" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7ABEDC2BCB1; Tue, 17 Mar 2026 20:10:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773778261; bh=fAVZD87pbrERscO5EBbL4UXt/gj+nHPQY7XsvwsyJC0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tlJk2j2MzYJvID+dpbCh1navkrRurTQmiczQjaillDfWg6ARn3tyVFuZE0uCDs7Nr 1Og1m41DWMpp7Ob8Mf+wC2A4HwTnFY+tHBbiM++QXHSrTQsZpOsxmQtzPWA06mcUFy 9gaaQBNQa17NHxSRA7V4coDfIPaFD91Jg1Dfnw8sVEBXWdpM+vFGNKI00WSF9bbk/c hcpzZIZOzR4bdeKnB41pK//HsMwBvLU1xII/Mo2pkGFE+eFjd7VdWIsadC3TxiUi92 VrL56TROCKFlbC3kjADqiRifxwt5WSmLcbL3p42VcCyzKsK6CqpAbn8bo5F6m5P0WB bu8Q7RBAjyFVw== From: Mark Brown Date: Tue, 17 Mar 2026 20:10:38 +0000 Subject: [PATCH v5 5/5] KVM: selftests: arm64: Use is_aarch32_id_reg() in test_vm_ftr_id_regs() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-kvm-arm64-set-id-regs-aarch64-v5-5-a60f2b956e22@kernel.org> References: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> In-Reply-To: <20260317-kvm-arm64-set-id-regs-aarch64-v5-0-a60f2b956e22@kernel.org> To: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Paolo Bonzini , Shuah Khan , Oliver Upton Cc: Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-e1b5b X-Developer-Signature: v=1; a=openpgp-sha256; l=1148; i=broonie@kernel.org; h=from:subject:message-id; bh=fAVZD87pbrERscO5EBbL4UXt/gj+nHPQY7XsvwsyJC0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpubVEYd+aI9Wa+jg3Mcnf1FBheli96NlRfce8t XvXHerjELyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCabm1RAAKCRAk1otyXVSH 0EhzB/9K4jNR0iqFUOb78qCy2x/wNhKRW0krzdRLgpZt5kJiumqyovOYWOyNkcw5uTqDRZkasqj Flags4TK84CeWQ9JlTbSFDbBS9nDJ7pG8RnBlkjHfisWibJKEfa2g593d1DJpO/VHnXbm3sB+u5 YKMfcYlFZjUi4TSOGNgbFsEWTMW+oSvqStZIjubMQjCSRQBcbUDE+RQkm7v7RwcIm/SFcfCFamz c+a8axfpP9fCLJC+y8sDmUOTj8935NnNo7+1y+SYja73ZnJQeITdXdu4CMe0aj9/RS29x5MRqQ3 2b4FsxaEDnbfd6tHnjbGV0sSZ2JugFleYWSukuogEMO02HpS X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB test_vm_ftr_id_regs() uses a simplified check for 32 bit ID registers since it knows it will only run on ID registers. For clarity update this to use the newly added is_aarch32_id_reg(), there should be no functional change. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 127defebb35a..50e9e9b6a365 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -502,7 +502,7 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, = bool aarch64_only) =20 for (int j =3D 0; ftr_bits[j].type !=3D FTR_END; j++) { /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */ - if (aarch64_only && sys_reg_CRm(reg_id) < 4) { + if (aarch64_only && is_aarch32_id_reg(reg_id)) { ksft_print_msg("%s on AARCH64 only system\n", ftr_bits[j].name); ksft_test_result_skip("%s invalid write rejected\n", --=20 2.47.3