From nobody Tue Apr 7 02:38:47 2026 Received: from www3579.sakura.ne.jp (www3579.sakura.ne.jp [49.212.243.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA0842D8DCF; Tue, 17 Mar 2026 06:38:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=49.212.243.89 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773729492; cv=none; b=uFO/3aY9c/TW0jdTlnbM+Z0kscAXayGcS5TvC4N3+xvk3tXpxA1i3r9Gc+PFnjjO4LViNkoLrNk+fYRkSTGtj/vJkwinwJtYM6WOkSC62dHTgZW7rz+JuLxEGydtdJJU0SG2aIVPz5JeXNIVC+i028RYM1LnZ1r9OJzvc277ZGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773729492; c=relaxed/simple; bh=6pigEJb6MjU5WOzv3cHoV2MRbx3gnmposFMAjl091HA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jucIHvj5PIcth8ngUZTkEyE2N7ZFyvDB3+A49L+25zXy4E1ZfP58V6RFePnQiUmrxg3JuzReFPuZc65+5d6eaymsp4ofm0jUb4C3LQWuYvuweo0FTDljkU2KIkayDSPFsQxk2OZi/WedfeuNyd1zch/MYEnfcgNQFeYHin9vykk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp; dkim=fail (0-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b=Uv38ahS0 reason="key not found in DNS"; arc=none smtp.client-ip=49.212.243.89 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rsg.ci.i.u-tokyo.ac.jp Authentication-Results: smtp.subspace.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=rsg.ci.i.u-tokyo.ac.jp header.i=@rsg.ci.i.u-tokyo.ac.jp header.b="Uv38ahS0" Received: from h205.csg.ci.i.u-tokyo.ac.jp (h205.csg.ci.i.u-tokyo.ac.jp [133.11.54.205]) (authenticated bits=0) by www3579.sakura.ne.jp (8.16.1/8.16.1) with ESMTPSA id 62H6aoNl004343 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 17 Mar 2026 15:37:00 +0900 (JST) (envelope-from odaki@rsg.ci.i.u-tokyo.ac.jp) DKIM-Signature: a=rsa-sha256; bh=Vpu164nWx4WQH4ej/oGZKppmfZaoPsbjbattGAiYgSg=; c=relaxed/relaxed; d=rsg.ci.i.u-tokyo.ac.jp; h=From:Message-Id:To:Subject:Date; s=rs20250326; t=1773729421; v=1; b=Uv38ahS0027vqQrbNp5ZXxqFQJvRmc6zUg9PFzYvYXNYliRYhrmFcZqez911WSTt YU8glRax61lZJrhDsMgPp8n07hqRkpqTbop74N4FLPE7dvMCz8MowA8r4mALFVsO JGxcOisqxHRHL/++Ft1vC3ztegZmSIsu65KH0sBBAiCTzo5VQbEbdYh/vFljChNf 10/G+rd9RyrEaBDP27L5GmSCyjcVrdwp3L48ejT9N3fVaGgcDHt35bj3BEfO1ZCe ySAt1VbtwJXS5bKI9CT3i/P0BcIpRCSkl8TBS1aZPj97/9wj6wCFUGF5Ip4r7ZwW aoVywVNUh42j4C8eys+HQg== From: Akihiko Odaki Date: Tue, 17 Mar 2026 15:36:49 +0900 Subject: [PATCH v4 1/4] KVM: arm64: PMU: Add kvm_pmu_enabled_counter_mask() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-hybrid-v4-1-bd62bcd48644@rsg.ci.i.u-tokyo.ac.jp> References: <20260317-hybrid-v4-0-bd62bcd48644@rsg.ci.i.u-tokyo.ac.jp> In-Reply-To: <20260317-hybrid-v4-0-bd62bcd48644@rsg.ci.i.u-tokyo.ac.jp> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Kees Cook , "Gustavo A. R. Silva" , Paolo Bonzini , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, devel@daynix.com, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Akihiko Odaki X-Mailer: b4 0.15-dev-5ab4c This function will be useful to enumerate enabled counters. Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index b03dbda7f1ab..59ec96e09321 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -619,18 +619,24 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 v= al) } } =20 -static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc) +static u64 kvm_pmu_enabled_counter_mask(struct kvm_vcpu *vcpu) { - struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); - unsigned int mdcr =3D __vcpu_sys_reg(vcpu, MDCR_EL2); + u64 mask =3D 0; =20 - if (!(__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(pmc->idx))) - return false; + if (__vcpu_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_HPME) + mask |=3D kvm_pmu_hyp_counter_mask(vcpu); =20 - if (kvm_pmu_counter_is_hyp(vcpu, pmc->idx)) - return mdcr & MDCR_EL2_HPME; + if (kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) + mask |=3D ~kvm_pmu_hyp_counter_mask(vcpu); + + return __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; +} + +static bool kvm_pmu_counter_is_enabled(struct kvm_pmc *pmc) +{ + struct kvm_vcpu *vcpu =3D kvm_pmc_to_vcpu(pmc); =20 - return kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E; + return kvm_pmu_enabled_counter_mask(vcpu) & BIT(pmc->idx); } =20 static bool kvm_pmc_counts_at_el0(struct kvm_pmc *pmc) --=20 2.53.0