From nobody Mon Apr 6 23:37:42 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 272D33F6613 for ; Tue, 17 Mar 2026 17:14:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773767699; cv=none; b=CiYpyKubPAjWkTPE3W4ekBA4fSXHZglr5DyKQA1akXF4XrnR7TfssTLuPEQnCzGfcCildZIygGOrPqnItN2/ne8dYKts6Nzj4x+CIeXKymON8CQfjOIdQbaT5IPdX5hmgBY9fcG/Um7h2SzDV9E6nhpEiLhdnIourWcJAUrPMk8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773767699; c=relaxed/simple; bh=4pHAiCPa/I4+70l4WTTxBfo7ZLYJXjIsYdQ2M+8BWJg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cWhSPaDR//2Ybwxl75u/A/OZy19UVR/YPrJKXeVnYMmZdUdp8zf43LE7BoYAwD4MvwKBMGNeoNeSeLwZVJzZPOjBWkp1oD4zmp/26qiwfnilr6TdCOMaccQk0pIdDt/l5CuEwNHg8ixhsTjwOZR4MwnuoKrTMdsmRCbEFEaBnCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=eyKXgEM0; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=h730Q+l7; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="eyKXgEM0"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="h730Q+l7" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62HD50Uk668972 for ; Tue, 17 Mar 2026 17:14:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= yB6RmntczqRFUMYtWGGfsH29TNbbMgoNZLAW4MMdSzo=; b=eyKXgEM0zh7blzXR SHJm3B+Mn799uS8qpnMberp7gCI+VvfvCiEzMVhovFwnjIbYYqF6HX0ygmAQ8t7A rGedOd7x0B96e/LwdClJwthk0ybiLp82Ph0mK7Lk57WERIsqqMfylT0AORBuFq7s MdW+ZCQ1s2QI0P5KOI70te7hWZ/rdf1Xom0g0xspnYu7DluUnM5xK/P0qRQc0oe3 rLOZOYoQpjKP59F6geaEq7rDxng9CIJleW8dJ+4RR0F1+8t7Z+4b0RPlXNFPlPB9 QCjhN03fAHm8fuFuLqm0sKaaGU3/09q0ir8YKUre08eVwVa1XHNabo4yiQurZot6 H/Q/yw== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cy7he10eq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 17 Mar 2026 17:14:57 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-359fe456655so5344823a91.3 for ; Tue, 17 Mar 2026 10:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773767696; x=1774372496; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yB6RmntczqRFUMYtWGGfsH29TNbbMgoNZLAW4MMdSzo=; b=h730Q+l72ITONiELt9Y5q6Du0WvHdKagrUbX5JcHWc+7poTKRlZf7rqXV8tzqUq37E /01i0svXAvulfJG/rdiHxNRMMWcXSe+lrvqj1Khi0quXdR26cEimTRNp8rQqm9Epl6xz Jcifgu4NpwNyYjipaCd//JlKxXaA7kXGMtYwTfbDW9bSsoZsllsTJZdL4J0iyJR1xhm+ QRxkvS4PBwIhWhzGV7TKypCKXOhmB0rNmqMYfr5o6o2/xc/B+167MxipSw/Y1Awh6JX6 GkcgONltTAQ4WAgrIoC3t7czvPPYHhI6rzPU9p7SHQBb2MLch8Fu7Uc3CcSBaW7m4S39 8KXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773767696; x=1774372496; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=yB6RmntczqRFUMYtWGGfsH29TNbbMgoNZLAW4MMdSzo=; b=XWratFQQIBpZ+E+dtuDf37Ka7AjRuq/Mj8TIBo+JNFfU0XgoZFau/n6gMqsS3SH13M aebrvNtHiQXEAzsopTAPm6kQA2mBWNUhmNEx6A9OMRvHgKE9478Vc3pt11N4BvgAHyiy 9CiCp3s/y/blSuzKAtGqpeYZBSAHDEuPMK/D+u0/rX6Q6CXFolPzc+mNHZ5dTUFxmtRW jKxk9cXBQpdTYO/2dWkd1Ps5NFH3h7pGRuzqtj/yPFlMgLnUPGbHJwo5axiD6WFltFp6 y1GwdZDRb+1rk08n/idL3t5fUpYS/WiemV97kT/TfzXpa7zE6jRQC3Tz6lR/5JQkArog dAzA== X-Forwarded-Encrypted: i=1; AJvYcCXDvJxcJ4N/zZdDQtNj8jDq10qVnESLPN4SfYQISzVVRys2OtDXWOhHgrBAXtagd3I3yJQipo0M9fp9YAo=@vger.kernel.org X-Gm-Message-State: AOJu0Yw8nFW76OgQ+/vssxcDrYTu4HSXgJwf4ss9uoZ4/XrghkRjBpMt TFcml4HiK3laXQDpM86Nyh/bqx+BkDj+Zl/DRR2WIm67CnuRYFm+xuRfDgEkU1KYefwDDO34BDr heDw/d6Ff7YhzKoplFPfjyP/JRlYv5LyKcKLhY/bx/g6N5TffT8qA3DhEuPD45xRV99w= X-Gm-Gg: ATEYQzyyCKufi01SemWkMGKx3OCPRChHN0cnn4xkP2K5ms1XneaqEtJ66uEjGPBrppr 6JtX0wPyVFUA1mxI+qR/SAWDO/cZft2ZGAMVj1Kz5kmX9fYcBJNxbaYXcpgmEY15HRdu2hMDguI /FG1E+TUonFLfvwribMYC3Y/eFILlPPqvVQMt5vkY39iDAo4/eMvDSwo07FYRCPojJj9xtMrtwL qeFFpTRiUPPhWvdG/7xCbwWBbnfxEyXf7Yu2ckB208vmzbyqZix9W2d+DUhWD3qyFjYdf/jaXi5 W46BVdkOZYc8d7zVSb0QA+AYt7zTKLEhZAaWi6l02o5F6W0AntnaXwG17YqZGHn8xLYvDH48Sy9 3oxXP1M5hVA39lBXOfHdjw5bJisgNAE+NRgzSH0lLRRTWrg== X-Received: by 2002:a17:90b:2f84:b0:359:8c01:674 with SMTP id 98e67ed59e1d1-35bb9ef5f24mr191409a91.22.1773767695183; Tue, 17 Mar 2026 10:14:55 -0700 (PDT) X-Received: by 2002:a17:90b:2f84:b0:359:8c01:674 with SMTP id 98e67ed59e1d1-35bb9ef5f24mr191376a91.22.1773767694568; Tue, 17 Mar 2026 10:14:54 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35bb9f1cb48sm28919a91.0.2026.03.17.10.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 10:14:54 -0700 (PDT) From: Taniya Das Date: Tue, 17 Mar 2026 22:44:23 +0530 Subject: [PATCH 2/7] dt-bindings: clock: qcom: document the Eliza GPU Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-eliza_mm_clock_controllers_v1-v1-2-4696eeda8cfb@oss.qualcomm.com> References: <20260317-eliza_mm_clock_controllers_v1-v1-0-4696eeda8cfb@oss.qualcomm.com> In-Reply-To: <20260317-eliza_mm_clock_controllers_v1-v1-0-4696eeda8cfb@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Vladimir Zapolskiy Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: FfmGgiW96-dC0hrJfY59kO6uoOfdUDrf X-Proofpoint-ORIG-GUID: FfmGgiW96-dC0hrJfY59kO6uoOfdUDrf X-Authority-Analysis: v=2.4 cv=QsVTHFyd c=1 sm=1 tr=0 ts=69b98c11 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=eqSiwPykCNIpSPSkj8oA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDE1MiBTYWx0ZWRfX5hV0oWbuDQtY o+wrJTSc59hMo9fer+mUnz500whxx50KMd6YqmvedHl5/OJi8sLdH50cxZdfLL9lSUtHOTp16FF TJeKn+q6jgbqHcpcmaVBe9uBPIwPcvBAnAGdykBq/+lJD7DRPC1cNr77Ha9ThB4/cNCom8Fcc+b YZYA4E1RZbwjEZeRX+O7kCHDlg99vfr40VgrHb3APgri9uOI50cbiVBYix83hRI4pMoiS+sG03c zSUDHiWeAZWt2q3ViasYV8LM7/WCjc1lFqKpA6KS9bJjkkTifDJFdWyUOZENjnSsARvD6bbVwcG UWkbtsONgl5OZTtEwwSmfGtHKo/+8ig37f/psvObSv7Sbu94wy52YBCGyy15T9JD0iFqkPdNSPC H6qsAxQmDb0LdI5A4EwKE1D2mlhUA1HacZavyfwMqJpA3EULBDJP2LQCf+fSV50NZI8LWT6HP4i 2/1eGdtx3WuXyxLoE6A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_03,2026-03-17_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170152 Add bindings documentation for the Eliza Graphics Clock Controller. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 3 ++ include/dt-bindings/clock/qcom,eliza-gpucc.h | 52 ++++++++++++++++++= ++++ 2 files changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index fdbdf605ee695637512ce4f98c9b6fcfacb9154f..734bab762a30800bda94c726f48= 013679f9ec542 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -15,6 +15,7 @@ description: | domains on Qualcomm SoCs. =20 See also: + include/dt-bindings/clock/qcom,eliza-gpucc.h include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h @@ -30,6 +31,7 @@ description: | properties: compatible: enum: + - qcom,eliza-gpucc - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc @@ -71,6 +73,7 @@ allOf: compatible: contains: enum: + - qcom,eliza-gpucc - qcom,sm8750-gpucc then: required: diff --git a/include/dt-bindings/clock/qcom,eliza-gpucc.h b/include/dt-bind= ings/clock/qcom,eliza-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..706e1c93240a8234dd8017ee181= d19e58091fd6d --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-gpucc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_ELIZA_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_DEMET_CLK 7 +#define GPU_CC_DEMET_DIV_CLK_SRC 8 +#define GPU_CC_FF_CLK_SRC 9 +#define GPU_CC_FREQ_MEASURE_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GPU_SMMU_VOTE_CLK 12 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 13 +#define GPU_CC_HUB_AON_CLK 14 +#define GPU_CC_HUB_CLK_SRC 15 +#define GPU_CC_HUB_CX_INT_CLK 16 +#define GPU_CC_MEMNOC_GFX_CLK 17 +#define GPU_CC_MND1X_0_GFX3D_CLK 18 +#define GPU_CC_MND1X_1_GFX3D_CLK 19 +#define GPU_CC_PLL0 20 +#define GPU_CC_PLL1 21 +#define GPU_CC_SLEEP_CLK 22 +#define GPU_CC_XO_CLK_SRC 23 +#define GPU_CC_XO_DIV_CLK_SRC 24 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_FF_BCR 4 +#define GPU_CC_GFX3D_AON_BCR 5 +#define GPU_CC_GMU_BCR 6 +#define GPU_CC_GX_BCR 7 +#define GPU_CC_RBCPR_BCR 8 +#define GPU_CC_XO_BCR 9 + +#endif --=20 2.34.1