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Signed-off-by: Maya Matuszczyk Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Reviewed-by: Krzysztof Kozlowski --- .../embedded-controller/qcom,hamoa-crd-ec.yaml | 56 ++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,ham= oa-crd-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom= ,hamoa-crd-ec.yaml new file mode 100644 index 000000000000..ac5a08f8f76d --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-= ec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/qcom,hamoa-crd-ec.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hamoa Embedded Controller + +maintainers: + - Sibi Sankar + - Anvesh Jain P + +description: + Qualcomm Snapdragon based Hamoa/Purwa and Glymur reference devices have = an + EC running on different MCU chips. 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a07340518sm16654056b3a.34.2026.03.17.05.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2026 05:28:41 -0700 (PDT) From: Anvesh Jain P Date: Tue, 17 Mar 2026 17:57:56 +0530 Subject: [PATCH v5 2/5] platform: arm64: Add driver for EC found on Qualcomm reference devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260317-add-driver-for-ec-v5-2-38d11f524856@oss.qualcomm.com> References: <20260317-add-driver-for-ec-v5-0-38d11f524856@oss.qualcomm.com> In-Reply-To: <20260317-add-driver-for-ec-v5-0-38d11f524856@oss.qualcomm.com> To: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, Anvesh Jain P , Maya Matuszczyk , Dmitry Baryshkov X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773750505; l=17183; i=anvesh.p@oss.qualcomm.com; s=20260313; h=from:subject:message-id; bh=yGcWYwhNcIQAFC7YddHUz0BJM5u00MPnO14ptGEVK00=; b=9HG71fL/Jy0ggDzuoW223nD3DKsSLYgZznZDsM28dWqzxt43nPEU/hHiMCfQP2KUL1n8SXNPX hxfe08mBzMyCbsbi47ySC/rermio66TmXBCIeCASRrEhvixro9nYz/D X-Developer-Key: i=anvesh.p@oss.qualcomm.com; a=ed25519; pk=8o9EG7gkPe2Er9y9UVCx8MTdcFCwU8Pa54hBZPuduXE= X-Proofpoint-GUID: yTLAJwTDQ1g9vI1cR8etpd41oWQrtQPd X-Proofpoint-ORIG-GUID: yTLAJwTDQ1g9vI1cR8etpd41oWQrtQPd X-Authority-Analysis: v=2.4 cv=KLxXzVFo c=1 sm=1 tr=0 ts=69b948fb cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=E2FcRaxJAAAA:8 a=689zGLOwWasileE73dUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=Yev8HTsh1NrKSfoOyGCL:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDEwOSBTYWx0ZWRfX40kCtyX/TpE/ DJJz2EMxCdiJQOLSvY3ZtVEvHG/+QCVReQFDXhmXz7zBu7LPyY+1HZdvkmuKvoRTwSRf+5M5mca TBJDY3pop39CuN8RQFu+Jm1tEZiqjX1p8qZQYNImRhsG+iibPm7BUzCNM1gBohk1Ip9qqrHBw2z KrGuzfCWVXgcwpUtszLZHc9T/cSC52/XR4JCRvMFO3FdtJXCzV0z+YPPaYbmSDa0HToBZuxSyDO 5dRvO5LWm7vCxCWQ5ZpCFXMOlzo1ZN7hMCllAWzSh85x4VemVZOA1ZeopIi0TBkp0lB5FgMGeQq p7hZzCN66dkMyvkkywFCrSOhc2+t25dNDjJ8NDHmpyiFDc+/Rrawgk3p3fJRtptTg66v1+gz+jb F75UieEPx14rG1ZInrvsNIPrC6at3F75QYUhI2XxNw2VNe2yehJcvVC6U38XABH8Cah06Gmhpwr JxkJT0bfN3GqcY3gx7Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_01,2026-03-17_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170109 From: Sibi Sankar Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm reference boards. It handles fan control, temperature sensors, access to EC state changes and supports reporting suspend entry/exit to the EC. Co-developed-by: Maya Matuszczyk Signed-off-by: Maya Matuszczyk Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Acked-by: Konrad Dybcio --- MAINTAINERS | 8 + drivers/platform/arm64/Kconfig | 12 + drivers/platform/arm64/Makefile | 1 + drivers/platform/arm64/qcom-hamoa-ec.c | 449 +++++++++++++++++++++++++++++= ++++ 4 files changed, 470 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2882a67bdf6d..9657c384be44 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21932,6 +21932,14 @@ S: Supported W: https://wireless.wiki.kernel.org/en/users/Drivers/wcn36xx F: drivers/net/wireless/ath/wcn36xx/ =20 +QUALCOMM HAMOA EMBEDDED CONTROLLER DRIVER +M: Sibi Sankar +M: Anvesh Jain P +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml +F: drivers/platform/arm64/qcom-hamoa-ec.c + QUANTENNA QTNFMAC WIRELESS DRIVER M: Igor Mitsyanko R: Sergey Matyukevich diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig index 10f905d7d6bf..025cdf091f9e 100644 --- a/drivers/platform/arm64/Kconfig +++ b/drivers/platform/arm64/Kconfig @@ -90,4 +90,16 @@ config EC_LENOVO_THINKPAD_T14S =20 Say M or Y here to include this support. =20 +config EC_QCOM_HAMOA + tristate "Embedded Controller driver for Qualcomm Hamoa/Glymur reference = devices" + depends on ARCH_QCOM || COMPILE_TEST + depends on I2C + help + Say M or Y here to enable the Embedded Controller driver for Qualcomm + Snapdragon-based Hamoa/Glymur reference devices. The driver handles fan + control, temperature sensors, access to EC state changes and supports + reporting suspend entry/exit to the EC. + + This driver currently supports Hamoa/Purwa/Glymur reference devices. + endif # ARM64_PLATFORM_DEVICES diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makef= ile index 60c131cff6a1..7681be4a46e9 100644 --- a/drivers/platform/arm64/Makefile +++ b/drivers/platform/arm64/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_EC_ACER_ASPIRE1) +=3D acer-aspire1-ec.o obj-$(CONFIG_EC_HUAWEI_GAOKUN) +=3D huawei-gaokun-ec.o obj-$(CONFIG_EC_LENOVO_YOGA_C630) +=3D lenovo-yoga-c630.o obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) +=3D lenovo-thinkpad-t14s.o +obj-$(CONFIG_EC_QCOM_HAMOA) +=3D qcom-hamoa-ec.o diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm6= 4/qcom-hamoa-ec.c new file mode 100644 index 000000000000..0b0c1df19695 --- /dev/null +++ b/drivers/platform/arm64/qcom-hamoa-ec.c @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Maya Matuszczyk + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define EC_SCI_EVT_READ_CMD 0x05 +#define EC_FW_VERSION_CMD 0x0e +#define EC_MODERN_STANDBY_CMD 0x23 +#define EC_FAN_DBG_CONTROL_CMD 0x30 +#define EC_SCI_EVT_CONTROL_CMD 0x35 +#define EC_THERMAL_CAP_CMD 0x42 + +#define EC_FW_VERSION_RESP_LEN 4 +#define EC_THERMAL_CAP_RESP_LEN 3 +#define EC_FAN_DEBUG_CMD_LEN 6 +#define EC_FAN_SPEED_DATA_SIZE 4 + +#define EC_MODERN_STANDBY_ENTER 0x01 +#define EC_MODERN_STANDBY_EXIT 0x00 + +#define EC_FAN_DEBUG_MODE_OFF 0 +#define EC_FAN_DEBUG_MODE_ON BIT(0) +#define EC_FAN_ON BIT(1) +#define EC_FAN_DEBUG_TYPE_PWM BIT(2) +#define EC_MAX_FAN_CNT 2 +#define EC_FAN_NAME_SIZE 20 +#define EC_FAN_MAX_PWM 255 + +enum qcom_ec_sci_events { + EC_FAN1_STATUS_CHANGE_EVT =3D 0x30, + EC_FAN2_STATUS_CHANGE_EVT, + EC_FAN1_SPEED_CHANGE_EVT, + EC_FAN2_SPEED_CHANGE_EVT, + EC_NEW_LUT_SET_EVT, + EC_FAN_PROFILE_SWITCH_EVT, + EC_THERMISTOR_1_THRESHOLD_CROSS_EVT, + EC_THERMISTOR_2_THRESHOLD_CROSS_EVT, + EC_THERMISTOR_3_THRESHOLD_CROSS_EVT, + /* Reserved: 0x39 - 0x3c/0x3f */ + EC_RECOVERED_FROM_RESET_EVT =3D 0x3d, +}; + +struct qcom_ec_version { + u8 main_version; + u8 sub_version; + u8 test_version; +}; + +struct qcom_ec_thermal_cap { +#define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x))) +#define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x))) +#define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x))) + u8 fan_cnt; + u8 fan_type; + u8 thermistor_mask; +}; + +struct qcom_ec_cooling_dev { + struct thermal_cooling_device *cdev; + struct device *parent_dev; + u8 fan_id; + u8 state; +}; + +struct qcom_ec { + struct qcom_ec_cooling_dev *ec_cdev; + struct qcom_ec_thermal_cap thermal_cap; + struct qcom_ec_version version; + struct i2c_client *client; +}; + +static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp) +{ + int ret; + + ret =3D i2c_smbus_read_i2c_block_data(ec->client, cmd, resp_len, resp); + + if (ret < 0) + return ret; + else if (ret =3D=3D 0 || ret =3D=3D 0xff) + return -EOPNOTSUPP; + + if (resp[0] >=3D resp_len) + return -EINVAL; + + return 0; +} + +/* + * EC Device Firmware Version: + * + * Read Response: + * ---------------------------------------------------------------------- + * | Offset | Name | Description | + * ---------------------------------------------------------------------- + * | 0x00 | Byte count | Number of bytes in response | + * | | | (excluding byte count) | + * ---------------------------------------------------------------------- + * | 0x01 | Test-version | Test-version of EC firmware | + * ---------------------------------------------------------------------- + * | 0x02 | Sub-version | Sub-version of EC firmware | + * ---------------------------------------------------------------------- + * | 0x03 | Main-version | Main-version of EC firmware | + * ---------------------------------------------------------------------- + * + */ +static int qcom_ec_read_fw_version(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + struct qcom_ec_version *version =3D &ec->version; + u8 resp[EC_FW_VERSION_RESP_LEN]; + int ret; + + ret =3D qcom_ec_read(ec, EC_FW_VERSION_CMD, EC_FW_VERSION_RESP_LEN, resp); + if (ret < 0) + return ret; + + version->main_version =3D resp[3]; + version->sub_version =3D resp[2]; + version->test_version =3D resp[1]; + + dev_dbg(dev, "EC Version %d.%d.%d\n", + version->main_version, version->sub_version, version->test_version); + + return 0; +} + +/* + * EC Device Thermal Capabilities: + * + * Read Response: + * -----------------------------------------------------------------------= ------- + * | Offset | Name | Description | + * -----------------------------------------------------------------------= ------- + * | 0x00 | Byte count | Number of bytes in response | + * | | | (excluding byte count) | + * -----------------------------------------------------------------------= ------- + * | 0x02 (LSB) | EC Thermal | Bit 0-1: Number of fans | + * | 0x3 | Capabilities | Bit 2-4: Type of fan | + * | | | Bit 5-6: Reserved | + * | | | Bit 7: Data Valid/Invalid | + * | | | (Valid - 1, Invalid - 0) | + * | | | Bit 8-15: Thermistor 0 - 7 presence | + * | | | (1 present, 0 absent) | + * -----------------------------------------------------------------------= ------- + * + */ +static int qcom_ec_thermal_capabilities(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + struct qcom_ec_thermal_cap *cap =3D &ec->thermal_cap; + u8 resp[EC_THERMAL_CAP_RESP_LEN]; + int ret; + + ret =3D qcom_ec_read(ec, EC_THERMAL_CAP_CMD, EC_THERMAL_CAP_RESP_LEN, res= p); + if (ret < 0) + return ret; + + cap->fan_cnt =3D min(EC_MAX_FAN_CNT, EC_THERMAL_FAN_CNT(resp[1])); + cap->fan_type =3D EC_THERMAL_FAN_TYPE(resp[1]); + cap->thermistor_mask =3D EC_THERMAL_THERMISTOR_MASK(resp[2]); + + dev_dbg(dev, "Fan count: %d Fan Type: %d Thermistor Mask: %d\n", + cap->fan_cnt, cap->fan_type, cap->thermistor_mask); + + return 0; +} + +static irqreturn_t qcom_ec_irq(int irq, void *data) +{ + struct qcom_ec *ec =3D data; + struct device *dev =3D &ec->client->dev; + int val; + + val =3D i2c_smbus_read_byte_data(ec->client, EC_SCI_EVT_READ_CMD); + if (val < 0) { + dev_err_ratelimited(dev, "Failed to read EC SCI Event: %d\n", val); + return IRQ_HANDLED; + } + + switch (val) { + case EC_FAN1_STATUS_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan1 status changed\n"); + break; + case EC_FAN2_STATUS_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan2 status changed\n"); + break; + case EC_FAN1_SPEED_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan1 speed crossed low/high trip point\n"); + break; + case EC_FAN2_SPEED_CHANGE_EVT: + dev_dbg_ratelimited(dev, "Fan2 speed crossed low/high trip point\n"); + break; + case EC_NEW_LUT_SET_EVT: + dev_dbg_ratelimited(dev, "New LUT set\n"); + break; + case EC_FAN_PROFILE_SWITCH_EVT: + dev_dbg_ratelimited(dev, "FAN Profile switched\n"); + break; + case EC_THERMISTOR_1_THRESHOLD_CROSS_EVT: + dev_dbg_ratelimited(dev, "Thermistor 1 threshold crossed\n"); + break; + case EC_THERMISTOR_2_THRESHOLD_CROSS_EVT: + dev_dbg_ratelimited(dev, "Thermistor 2 threshold crossed\n"); + break; + case EC_THERMISTOR_3_THRESHOLD_CROSS_EVT: + dev_dbg_ratelimited(dev, "Thermistor 3 threshold crossed\n"); + break; + case EC_RECOVERED_FROM_RESET_EVT: + dev_dbg_ratelimited(dev, "EC recovered from reset\n"); + break; + default: + dev_notice_ratelimited(dev, "Unknown EC event: %d\n", val); + break; + } + + return IRQ_HANDLED; +} + +static int qcom_ec_sci_evt_control(struct device *dev, bool enable) +{ + struct i2c_client *client =3D to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, EC_SCI_EVT_CONTROL_CMD, !!enable= ); +} + +static int qcom_ec_fan_get_max_state(struct thermal_cooling_device *cdev, = unsigned long *state) +{ + *state =3D EC_FAN_MAX_PWM; + + return 0; +} + +static int qcom_ec_fan_get_cur_state(struct thermal_cooling_device *cdev, = unsigned long *state) +{ + struct qcom_ec_cooling_dev *ec_cdev =3D cdev->devdata; + + *state =3D ec_cdev->state; + + return 0; +} + +/* + * Fan Debug control command: + * + * Command Payload: + * -----------------------------------------------------------------------= --------------- + * | Offset | Name | Description | + * -----------------------------------------------------------------------= --------------- + * | 0x00 | Command | Fan control command | + * -----------------------------------------------------------------------= --------------- + * | 0x01 | Fan ID | 0x1 : Fan 1 | + * | | | 0x2 : Fan 2 | + * -----------------------------------------------------------------------= --------------- + * | 0x02 | Byte count =3D 4| Size of data to set fan speed | + * -----------------------------------------------------------------------= --------------- + * | 0x03 | Mode | Bit 0: Debug Mode On/Off (0 - OFF, 1 - ON ) | + * | | | Bit 1: Fan On/Off (0 - Off, 1 - ON) | + * | | | Bit 2: Debug Type (0 - RPM, 1 - PWM) | + * -----------------------------------------------------------------------= --------------- + * | 0x04 (LSB) | Speed in RPM | RPM value, if mode selected is RPM | + * | 0x05 | | | + * -----------------------------------------------------------------------= --------------- + * | 0x06 | Speed in PWM | PWM value, if mode selected is PWM (0 - 255) | + * _______________________________________________________________________= _______________ + * + */ +static int qcom_ec_fan_debug_mode_off(struct qcom_ec_cooling_dev *ec_cdev) +{ + struct device *dev =3D ec_cdev->parent_dev; + struct i2c_client *client =3D to_i2c_client(dev); + u8 request[6] =3D { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE, + EC_FAN_DEBUG_MODE_OFF, 0, 0, 0 }; + int ret; + + ret =3D i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD, + sizeof(request), request); + if (ret) + dev_err(dev, "Failed to turn off fan%d debug mode: %d\n", + ec_cdev->fan_id, ret); + + return ret; +} + +static int qcom_ec_fan_set_cur_state(struct thermal_cooling_device *cdev, = unsigned long state) +{ + struct qcom_ec_cooling_dev *ec_cdev =3D cdev->devdata; + struct device *dev =3D ec_cdev->parent_dev; + struct i2c_client *client =3D to_i2c_client(dev); + + u8 request[6] =3D { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE, + EC_FAN_DEBUG_MODE_ON | EC_FAN_ON | EC_FAN_DEBUG_TYPE_PWM, + 0, 0, state }; + int ret; + + ret =3D i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD, + sizeof(request), request); + if (ret) { + dev_err(dev, "Failed to set fan pwm: %d\n", ret); + return ret; + } + + ec_cdev->state =3D state; + + return 0; +} + +static const struct thermal_cooling_device_ops qcom_ec_thermal_ops =3D { + .get_max_state =3D qcom_ec_fan_get_max_state, + .get_cur_state =3D qcom_ec_fan_get_cur_state, + .set_cur_state =3D qcom_ec_fan_set_cur_state, +}; + +static int qcom_ec_resume(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD, + EC_MODERN_STANDBY_ENTER); +} + +static int qcom_ec_suspend(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + + return i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD, + EC_MODERN_STANDBY_EXIT); +} + +static int qcom_ec_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct qcom_ec *ec; + int ret, i; + + ec =3D devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + ec->client =3D client; + + ret =3D devm_request_threaded_irq(dev, client->irq, NULL, qcom_ec_irq, + IRQF_ONESHOT, "qcom_ec", ec); + if (ret < 0) + return ret; + + i2c_set_clientdata(client, ec); + + ret =3D qcom_ec_read_fw_version(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read EC firmware version\n"); + + ret =3D qcom_ec_sci_evt_control(dev, true); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable SCI events\n"); + + ret =3D qcom_ec_thermal_capabilities(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n"); + + if (ec->thermal_cap.fan_cnt =3D=3D 0) { + dev_warn(dev, FW_BUG "Failed to get fan count, firmware update required\= n"); + return 0; + } + + ec->ec_cdev =3D devm_kcalloc(dev, ec->thermal_cap.fan_cnt, sizeof(*ec->ec= _cdev), GFP_KERNEL); + if (!ec->ec_cdev) + return -ENOMEM; + + for (i =3D 0; i < ec->thermal_cap.fan_cnt; i++) { + struct qcom_ec_cooling_dev *ec_cdev =3D &ec->ec_cdev[i]; + char name[EC_FAN_NAME_SIZE]; + + snprintf(name, EC_FAN_NAME_SIZE, "qcom_ec_fan_%u", (unsigned int)i); + ec_cdev->fan_id =3D i + 1; + ec_cdev->parent_dev =3D dev; + + ec_cdev->cdev =3D devm_thermal_of_cooling_device_register(dev, + NULL, + name, + ec_cdev, + &qcom_ec_thermal_ops); + if (IS_ERR(ec_cdev->cdev)) + return dev_err_probe(dev, PTR_ERR(ec_cdev->cdev), + "Failed to register fan%d cooling device\n", i); + } + + return 0; +} + +static void qcom_ec_remove(struct i2c_client *client) +{ + struct qcom_ec *ec =3D i2c_get_clientdata(client); + struct device *dev =3D &client->dev; + int ret; + + ret =3D qcom_ec_sci_evt_control(dev, false); + if (ret < 0) + dev_err(dev, "Failed to disable SCI events: %d\n", ret); + + for (int i =3D 0; i < ec->thermal_cap.fan_cnt; i++) { + struct qcom_ec_cooling_dev *ec_cdev =3D &ec->ec_cdev[i]; + + qcom_ec_fan_debug_mode_off(ec_cdev); + } +} + +static const struct of_device_id qcom_ec_of_match[] =3D { + { .compatible =3D "qcom,hamoa-crd-ec" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_ec_of_match); + +static const struct i2c_device_id qcom_ec_i2c_id_table[] =3D { + { "qcom-hamoa-ec", }, + {} +}; +MODULE_DEVICE_TABLE(i2c, qcom_ec_i2c_id_table); + +static DEFINE_SIMPLE_DEV_PM_OPS(qcom_ec_pm_ops, + qcom_ec_suspend, + qcom_ec_resume); + +static struct i2c_driver qcom_ec_i2c_driver =3D { + .driver =3D { + .name =3D "qcom-hamoa-ec", + .of_match_table =3D qcom_ec_of_match, + .pm =3D &qcom_ec_pm_ops + }, + .probe =3D qcom_ec_probe, + .remove =3D qcom_ec_remove, + .id_table =3D qcom_ec_i2c_id_table, +}; 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Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 877945319012..ae24af25aa6d 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -367,6 +367,22 @@ vreg_l4h_e0_1p2: ldo4 { }; }; =20 +&i2c9 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + embedded-controller@76 { + compatible =3D "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ec_int_n_default>; + pinctrl-names =3D "default"; + }; +}; + &pcie3b { vddpe-3v3-supply =3D <&vreg_nvmesec>; =20 @@ -490,6 +506,12 @@ &tlmm { <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ =20 + ec_int_n_default: ec-int-n-state { + pins =3D "gpio66"; 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Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qco= m/x1-crd.dtsi index ded96fb43489..d523e7cea3ec 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1042,6 +1042,16 @@ eusb6_repeater: redriver@4f { =20 #phy-cells =3D <0>; }; + + embedded-controller@76 { + compatible =3D "qcom,hamoa-crd-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ec_int_n_default>; + pinctrl-names =3D "default"; + }; }; =20 &i2c7 { @@ -1485,6 +1495,12 @@ &tlmm { <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ =20 + ec_int_n_default: ec-int-n-state { + pins =3D "gpio66"; + function =3D "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins =3D "gpio70"; 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Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index 630642baa435..b3430424a052 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -799,6 +799,16 @@ eusb6_repeater: redriver@4f { pinctrl-0 =3D <&eusb6_reset_n>; pinctrl-names =3D "default"; }; + + embedded-controller@76 { + compatible =3D "qcom,hamoa-iot-evk-ec", "qcom,hamoa-crd-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ec_int_n_default>; + pinctrl-names =3D "default"; + }; }; =20 &i2c7 { @@ -1272,6 +1282,12 @@ right_tweeter: speaker@0,1 { }; =20 &tlmm { + ec_int_n_default: ec-int-n-state { + pins =3D "gpio66"; + function =3D "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins =3D "gpio70"; function =3D "gpio"; --=20 2.34.1