From nobody Tue Apr 7 04:36:40 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F39BD39B967 for ; Mon, 16 Mar 2026 13:33:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773667997; cv=none; b=KQBlFhwqWHeE93WyS8TYQIzkqHiE1+RdY0tn67JoThNSf3st0ZmBZi3rBFwI3C3l7Vajs8NNeLBeSes48wr/6ZdgqcRn1bvdYUtshg5ZntGrNU21yKALIBYKPEDW/u3IHMu7Ohd6y1e3t78aPsXv05mTgeO4YyatqvEztDqJvbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773667997; c=relaxed/simple; bh=ecqtaf7Do4ElxtKTnuGKZQz9EFVZ1CRcpGzEUQrCfZo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UOnWQCsYx2pCY3AWqNxiJf3BYZonB1/ZOZDPcf+59+oksKMk51AHZgvm/dvo2QxQXjHcNa5MKJziI7t/yoLZ+jap9M1CTig0fGKr+h+/t3eArHnVYFhgAAinR6Yw7iRLVPpPl0oYNCm3jOiC/EW7e5CSTmnKeSgscDfTnxPUX9Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=pzpl/P09; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="pzpl/P09" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-43b40fb7f95so1185913f8f.3 for ; Mon, 16 Mar 2026 06:33:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1773667994; x=1774272794; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6/BkmUQ2l+8tVuUtRTiufCnFCzRaYeuhvEfWVLz7aiM=; b=pzpl/P09blF59a4kBhmtiNt0RBr+IqtBQHqXHCQw9hLJVAuHPVM78FfPmOq+5sR1mN yMkkvIOVF3Hn2XafwcRvwzkNFmKhYdNXVOGA1WFwy7PPb0bQvCqTpK7/ljIvVs2GPI14 d64X/tsYse1zE9LdGOQsIs8uTW1s6N46Np6Tfc63mcB05zUjypSgRcdiqfjiHCvK9vt1 nU3LEanF6qnfhVe2NNvN6Rx4/IiHJ9uJgySi1GyGNQkTjIvHDP2t3BH4QL8znvLHBd7u Cm65ajYvEhmJlNMqcWp7de4k2oyJc2nCrnUMcAiYYVraSDwZaqa6ZRFvd08bpGiy9qdX cn7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773667994; x=1774272794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=6/BkmUQ2l+8tVuUtRTiufCnFCzRaYeuhvEfWVLz7aiM=; b=VvEPiVofTkHtgGM19KL5k0hGb3IZBGakmpUhbOPVblDWsaBFUjIQBhtqZgfCAzV/0W 8Xm8pgLH3ke/QzCA0jxf6pf8Evm8f1vtGiR+PxSnT4R4AfcCxFouFsaW4pAt+iTzoah1 1sdP20/N0Wc1ntPeLIRAMRPAPkFEINdGWMuADmdHDHmxiCFiZorcQKcRgPHXsUgyG15Q 74QB78q52nVzSadfv1ljDTTasjtq/vTKjdPNdqH7h42lUH3CUDLJvxDN2rSWOsqXV2aE 6VfqwFiYu3qUEZCzxbegxfPFX8KSfJRFBGu17FVcfLa5mM2yW0125JNUA2cnGzok6MD3 dwLA== X-Forwarded-Encrypted: i=1; AJvYcCWYDm7pKjgyY9D5M+xS273IU2o0zy2nLEMDirQaAtZ1fgewIRKL1N0H2KL8TpcvpZgfccKYc1dWVILN4EA=@vger.kernel.org X-Gm-Message-State: AOJu0Ywt7ryK6rKuzi81MlXwfnZYwp8fOpGJzgXJodRy5mnLpVPkDHi7 acrqQLgZnPnMJnRZAK9mp86Vo8pBCeCba1gcMYDPMVTb1ztq/m/n7ll/aKQV2C+03+k= X-Gm-Gg: ATEYQzyPmkXh/hwsAOgRXRPugK29A3zb/zUZqCNqe5cHu+LBQrnrgZc+bkJ5T1G3AMR NCYGJU4VfHpAyIM4qhm42QYgL1t+Pob5Yj4WGKyNDhsClfddCFgk2C0YHVVRUQx+hpS64qWmyE9 emohVSMDy/gtS6Sr1Awel0m7lEqz5oCGCgr4ZMgUoBau1uKox1PDLJfWtaAmUQBSB3vuOw4bl/D MvWf3551Zym8kbaS4JWYFFs1Sg/PxJMM4rVYxT36j1YP5m6q8LNT0xq3ZznXQ5KsLgZPcJPMN7W ORPBQP/UNPvcGPi4/oG/cci9+9URzqQfyF8VOjSNqU6CIyN/WOSHzlzYuzLobWkEieFoqaY1ze0 iX12VlwfAqQR6W+hxCRxQIpB0gb4RqwFbksrD4qqD9L+1XPGTLHNRxYJP6wRw7sGJCkCU7lDhK1 b6pJ2yfi9NKvapGEoHmU5MyoeDleS+IZUBpS4KIs1U1HnAOaiXIlcbRDby8yq9MmfMHnSamlPmB 3/PuZA= X-Received: by 2002:a05:600c:c049:b0:483:7903:c3b1 with SMTP id 5b1f17b1804b1-485566f7a35mr176544055e9.20.1773667994206; Mon, 16 Mar 2026 06:33:14 -0700 (PDT) Received: from claudiu-TUXEDO-InfinityBook-Pro-AMD-Gen9.. ([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:13 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Long Luu , Claudiu Beznea Subject: [PATCH v10 7/8] dmaengine: sh: rz-dmac: Add device_tx_status() callback Date: Mon, 16 Mar 2026 15:32:51 +0200 Message-ID: <20260316133252.240348-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L SCIFA driver uses dmaengine_prep_slave_sg() to enqueue DMA transfers and implements a timeout mechanism on RX to handle cases where a DMA transfer does not complete. The timeout is implemented using an hrtimer. In the hrtimer callback, dmaengine_tx_status() is called (along with dmaengine_pause()) to retrieve the transfer residue and handle incomplete DMA transfers. Add support for the device_tx_status() callback. Co-developed-by: Long Luu Signed-off-by: Long Luu Signed-off-by: Biju Das Co-developed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - adjusted the patch description - dropped contribution list for Claudiu Beznea - used Co-developed-by + SoB tags and included Long Luu in the contribution list as well - dropped the read of CRLA in rz_dmac_calculate_residue_bytes_in_vd() and use the copy from the calling function (rz_dmac_chan_get_residue()) Changes in v8: - populated engine->residue_granularity Changes in v7: - none Changes in v6: - s/byte/bytes in comment from rz_dmac_chan_get_residue() Changes in v5: - post-increment lmdesc in rz_dmac_get_next_lmdesc() to allow the next pointer to advance - use 'lmdesc->nxla !=3D crla' comparison instead of '!(lmdesc->nxla =3D=3D crla)' in rz_dmac_calculate_residue_bytes_in_vd() - in rz_dmac_calculate_residue_bytes_in_vd() use '++i >=3D DMAC_NR_LMDESC' to verify if the full lmdesc list was checked - drop rz_dmac_calculate_total_bytes_in_vd() and use desc->len instead - re-arranged comments so they span fewer lines and are wrapped to ~80 characters - use u32 for the residue value and the functions returning it - use u32 for the variables storing register values - fixed typos drivers/dma/sh/rz-dmac.c | 144 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 6bfa77844e02..4f6f9f4bacca 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -124,10 +124,12 @@ struct rz_dmac { * Registers */ =20 +#define CRTB 0x0020 #define CHSTAT 0x0024 #define CHCTRL 0x0028 #define CHCFG 0x002c #define NXLA 0x0038 +#define CRLA 0x003c =20 #define DCTRL 0x0000 =20 @@ -676,6 +678,145 @@ static void rz_dmac_device_synchronize(struct dma_cha= n *chan) rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_= no); } =20 +static struct rz_lmdesc * +rz_dmac_get_next_lmdesc(struct rz_lmdesc *base, struct rz_lmdesc *lmdesc) +{ + struct rz_lmdesc *next =3D ++lmdesc; + + if (next >=3D base + DMAC_NR_LMDESC) + next =3D base; + + return next; +} + +static u32 rz_dmac_calculate_residue_bytes_in_vd(struct rz_dmac_chan *chan= nel, u32 crla) +{ + struct rz_lmdesc *lmdesc =3D channel->lmdesc.head; + struct dma_chan *chan =3D &channel->vc.chan; + struct rz_dmac *dmac =3D to_rz_dmac(chan->device); + u32 residue =3D 0, i =3D 0; + + while (lmdesc->nxla !=3D crla) { + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + if (++i >=3D DMAC_NR_LMDESC) + return 0; + } + + /* Calculate residue from next lmdesc to end of virtual desc */ + while (lmdesc->chcfg & CHCFG_DEM) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } + + dev_dbg(dmac->dev, "%s: VD residue is %u\n", __func__, residue); + + return residue; +} + +static u32 rz_dmac_chan_get_residue(struct rz_dmac_chan *channel, + dma_cookie_t cookie) +{ + struct rz_dmac_desc *current_desc, *desc; + enum dma_status status; + u32 crla, crtb, i; + + /* Get current processing virtual descriptor */ + current_desc =3D list_first_entry(&channel->ld_active, + struct rz_dmac_desc, node); + if (!current_desc) + return 0; + + /* + * If the cookie corresponds to a descriptor that has been completed + * there is no residue. The same check has already been performed by the + * caller but without holding the channel lock, so the descriptor could + * now be complete. + */ + status =3D dma_cookie_status(&channel->vc.chan, cookie, NULL); + if (status =3D=3D DMA_COMPLETE) + return 0; + + /* + * If the cookie doesn't correspond to the currently processing virtual + * descriptor then the descriptor hasn't been processed yet, and the + * residue is equal to the full descriptor size. Also, a client driver + * is possible to call this function before rz_dmac_irq_handler_thread() + * runs. In this case, the running descriptor will be the next + * descriptor, and will appear in the done list. So, if the argument + * cookie matches the done list's cookie, we can assume the residue is + * zero. + */ + if (cookie !=3D current_desc->vd.tx.cookie) { + list_for_each_entry(desc, &channel->ld_free, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return 0; + } + + list_for_each_entry(desc, &channel->ld_queue, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return desc->len; + } + + list_for_each_entry(desc, &channel->ld_active, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return desc->len; + } + + /* + * No descriptor found for the cookie, there's thus no residue. + * This shouldn't happen if the calling driver passes a correct + * cookie value. + */ + WARN(1, "No descriptor for cookie!"); + return 0; + } + + /* + * We need to read two registers. Make sure the hardware does not move + * to next lmdesc while reading the current lmdesc. Trying it 3 times + * should be enough: initial read, retry, retry for the paranoid. + */ + for (i =3D 0; i < 3; i++) { + crla =3D rz_dmac_ch_readl(channel, CRLA, 1); + crtb =3D rz_dmac_ch_readl(channel, CRTB, 1); + /* Still the same? */ + if (crla =3D=3D rz_dmac_ch_readl(channel, CRLA, 1)) + break; + } + + WARN_ONCE(i >=3D 3, "residue might not be continuous!"); + + /* + * Calculate number of bytes transferred in processing virtual descriptor. + * One virtual descriptor can have many lmdesc. + */ + return crtb + rz_dmac_calculate_residue_bytes_in_vd(channel, crla); +} + +static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + enum dma_status status; + u32 residue; + + status =3D dma_cookie_status(chan, cookie, txstate); + if (status =3D=3D DMA_COMPLETE || !txstate) + return status; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) + residue =3D rz_dmac_chan_get_residue(channel, cookie); + + /* if there's no residue, the cookie is complete */ + if (!residue) + return DMA_COMPLETE; + + dma_set_residue(txstate, residue); + + return status; +} + /* * -----------------------------------------------------------------------= ------ * IRQ handling @@ -997,6 +1138,7 @@ static int rz_dmac_probe(struct platform_device *pdev) engine =3D &dmac->engine; dma_cap_set(DMA_SLAVE, engine->cap_mask); dma_cap_set(DMA_MEMCPY, engine->cap_mask); + engine->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); =20 @@ -1004,7 +1146,7 @@ static int rz_dmac_probe(struct platform_device *pdev) =20 engine->device_alloc_chan_resources =3D rz_dmac_alloc_chan_resources; engine->device_free_chan_resources =3D rz_dmac_free_chan_resources; - engine->device_tx_status =3D dma_cookie_status; + engine->device_tx_status =3D rz_dmac_tx_status; engine->device_prep_slave_sg =3D rz_dmac_prep_slave_sg; engine->device_prep_dma_memcpy =3D rz_dmac_prep_dma_memcpy; engine->device_config =3D rz_dmac_config; --=20 2.43.0