From nobody Tue Apr 7 02:56:25 2026 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF717399357 for ; Mon, 16 Mar 2026 13:33:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773667987; cv=none; b=rdzlf1oFnzg23e88BU9XZTjqb6mlhgOuF/+2CuD6MNFLvLMP67qwejCeZBuM88Xozjpy7DMU2tOUonBhbbaMqdWwrPdKFWtHVZ2flDJYrhlN9lK4/bnH6qCjpOePfIg+k/Nm5ZZlrXozCJMkeiXPLTNt+DnUM2AV2ZypJ2C4Q2A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773667987; c=relaxed/simple; bh=5vNGiQOV9z2LuY7BexBTaM4+b8WdnI5Dm+Qs8Ojt3x4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RUM5uS2GOjckBTOuGl2zTaP4RbtKoaCOAGGrt4mczTnFWNqTKVxBAvwHOXzgb3SzhNFR+IhG8zIggzJzH3m2mvXs0dJQtTPiWnDBwzCNegWG117xhZS0evY1CveI4A9noce2fHlUHJEMQsn4FRLESL+Pvu0hvIMgiMjsAnCVto0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=Y3cleuAq; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Y3cleuAq" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-6653b589a78so1817750a12.3 for ; Mon, 16 Mar 2026 06:33:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1773667984; x=1774272784; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3+W56HzNycC2wMkiULlWF3cNiCiN6FevvWbhSc6vRfM=; b=Y3cleuAqHMD2a1ulTa1eWT8AYviCDnSgUM1AjUDk3vEQfxmWIN1okEtY2l/sUvGgLl hoYhqQGkCZH1YOQAmJ/Q+hRM5TsSbvmrbD0u4XVRbar9sKzQO4E3H0FKVpBwwaaNf1RB OQVVM15AxdJ/KwTYgCxt1jdcdfl4wMj3a9L70LDq0SKSLhQh/ToEDQnrV0wGzrzF6egR 3mM+Niqtg7eKyq3Ai36fl5QliY9C0gEt1NyZAdAVWhPkuLFlpdT1rmXurk6Lpc0sqQFB Pdjzj5d8YQ+LlqlLTbgv8LAjIzwjKFgyBdtZS6DCREyQWR8JTAmfaQsgWH2uPZov9axC xx2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773667984; x=1774272784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3+W56HzNycC2wMkiULlWF3cNiCiN6FevvWbhSc6vRfM=; b=JBXAXDo7PcoILOSJssdsizLk+QmLYbrm5SiMTFx8au5Yhk/WcEH0GtTHdhgDevLc9J dgC2G2gWzHZ45aCZEwaS1ODzQNLKGJBDQK7fNePAbvmfjGpUJNgZDCXv6Ei9P70tyAjs H25ID179+JAT5hZElvm9jUT1dAh9cC3HRjBCtJYZfCUvj3RLYsoqiNzBFxQVWZDHfGdh UsHofTLQbYNSZFaq7kUzseRdhncNFd+R6P1HtDdPz7zbeRzTCRwT9DrkCcDLz0vZDH57 KpBI0SvO3hyjaFEWdp2yyHykJpaIcAiiyBMYl3in/ottkqYqcY620r+xIM8onjz8gNS0 GA5g== X-Forwarded-Encrypted: i=1; AJvYcCXibO3Omp7DZfGCOgIk8iAbfLvNO+geLGA0KZopXxiCgQh8voAs4NjwoWHXXwYjtWu9OH+8FxWYAsYH8ak=@vger.kernel.org X-Gm-Message-State: AOJu0Yz+xzdqdLQAqK67rk2tol0V1j6bhboeSTQg/04GHHWemLXnAqid zqoRE2xU4l30YvQGzarI8bEMzngaB88C3no1YUNMEbby68OCf46skMG1RADd8tJPJdA= X-Gm-Gg: ATEYQzzXRskwd8voGMK5UqhVvTrGBQNnS/LrPF2UIXDFURkGua5AWgAtZ5ZhQZBx7Dm fUdZ4AFctdTvvPkk3uuJa/1E5iyD4OnXp8BhhmmA9w9rk4hb3p++cbxHh0u/opRKwjCZ9/G4B9I OdzvW4e8M6Cv+0lq62O/UBDAvuv7dDL7VR80ross1soN3DRqs9jMRePodaSf7dh643IviWKOgWn yNT2PDOG+lQDgkD9v0ZGSFOej6GRVh8c33rWOa0m/NvYbI1wcL1gvsqVNO7VMx1RPb/7/byRmnL qe76x4eBtT/OQ15dNzAJd1cfaUJ1wDDJGENNIz2eKISd2cS6OVxiEpWlvMLycPjyLPs3TANzptu QIRTVr2e6Y9BuHBrWjnbknY/U1ooQRuKL1cO5g/3PzfsZB448xHtSlw6En7m7HiSlgmDYQR7hcK fjJIuBK2isl00akG5QCgUGw59jpRtuELWNVfxRi9v6Sl39ie6jE5fqnt3i5yJpWkaybZg2hN9GW GlJABg= X-Received: by 2002:a17:907:2982:b0:b93:5405:9260 with SMTP id a640c23a62f3a-b976519a1e1mr613963966b.30.1773667983963; Mon, 16 Mar 2026 06:33:03 -0700 (PDT) Received: from claudiu-TUXEDO-InfinityBook-Pro-AMD-Gen9.. ([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:03 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org, Frank Li Subject: [PATCH v10 1/8] dmaengine: sh: rz-dmac: Protect the driver specific lists Date: Mon, 16 Mar 2026 15:32:45 +0200 Message-ID: <20260316133252.240348-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver lists (ld_free, ld_queue) are used in rz_dmac_free_chan_resources(), rz_dmac_terminate_all(), rz_dmac_issue_pending(), and rz_dmac_irq_handler_thread(), all under the virtual channel lock. Take the same lock in rz_dmac_prep_slave_sg() and rz_dmac_prep_dma_memcpy() as well to avoid concurrency issues, since these functions also check whether the lists are empty and update or remove list entries. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - collected tags Changes in v8: - none Changes in v7: - none Changes in v6: - none Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 57 ++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index c75e9202e239..ec1b6b00af76 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -10,6 +10,7 @@ */ =20 #include +#include #include #include #include @@ -452,6 +453,7 @@ static int rz_dmac_alloc_chan_resources(struct dma_chan= *chan) if (!desc) break; =20 + /* No need to lock. This is called only for the 1st client. */ list_add_tail(&desc->node, &channel->ld_free); channel->descs_allocated++; } @@ -507,18 +509,21 @@ rz_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_ad= dr_t dest, dma_addr_t src, dev_dbg(dmac->dev, "%s channel: %d src=3D0x%pad dst=3D0x%pad len=3D%zu\n", __func__, channel->index, &src, &dest, len); =20 - if (list_empty(&channel->ld_free)) - return NULL; + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + if (list_empty(&channel->ld_free)) + return NULL; + + desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); =20 - desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + desc->type =3D RZ_DMAC_DESC_MEMCPY; + desc->src =3D src; + desc->dest =3D dest; + desc->len =3D len; + desc->direction =3D DMA_MEM_TO_MEM; =20 - desc->type =3D RZ_DMAC_DESC_MEMCPY; - desc->src =3D src; - desc->dest =3D dest; - desc->len =3D len; - desc->direction =3D DMA_MEM_TO_MEM; + list_move_tail(channel->ld_free.next, &channel->ld_queue); + } =20 - list_move_tail(channel->ld_free.next, &channel->ld_queue); return vchan_tx_prep(&channel->vc, &desc->vd, flags); } =20 @@ -534,27 +539,29 @@ rz_dmac_prep_slave_sg(struct dma_chan *chan, struct s= catterlist *sgl, int dma_length =3D 0; int i =3D 0; =20 - if (list_empty(&channel->ld_free)) - return NULL; + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + if (list_empty(&channel->ld_free)) + return NULL; =20 - desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); + desc =3D list_first_entry(&channel->ld_free, struct rz_dmac_desc, node); =20 - for_each_sg(sgl, sg, sg_len, i) { - dma_length +=3D sg_dma_len(sg); - } + for_each_sg(sgl, sg, sg_len, i) + dma_length +=3D sg_dma_len(sg); =20 - desc->type =3D RZ_DMAC_DESC_SLAVE_SG; - desc->sg =3D sgl; - desc->sgcount =3D sg_len; - desc->len =3D dma_length; - desc->direction =3D direction; + desc->type =3D RZ_DMAC_DESC_SLAVE_SG; + desc->sg =3D sgl; + desc->sgcount =3D sg_len; + desc->len =3D dma_length; + desc->direction =3D direction; =20 - if (direction =3D=3D DMA_DEV_TO_MEM) - desc->src =3D channel->src_per_address; - else - desc->dest =3D channel->dst_per_address; + if (direction =3D=3D DMA_DEV_TO_MEM) + desc->src =3D channel->src_per_address; + else + desc->dest =3D channel->dst_per_address; + + list_move_tail(channel->ld_free.next, &channel->ld_queue); + } =20 - list_move_tail(channel->ld_free.next, &channel->ld_queue); return vchan_tx_prep(&channel->vc, &desc->vd, flags); } =20 --=20 2.43.0 From nobody Tue Apr 7 02:56:25 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86F2339A053 for ; Mon, 16 Mar 2026 13:33:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773667989; cv=none; b=ZxBX4Mhc/c3xMjnVz5QQQnFwpL2lp4paFwi1TE2tY929WuwvjXoRaVAgtC58xns81SL4ZJqtZOYHBrCScmZwNc6TRHmPCQhdf5KYpo5h09gQZ83SIL2IzVOTNxbQDABGTCLdBfnW+668p+5XIpI6T083vgtXDI3GuaRnM2wgtV0= ARC-Message-Signature: i=1; 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Mon, 16 Mar 2026 06:33:05 -0700 (PDT) Received: from claudiu-TUXEDO-InfinityBook-Pro-AMD-Gen9.. ([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:05 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , stable@vger.kernel.org, Frank Li Subject: [PATCH v10 2/8] dmaengine: sh: rz-dmac: Move CHCTRL updates under spinlock Date: Mon, 16 Mar 2026 15:32:46 +0200 Message-ID: <20260316133252.240348-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both rz_dmac_disable_hw() and rz_dmac_irq_handle_channel() update the CHCTRL register. To avoid concurrency issues when configuring functionalities exposed by this registers, take the virtual channel lock. All other CHCTRL updates were already protected by the same lock. Previously, rz_dmac_disable_hw() disabled and re-enabled local IRQs, before accessing CHCTRL registers but this does not ensure race-free access. Remove the local IRQ disable/enable code as well. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Reviewed-by: Biju Das Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - collected tags Changes in v8: - none Changes in v7: - collected tags Changes in v6: - update patch title and description - in rz_dmac_irq_handle_channel() lock only around the updates for the error path and continued using the vc lock as this is the error path and the channel will anyway be stopped; this avoids updating the code with another lock as it was suggested in the review process of v5 and the code remain simpler for a fix, w/o any impact on performance Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index ec1b6b00af76..e2d506eb8194 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -303,13 +303,10 @@ static void rz_dmac_disable_hw(struct rz_dmac_chan *c= hannel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - unsigned long flags; =20 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); =20 - local_irq_save(flags); rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); - local_irq_restore(flags); } =20 static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 d= mars) @@ -573,8 +570,8 @@ static int rz_dmac_terminate_all(struct dma_chan *chan) unsigned int i; LIST_HEAD(head); =20 - rz_dmac_disable_hw(channel); spin_lock_irqsave(&channel->vc.lock, flags); + rz_dmac_disable_hw(channel); for (i =3D 0; i < DMAC_NR_LMDESC; i++) lmdesc[i].header =3D 0; =20 @@ -705,7 +702,9 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_c= han *channel) if (chstat & CHSTAT_ER) { dev_err(dmac->dev, "DMAC err CHSTAT_%d =3D %08X\n", channel->index, chstat); - rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); + + scoped_guard(spinlock_irqsave, &channel->vc.lock) + rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); goto done; 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([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:07 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Frank Li Subject: [PATCH v10 3/8] dmaengine: sh: rz-dmac: Drop read of CHCTRL register Date: Mon, 16 Mar 2026 15:32:47 +0200 Message-ID: <20260316133252.240348-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CHCTRL register has 11 bits that can be updated by software. The documentation for all these bits states the following: - A read operation results in 0 being read - Writing zero does not affect the operation All bits in the CHCTRL register accessible by software are set and clear bits. The documentation for the CLREND bit of CHCTRL states: Setting this bit to 1 can clear the END bit of the CHSTAT_n/nS register. Also, the DMA transfer end interrupt is cleared. An attempt to read this bit results in 0 being read. 1: Clears the END bit. 0: Does not affect the operation. Since writing zero to any bit in this register does not affect controller operation and reads always return zero, there is no need to perform read-modify-write accesses to set the CLREND bit. Drop the read of the CHCTRL register. Also, since setting the CLREND bit does not interact with other functionalities exposed through this register and only clears the END interrupt, there is no need to lock around this operation. Add a comment to document this. Reviewed-by: Biju Das Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - collected tags Changes in v8: - none Changes in v7: - collected tags Changes in v6: - none, this patch is new drivers/dma/sh/rz-dmac.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index e2d506eb8194..29fa2ad07e30 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -696,7 +696,7 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_c= han *channel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - u32 chstat, chctrl; + u32 chstat; =20 chstat =3D rz_dmac_ch_readl(channel, CHSTAT, 1); if (chstat & CHSTAT_ER) { @@ -708,8 +708,11 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_= chan *channel) goto done; } =20 - chctrl =3D rz_dmac_ch_readl(channel, CHCTRL, 1); - rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1); + /* + * No need to lock. This just clears the END interrupt. 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([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:08 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Frank Li Subject: [PATCH v10 4/8] dmaengine: sh: rz-dmac: Drop goto instruction and label Date: Mon, 16 Mar 2026 15:32:48 +0200 Message-ID: <20260316133252.240348-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no need to jump to the done label, so return immediately. Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - collected tags - updated patch description Changes in v8: - none Changes in v7: - none Changes in v6: - none, this patch is new drivers/dma/sh/rz-dmac.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 29fa2ad07e30..6c9bfe39a11e 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -705,7 +705,7 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_c= han *channel) =20 scoped_guard(spinlock_irqsave, &channel->vc.lock) rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1); - goto done; + return; } =20 /* @@ -713,8 +713,6 @@ static void rz_dmac_irq_handle_channel(struct rz_dmac_c= han *channel) * zeros to CHCTRL is just ignored by HW. */ rz_dmac_ch_writel(channel, CHCTRL_CLREND, CHCTRL, 1); -done: - return; } =20 static irqreturn_t rz_dmac_irq_handler(int irq, void *dev_id) --=20 2.43.0 From nobody Tue Apr 7 02:56:25 2026 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 964E0398915 for ; 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([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:10 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea , Frank Li Subject: [PATCH v10 5/8] dmaengine: sh: rz-dmac: Drop unnecessary local_irq_save() call Date: Mon, 16 Mar 2026 15:32:49 +0200 Message-ID: <20260316133252.240348-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" rz_dmac_enable_hw() calls local_irq_save()/local_irq_restore(), but this is not needed because the callers of rz_dmac_enable_hw() already protect the critical section using spin_lock_irqsave()/spin_lock_irqrestore(). Remove the local_irq_save()/local_irq_restore() calls. Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - collected tags Changes in v8: - none Changes in v7: - none Changes in v6: - none Changes in v5: - none, this patch is new drivers/dma/sh/rz-dmac.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 6c9bfe39a11e..eca62d9e9772 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -272,15 +272,12 @@ static void rz_dmac_enable_hw(struct rz_dmac_chan *ch= annel) { struct dma_chan *chan =3D &channel->vc.chan; struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - unsigned long flags; u32 nxla; u32 chctrl; u32 chstat; =20 dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index); =20 - local_irq_save(flags); - rz_dmac_lmdesc_recycle(channel); =20 nxla =3D channel->lmdesc.base_dma + @@ -295,8 +292,6 @@ static void rz_dmac_enable_hw(struct rz_dmac_chan *chan= nel) rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1); rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1); 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([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:12 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v10 6/8] dmaengine: sh: rz-dmac: Use rz_lmdesc_setup() to invalidate descriptors Date: Mon, 16 Mar 2026 15:32:50 +0200 Message-ID: <20260316133252.240348-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: John Madieu rz_lmdesc_setup() invalidates DMA descriptors more comprehensively. It resets the base, head, and tail pointers of the descriptor list and clears the descriptor headers and their NXLA pointers. Use rz_lmdesc_setup() instead of open-coding parts of its logic. Signed-off-by: John Madieu Signed-off-by: Claudiu Beznea Reviewed-by: Frank Li --- Changes in v10: - none, this patch is new and replaces the patch 6/8 ("dmaengine: sh: rz-dmac: Add rz_dmac_invalidate_lmdesc()") from v9 drivers/dma/sh/rz-dmac.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index eca62d9e9772..6bfa77844e02 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -460,15 +460,12 @@ static void rz_dmac_free_chan_resources(struct dma_ch= an *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); struct rz_dmac *dmac =3D to_rz_dmac(chan->device); - struct rz_lmdesc *lmdesc =3D channel->lmdesc.base; struct rz_dmac_desc *desc, *_desc; unsigned long flags; - unsigned int i; =20 spin_lock_irqsave(&channel->vc.lock, flags); =20 - for (i =3D 0; i < DMAC_NR_LMDESC; i++) - lmdesc[i].header =3D 0; + rz_lmdesc_setup(channel, channel->lmdesc.base); =20 rz_dmac_disable_hw(channel); list_splice_tail_init(&channel->ld_active, &channel->ld_free); @@ -560,15 +557,12 @@ rz_dmac_prep_slave_sg(struct dma_chan *chan, struct s= catterlist *sgl, static int rz_dmac_terminate_all(struct dma_chan *chan) { struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); - struct rz_lmdesc *lmdesc =3D channel->lmdesc.base; unsigned long flags; - unsigned int i; LIST_HEAD(head); =20 spin_lock_irqsave(&channel->vc.lock, flags); rz_dmac_disable_hw(channel); - for (i =3D 0; i < DMAC_NR_LMDESC; i++) - lmdesc[i].header =3D 0; + rz_lmdesc_setup(channel, channel->lmdesc.base); =20 list_splice_tail_init(&channel->ld_active, &channel->ld_free); list_splice_tail_init(&channel->ld_queue, &channel->ld_free); --=20 2.43.0 From nobody Tue Apr 7 02:56:25 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F39BD39B967 for ; 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([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:13 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Long Luu , Claudiu Beznea Subject: [PATCH v10 7/8] dmaengine: sh: rz-dmac: Add device_tx_status() callback Date: Mon, 16 Mar 2026 15:32:51 +0200 Message-ID: <20260316133252.240348-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L SCIFA driver uses dmaengine_prep_slave_sg() to enqueue DMA transfers and implements a timeout mechanism on RX to handle cases where a DMA transfer does not complete. The timeout is implemented using an hrtimer. In the hrtimer callback, dmaengine_tx_status() is called (along with dmaengine_pause()) to retrieve the transfer residue and handle incomplete DMA transfers. Add support for the device_tx_status() callback. Co-developed-by: Long Luu Signed-off-by: Long Luu Signed-off-by: Biju Das Co-developed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - adjusted the patch description - dropped contribution list for Claudiu Beznea - used Co-developed-by + SoB tags and included Long Luu in the contribution list as well - dropped the read of CRLA in rz_dmac_calculate_residue_bytes_in_vd() and use the copy from the calling function (rz_dmac_chan_get_residue()) Changes in v8: - populated engine->residue_granularity Changes in v7: - none Changes in v6: - s/byte/bytes in comment from rz_dmac_chan_get_residue() Changes in v5: - post-increment lmdesc in rz_dmac_get_next_lmdesc() to allow the next pointer to advance - use 'lmdesc->nxla !=3D crla' comparison instead of '!(lmdesc->nxla =3D=3D crla)' in rz_dmac_calculate_residue_bytes_in_vd() - in rz_dmac_calculate_residue_bytes_in_vd() use '++i >=3D DMAC_NR_LMDESC' to verify if the full lmdesc list was checked - drop rz_dmac_calculate_total_bytes_in_vd() and use desc->len instead - re-arranged comments so they span fewer lines and are wrapped to ~80 characters - use u32 for the residue value and the functions returning it - use u32 for the variables storing register values - fixed typos drivers/dma/sh/rz-dmac.c | 144 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 6bfa77844e02..4f6f9f4bacca 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -124,10 +124,12 @@ struct rz_dmac { * Registers */ =20 +#define CRTB 0x0020 #define CHSTAT 0x0024 #define CHCTRL 0x0028 #define CHCFG 0x002c #define NXLA 0x0038 +#define CRLA 0x003c =20 #define DCTRL 0x0000 =20 @@ -676,6 +678,145 @@ static void rz_dmac_device_synchronize(struct dma_cha= n *chan) rz_dmac_set_dma_req_no(dmac, channel->index, dmac->info->default_dma_req_= no); } =20 +static struct rz_lmdesc * +rz_dmac_get_next_lmdesc(struct rz_lmdesc *base, struct rz_lmdesc *lmdesc) +{ + struct rz_lmdesc *next =3D ++lmdesc; + + if (next >=3D base + DMAC_NR_LMDESC) + next =3D base; + + return next; +} + +static u32 rz_dmac_calculate_residue_bytes_in_vd(struct rz_dmac_chan *chan= nel, u32 crla) +{ + struct rz_lmdesc *lmdesc =3D channel->lmdesc.head; + struct dma_chan *chan =3D &channel->vc.chan; + struct rz_dmac *dmac =3D to_rz_dmac(chan->device); + u32 residue =3D 0, i =3D 0; + + while (lmdesc->nxla !=3D crla) { + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + if (++i >=3D DMAC_NR_LMDESC) + return 0; + } + + /* Calculate residue from next lmdesc to end of virtual desc */ + while (lmdesc->chcfg & CHCFG_DEM) { + residue +=3D lmdesc->tb; + lmdesc =3D rz_dmac_get_next_lmdesc(channel->lmdesc.base, lmdesc); + } + + dev_dbg(dmac->dev, "%s: VD residue is %u\n", __func__, residue); + + return residue; +} + +static u32 rz_dmac_chan_get_residue(struct rz_dmac_chan *channel, + dma_cookie_t cookie) +{ + struct rz_dmac_desc *current_desc, *desc; + enum dma_status status; + u32 crla, crtb, i; + + /* Get current processing virtual descriptor */ + current_desc =3D list_first_entry(&channel->ld_active, + struct rz_dmac_desc, node); + if (!current_desc) + return 0; + + /* + * If the cookie corresponds to a descriptor that has been completed + * there is no residue. The same check has already been performed by the + * caller but without holding the channel lock, so the descriptor could + * now be complete. + */ + status =3D dma_cookie_status(&channel->vc.chan, cookie, NULL); + if (status =3D=3D DMA_COMPLETE) + return 0; + + /* + * If the cookie doesn't correspond to the currently processing virtual + * descriptor then the descriptor hasn't been processed yet, and the + * residue is equal to the full descriptor size. Also, a client driver + * is possible to call this function before rz_dmac_irq_handler_thread() + * runs. In this case, the running descriptor will be the next + * descriptor, and will appear in the done list. So, if the argument + * cookie matches the done list's cookie, we can assume the residue is + * zero. + */ + if (cookie !=3D current_desc->vd.tx.cookie) { + list_for_each_entry(desc, &channel->ld_free, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return 0; + } + + list_for_each_entry(desc, &channel->ld_queue, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return desc->len; + } + + list_for_each_entry(desc, &channel->ld_active, node) { + if (cookie =3D=3D desc->vd.tx.cookie) + return desc->len; + } + + /* + * No descriptor found for the cookie, there's thus no residue. + * This shouldn't happen if the calling driver passes a correct + * cookie value. + */ + WARN(1, "No descriptor for cookie!"); + return 0; + } + + /* + * We need to read two registers. Make sure the hardware does not move + * to next lmdesc while reading the current lmdesc. Trying it 3 times + * should be enough: initial read, retry, retry for the paranoid. + */ + for (i =3D 0; i < 3; i++) { + crla =3D rz_dmac_ch_readl(channel, CRLA, 1); + crtb =3D rz_dmac_ch_readl(channel, CRTB, 1); + /* Still the same? */ + if (crla =3D=3D rz_dmac_ch_readl(channel, CRLA, 1)) + break; + } + + WARN_ONCE(i >=3D 3, "residue might not be continuous!"); + + /* + * Calculate number of bytes transferred in processing virtual descriptor. + * One virtual descriptor can have many lmdesc. + */ + return crtb + rz_dmac_calculate_residue_bytes_in_vd(channel, crla); +} + +static enum dma_status rz_dmac_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + enum dma_status status; + u32 residue; + + status =3D dma_cookie_status(chan, cookie, txstate); + if (status =3D=3D DMA_COMPLETE || !txstate) + return status; + + scoped_guard(spinlock_irqsave, &channel->vc.lock) + residue =3D rz_dmac_chan_get_residue(channel, cookie); + + /* if there's no residue, the cookie is complete */ + if (!residue) + return DMA_COMPLETE; + + dma_set_residue(txstate, residue); + + return status; +} + /* * -----------------------------------------------------------------------= ------ * IRQ handling @@ -997,6 +1138,7 @@ static int rz_dmac_probe(struct platform_device *pdev) engine =3D &dmac->engine; dma_cap_set(DMA_SLAVE, engine->cap_mask); dma_cap_set(DMA_MEMCPY, engine->cap_mask); + engine->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL); rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL); =20 @@ -1004,7 +1146,7 @@ static int rz_dmac_probe(struct platform_device *pdev) =20 engine->device_alloc_chan_resources =3D rz_dmac_alloc_chan_resources; engine->device_free_chan_resources =3D rz_dmac_free_chan_resources; - engine->device_tx_status =3D dma_cookie_status; + engine->device_tx_status =3D rz_dmac_tx_status; engine->device_prep_slave_sg =3D rz_dmac_prep_slave_sg; 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([2a02:2f04:6208:0:c5e3:3624:ad1c:6b4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b419270efsm11629888f8f.16.2026.03.16.06.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 06:33:15 -0700 (PDT) From: Claudiu Beznea X-Google-Original-From: Claudiu Beznea To: vkoul@kernel.org, Frank.Li@kernel.org, geert+renesas@glider.be, biju.das.jz@bp.renesas.com, john.madieu.xa@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v10 8/8] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks Date: Mon, 16 Mar 2026 15:32:52 +0200 Message-ID: <20260316133252.240348-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> References: <20260316133252.240348-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RZ/G2L SCIFA driver uses dmaengine_prep_slave_sg() to enqueue DMA transfers and implements a timeout mechanism on RX to handle cases where a DMA transfer does not complete. The timeout is implemented using an hrtimer. In the hrtimer callback, dmaengine_tx_status() is called (along with dmaengine_pause()) to retrieve the transfer residue and handle incomplete DMA transfers. Add support for device_{pause, resume}() callbacks. Signed-off-by: Claudiu Beznea --- Changes in v10: - none Changes in v9: - updated the patch description Changes in v8: - reported residue for paused channels as well Changes in v7: - use guard() instead of scoped_guard() - in rz_dmac_device_pause() checked the channel is enabled before suspending it to avoid read poll timeouts - added a comment in rz_dmac_device_resume() Changes in v6: - set CHCTRL_SETSUS for pause and CHCTRL_CLRSUS for resume - dropped read-modify-update approach for CHCTRL updates as the HW returns zero when reading CHCTRL - moved the read_poll_timeout_atomic() under spin lock to ensure avoid any races b/w pause and resume functionalities Changes in v5: - used suspend capability of the controller to pause/resume the transfers drivers/dma/sh/rz-dmac.c | 49 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 4f6f9f4bacca..625ff29024de 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -140,10 +140,12 @@ struct rz_dmac { #define CHANNEL_8_15_COMMON_BASE 0x0700 =20 #define CHSTAT_ER BIT(4) +#define CHSTAT_SUS BIT(3) #define CHSTAT_EN BIT(0) =20 #define CHCTRL_CLRINTMSK BIT(17) #define CHCTRL_CLRSUS BIT(9) +#define CHCTRL_SETSUS BIT(8) #define CHCTRL_CLRTC BIT(6) #define CHCTRL_CLREND BIT(5) #define CHCTRL_CLRRQ BIT(4) @@ -805,11 +807,18 @@ static enum dma_status rz_dmac_tx_status(struct dma_c= han *chan, if (status =3D=3D DMA_COMPLETE || !txstate) return status; =20 - scoped_guard(spinlock_irqsave, &channel->vc.lock) + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + u32 val; + residue =3D rz_dmac_chan_get_residue(channel, cookie); =20 - /* if there's no residue, the cookie is complete */ - if (!residue) + val =3D rz_dmac_ch_readl(channel, CHSTAT, 1); + if (val & CHSTAT_SUS) + status =3D DMA_PAUSED; + } + + /* if there's no residue and no paused, the cookie is complete */ + if (!residue && status !=3D DMA_PAUSED) return DMA_COMPLETE; =20 dma_set_residue(txstate, residue); @@ -817,6 +826,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_ch= an *chan, return status; } =20 +static int rz_dmac_device_pause(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + + guard(spinlock_irqsave)(&channel->vc.lock); + + val =3D rz_dmac_ch_readl(channel, CHSTAT, 1); + if (!(val & CHSTAT_EN)) + return 0; + + rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, + (val & CHSTAT_SUS), 1, 1024, + false, channel, CHSTAT, 1); +} + +static int rz_dmac_device_resume(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + + guard(spinlock_irqsave)(&channel->vc.lock); + + /* Do not check CHSTAT_SUS but rely on HW capabilities. */ + + rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, + !(val & CHSTAT_SUS), 1, 1024, + false, channel, CHSTAT, 1); +} + /* * -----------------------------------------------------------------------= ------ * IRQ handling @@ -1153,6 +1194,8 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_terminate_all =3D rz_dmac_terminate_all; engine->device_issue_pending =3D rz_dmac_issue_pending; engine->device_synchronize =3D rz_dmac_device_synchronize; + engine->device_pause =3D rz_dmac_device_pause; + engine->device_resume =3D rz_dmac_device_resume; =20 engine->copy_align =3D DMAENGINE_ALIGN_1_BYTE; dma_set_max_seg_size(engine->dev, U32_MAX); --=20 2.43.0