From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B8D8F3939DD; Mon, 16 Mar 2026 12:12:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663181; cv=none; b=UIgYJyvT8+W1VDI06K0kCbkfkbver7JQKpgYKvVQP0+UQ/gPpJkeQPytUVOuyAyrRIxFnIK1Lvd9/JFCYBRODn5f+e5zL1Gm2rbUAdaH9SXPCf6fxkTb25vlx4+qrlyMCtnZ5HawtTeIEoV6vLIU+xYwDAA9VByKIeppsw3r6Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663181; c=relaxed/simple; bh=MVIADVbueLx3yQEJ2iYnj2s1XkLRnQtQerVrnAstgKk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NlAS7HCwM9edbVDK9LRaDR+ajUmHiS+6AxALu2zTrR81GUp0K9L3rxPO3RMyiqYO65qy4Bgtf6LgSVPQeAJGpX7x3VWI8DDpIw2F62inpnF7pPGjUUP1XB7e/3Xg+ENaSU/euaV/hqyqDbn2/g6rHxOXi9RmP4iT6PkRYlD/Kp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=JnrfaQ1q; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="JnrfaQ1q" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id C980B20B7129; Mon, 16 Mar 2026 05:12:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com C980B20B7129 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663179; bh=6df6NmlHbYEwsjePCZxMwR+//HiqFND2iuF0yusrO7A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JnrfaQ1qzJtMxSWlOSqo+uWUtX+v3P2ZCsXLOhdyHnOiD5Mf/g2gbHMdnHNx1+B0e HG2BK6FeWTAuENeXTbTg7QebepK3AW7xpc2WLe6mfQa3LB3dskvBj/x9U7s0qec5Nj uex5YeK0kEHqZinvkTyE9P6h/eVsH96Ez3dITCIY= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 01/11] arch: arm64: Export arch_smp_send_reschedule for mshv_vtl module Date: Mon, 16 Mar 2026 12:12:31 +0000 Message-ID: <20260316121241.910764-2-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mshv_vtl_main.c calls smp_send_reschedule() which expands to arch_smp_send_reschedule(). When CONFIG_MSHV_VTL=3Dm, the module cannot access this symbol since it is not exported on arm64. smp_send_reschedule() is used in mshv_vtl_cancel() to interrupt a vCPU thread running on another CPU. When a vCPU is looping in mshv_vtl_ioctl_return_to_lower_vtl(), it checks a per-CPU cancel flag before each VTL0 entry. Setting cancel=3D1 alone is not enough if the target CPU thread is sleeping - the IPI from smp_send_reschedule() kicks the remote CPU out of idle/sleep so it re-checks the cancel flag and exits the loop promptly. Other architectures (riscv, loongarch, powerpc) already export this symbol. Add the same EXPORT_SYMBOL_GPL for arm64. This is required for adding arm64 support in MSHV_VTL. Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/arm64/kernel/smp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 1aa324104afb..26b1a4456ceb 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -1152,6 +1152,7 @@ void arch_smp_send_reschedule(int cpu) { smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); } +EXPORT_SYMBOL_GPL(arch_smp_send_reschedule); =20 #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL void arch_send_wakeup_ipi(unsigned int cpu) --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 87953393DC8; Mon, 16 Mar 2026 12:13:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663189; cv=none; b=LH0q5WklZwCkWDDKDQU1fM0Dt7VycyFZk2UXgmZKBb13xgRfYvf2d06+dzAOA/I1pDFBtg62pqFWn8h5G25vy7cU6iNYZFzxREkrLZpd97N9FA5Dhk45iH6Y6QzqpeTEvGufWSdvJIJ/ejr//zH6adM/1SiiGkmzhNFeNERlmb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663189; c=relaxed/simple; bh=dMpds+80CaLzIb/6yDFh8OyjGvS73w9th8MuzJ7NFN8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NtK1bObIx6YovGe6pRfs/c7jx7i/bs9VrPE5HLyIE7lfRM2/b7GEk+1W1bW8BtJAGrqemi2rhzy3I9JjFz0EGRJTRfHpcc9HhHTgEN6EwDIPXy0ALlhpBa6C3mMuaSVMxpQjNKey2ZrM8nQpAmh36Zv3VN/hzI8x50hmpL91tMI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=MPIYb9Xz; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="MPIYb9Xz" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id 34AFF20B712D; Mon, 16 Mar 2026 05:13:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 34AFF20B712D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663186; bh=ffZk0PPKYEQEqi1cdn+WAt9NLDrbIaqAeaBwUEetWAg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MPIYb9XzXXhOtWJAFnJB6nZ7H0wBSf/zjtHoA+1FkmglvN+dzRFPkCmn/qqqN1dCo wztaCF4qN/g4gdiNsuoXACDpx8w1h+AX3/4iyV20B9gFJWyd9dIL0Lp3fAbHIlcCY+ bwhT10Nd7QrYt2Gw3FwqupZOPKfnTmDVDFiXADjM= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 02/11] Drivers: hv: Move hv_vp_assist_page to common files Date: Mon, 16 Mar 2026 12:12:32 +0000 Message-ID: <20260316121241.910764-3-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the logic to initialize and export hv_vp_assist_page from x86 architecture code to Hyper-V common code to allow it to be used for upcoming arm64 support in MSHV_VTL driver. Note: This change also improves error handling - if VP assist page allocation fails, hyperv_init() now returns early instead of continuing with partial initialization. Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/x86/hyperv/hv_init.c | 88 +--------------------------------- drivers/hv/hv_common.c | 88 ++++++++++++++++++++++++++++++++++ include/asm-generic/mshyperv.h | 4 ++ include/hyperv/hvgdk_mini.h | 2 + 4 files changed, 95 insertions(+), 87 deletions(-) diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c index 323adc93f2dc..75a98b5e451b 100644 --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -81,9 +81,6 @@ union hv_ghcb * __percpu *hv_ghcb_pg; /* Storage to save the hypercall page temporarily for hibernation */ static void *hv_hypercall_pg_saved; =20 -struct hv_vp_assist_page **hv_vp_assist_page; -EXPORT_SYMBOL_GPL(hv_vp_assist_page); - static int hyperv_init_ghcb(void) { u64 ghcb_gpa; @@ -117,59 +114,12 @@ static int hyperv_init_ghcb(void) =20 static int hv_cpu_init(unsigned int cpu) { - union hv_vp_assist_msr_contents msr =3D { 0 }; - struct hv_vp_assist_page **hvp; int ret; =20 ret =3D hv_common_cpu_init(cpu); if (ret) return ret; =20 - if (!hv_vp_assist_page) - return 0; - - hvp =3D &hv_vp_assist_page[cpu]; - if (hv_root_partition()) { - /* - * For root partition we get the hypervisor provided VP assist - * page, instead of allocating a new page. - */ - rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); - *hvp =3D memremap(msr.pfn << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT, - PAGE_SIZE, MEMREMAP_WB); - } else { - /* - * The VP assist page is an "overlay" page (see Hyper-V TLFS's - * Section 5.2.1 "GPA Overlay Pages"). Here it must be zeroed - * out to make sure we always write the EOI MSR in - * hv_apic_eoi_write() *after* the EOI optimization is disabled - * in hv_cpu_die(), otherwise a CPU may not be stopped in the - * case of CPU offlining and the VM will hang. - */ - if (!*hvp) { - *hvp =3D __vmalloc(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO); - - /* - * Hyper-V should never specify a VM that is a Confidential - * VM and also running in the root partition. Root partition - * is blocked to run in Confidential VM. So only decrypt assist - * page in non-root partition here. - */ - if (*hvp && !ms_hyperv.paravisor_present && hv_isolation_type_snp()) { - WARN_ON_ONCE(set_memory_decrypted((unsigned long)(*hvp), 1)); - memset(*hvp, 0, PAGE_SIZE); - } - } - - if (*hvp) - msr.pfn =3D vmalloc_to_pfn(*hvp); - - } - if (!WARN_ON(!(*hvp))) { - msr.enable =3D 1; - wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); - } - /* Allow Hyper-V stimer vector to be injected from Hypervisor. */ if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) apic_update_vector(cpu, HYPERV_STIMER0_VECTOR, true); @@ -286,23 +236,6 @@ static int hv_cpu_die(unsigned int cpu) =20 hv_common_cpu_die(cpu); =20 - if (hv_vp_assist_page && hv_vp_assist_page[cpu]) { - union hv_vp_assist_msr_contents msr =3D { 0 }; - if (hv_root_partition()) { - /* - * For root partition the VP assist page is mapped to - * hypervisor provided page, and thus we unmap the - * page here and nullify it, so that in future we have - * correct page address mapped in hv_cpu_init. - */ - memunmap(hv_vp_assist_page[cpu]); - hv_vp_assist_page[cpu] =3D NULL; - rdmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); - msr.enable =3D 0; - } - wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); - } - if (hv_reenlightenment_cb =3D=3D NULL) return 0; =20 @@ -460,21 +393,6 @@ void __init hyperv_init(void) if (hv_common_init()) return; =20 - /* - * The VP assist page is useless to a TDX guest: the only use we - * would have for it is lazy EOI, which can not be used with TDX. - */ - if (hv_isolation_type_tdx()) - hv_vp_assist_page =3D NULL; - else - hv_vp_assist_page =3D kzalloc_objs(*hv_vp_assist_page, nr_cpu_ids); - if (!hv_vp_assist_page) { - ms_hyperv.hints &=3D ~HV_X64_ENLIGHTENED_VMCS_RECOMMENDED; - - if (!hv_isolation_type_tdx()) - goto common_free; - } - if (ms_hyperv.paravisor_present && hv_isolation_type_snp()) { /* Negotiate GHCB Version. */ if (!hv_ghcb_negotiate_protocol()) @@ -483,7 +401,7 @@ void __init hyperv_init(void) =20 hv_ghcb_pg =3D alloc_percpu(union hv_ghcb *); if (!hv_ghcb_pg) - goto free_vp_assist_page; + goto free_ghcb_page; } =20 cpuhp =3D cpuhp_setup_state(CPUHP_AP_HYPERV_ONLINE, "x86/hyperv_init:onli= ne", @@ -613,10 +531,6 @@ void __init hyperv_init(void) cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE); free_ghcb_page: free_percpu(hv_ghcb_pg); -free_vp_assist_page: - kfree(hv_vp_assist_page); - hv_vp_assist_page =3D NULL; -common_free: hv_common_free(); } =20 diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c index 6b67ac616789..d1ebc0ebd08f 100644 --- a/drivers/hv/hv_common.c +++ b/drivers/hv/hv_common.c @@ -28,7 +28,9 @@ #include #include #include +#include #include +#include #include =20 u64 hv_current_partition_id =3D HV_PARTITION_ID_SELF; @@ -78,6 +80,8 @@ static struct ctl_table_header *hv_ctl_table_hdr; u8 * __percpu *hv_synic_eventring_tail; EXPORT_SYMBOL_GPL(hv_synic_eventring_tail); =20 +struct hv_vp_assist_page **hv_vp_assist_page; +EXPORT_SYMBOL_GPL(hv_vp_assist_page); /* * Hyper-V specific initialization and shutdown code that is * common across all architectures. Called from architecture @@ -92,6 +96,9 @@ void __init hv_common_free(void) if (ms_hyperv.misc_features & HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE) hv_kmsg_dump_unregister(); =20 + kfree(hv_vp_assist_page); + hv_vp_assist_page =3D NULL; + kfree(hv_vp_index); hv_vp_index =3D NULL; =20 @@ -394,6 +401,23 @@ int __init hv_common_init(void) for (i =3D 0; i < nr_cpu_ids; i++) hv_vp_index[i] =3D VP_INVAL; =20 + /* + * The VP assist page is useless to a TDX guest: the only use we + * would have for it is lazy EOI, which can not be used with TDX. + */ + if (hv_isolation_type_tdx()) { + hv_vp_assist_page =3D NULL; + } else { + hv_vp_assist_page =3D kzalloc_objs(*hv_vp_assist_page, nr_cpu_ids); + if (!hv_vp_assist_page) { +#ifdef CONFIG_X86_64 + ms_hyperv.hints &=3D ~HV_X64_ENLIGHTENED_VMCS_RECOMMENDED; +#endif + hv_common_free(); + return -ENOMEM; + } + } + return 0; } =20 @@ -471,6 +495,8 @@ void __init ms_hyperv_late_init(void) =20 int hv_common_cpu_init(unsigned int cpu) { + union hv_vp_assist_msr_contents msr =3D { 0 }; + struct hv_vp_assist_page **hvp; void **inputarg, **outputarg; u8 **synic_eventring_tail; u64 msr_vp_index; @@ -542,6 +568,50 @@ int hv_common_cpu_init(unsigned int cpu) ret =3D -ENOMEM; } =20 + if (!hv_vp_assist_page) + return ret; + + hvp =3D &hv_vp_assist_page[cpu]; + if (hv_root_partition()) { + /* + * For root partition we get the hypervisor provided VP assist + * page, instead of allocating a new page. + */ + msr.as_uint64 =3D hv_get_msr(HV_SYN_REG_VP_ASSIST_PAGE); + *hvp =3D memremap(msr.pfn << HV_VP_ASSIST_PAGE_ADDRESS_SHIFT, + PAGE_SIZE, MEMREMAP_WB); + } else { + /* + * The VP assist page is an "overlay" page (see Hyper-V TLFS's + * Section 5.2.1 "GPA Overlay Pages"). Here it must be zeroed + * out to make sure we always write the EOI MSR in + * hv_apic_eoi_write() *after* the EOI optimization is disabled + * in hv_cpu_die(), otherwise a CPU may not be stopped in the + * case of CPU offlining and the VM will hang. + */ + if (!*hvp) { + *hvp =3D __vmalloc(PAGE_SIZE, GFP_KERNEL | __GFP_ZERO); + + /* + * Hyper-V should never specify a VM that is a Confidential + * VM and also running in the root partition. Root partition + * is blocked to run in Confidential VM. So only decrypt assist + * page in non-root partition here. + */ + if (*hvp && !ms_hyperv.paravisor_present && hv_isolation_type_snp()) { + WARN_ON_ONCE(set_memory_decrypted((unsigned long)(*hvp), 1)); + memset(*hvp, 0, PAGE_SIZE); + } + } + + if (*hvp) + msr.pfn =3D vmalloc_to_pfn(*hvp); + } + if (!WARN_ON(!(*hvp))) { + msr.enable =3D 1; + hv_set_msr(HV_SYN_REG_VP_ASSIST_PAGE, msr.as_uint64); + } + return ret; } =20 @@ -566,6 +636,24 @@ int hv_common_cpu_die(unsigned int cpu) *synic_eventring_tail =3D NULL; } =20 + if (hv_vp_assist_page && hv_vp_assist_page[cpu]) { + union hv_vp_assist_msr_contents msr =3D { 0 }; + + if (hv_root_partition()) { + /* + * For root partition the VP assist page is mapped to + * hypervisor provided page, and thus we unmap the + * page here and nullify it, so that in future we have + * correct page address mapped in hv_cpu_init. + */ + memunmap(hv_vp_assist_page[cpu]); + hv_vp_assist_page[cpu] =3D NULL; + msr.as_uint64 =3D hv_get_msr(HV_SYN_REG_VP_ASSIST_PAGE); + msr.enable =3D 0; + } + hv_set_msr(HV_SYN_REG_VP_ASSIST_PAGE, msr.as_uint64); + } + return 0; } =20 diff --git a/include/asm-generic/mshyperv.h b/include/asm-generic/mshyperv.h index d37b68238c97..108f135d4fd9 100644 --- a/include/asm-generic/mshyperv.h +++ b/include/asm-generic/mshyperv.h @@ -25,6 +25,7 @@ #include #include #include +#include =20 #define VTPM_BASE_ADDRESS 0xfed40000 =20 @@ -299,6 +300,8 @@ do { \ #define hv_status_debug(status, fmt, ...) \ hv_status_printk(debug, status, fmt, ##__VA_ARGS__) =20 +extern struct hv_vp_assist_page **hv_vp_assist_page; + const char *hv_result_to_string(u64 hv_status); int hv_result_to_errno(u64 status); void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die); @@ -377,6 +380,7 @@ static inline int hv_deposit_memory(u64 partition_id, u= 64 status) return hv_deposit_memory_node(NUMA_NO_NODE, partition_id, status); } =20 +#define HV_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 #if IS_ENABLED(CONFIG_HYPERV_VTL_MODE) u8 __init get_vtl(void); #else diff --git a/include/hyperv/hvgdk_mini.h b/include/hyperv/hvgdk_mini.h index 056ef7b6b360..be697ddb211a 100644 --- a/include/hyperv/hvgdk_mini.h +++ b/include/hyperv/hvgdk_mini.h @@ -149,6 +149,7 @@ struct hv_u128 { #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) +#define HV_SYN_REG_VP_ASSIST_PAGE (HV_X64_MSR_VP_ASSIST_PAGE) =20 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff @@ -1185,6 +1186,7 @@ enum hv_register_name { =20 #define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG) #define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT) +#define HV_SYN_REG_VP_ASSIST_PAGE (HV_REGISTER_VP_ASSIST_PAGE) =20 #endif /* CONFIG_ARM64 */ =20 --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A5D93932C3; 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arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="ZMDm6OU2" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id ECDB820B712B; Mon, 16 Mar 2026 05:13:07 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com ECDB820B712B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663194; bh=E3StM9+iDpcoit1RWPxAyV+2hPmFkaB3kEah6gv3o8Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZMDm6OU2yqAfZL7t2pqxQXx0b+7Tzsl4B3jaASsVyXx4EtKOat/05+uslxY9NnP2z 2qsH8BP+y+pNNzM6HR60ValkMckk/IJ3+xUNijOYFVQ2x1XUoFaNp//Gzxc3sCXm1o mbW5a0iAOYbxtYDeW/Is9Z2foXY/L41i7tMDtNB4= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 03/11] Drivers: hv: Add support to setup percpu vmbus handler Date: Mon, 16 Mar 2026 12:12:33 +0000 Message-ID: <20260316121241.910764-4-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a wrapper function - hv_setup_percpu_vmbus_handler(), similar to hv_setup_vmbus_handler() to allow setting up custom per-cpu VMBus interrupt handler. This is required for arm64 support, to be added in MSHV_VTL driver, where per-cpu VMBus interrupt handler will be set to mshv_vtl_vmbus_isr() for VTL2 (Virtual Trust Level 2). Signed-off-by: Saurabh Sengar Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/arm64/hyperv/mshyperv.c | 13 +++++++++++++ drivers/hv/hv_common.c | 11 +++++++++++ drivers/hv/vmbus_drv.c | 7 +------ include/asm-generic/mshyperv.h | 3 +++ 4 files changed, 28 insertions(+), 6 deletions(-) diff --git a/arch/arm64/hyperv/mshyperv.c b/arch/arm64/hyperv/mshyperv.c index 4fdc26ade1d7..d4494ceeaad0 100644 --- a/arch/arm64/hyperv/mshyperv.c +++ b/arch/arm64/hyperv/mshyperv.c @@ -134,3 +134,16 @@ bool hv_is_hyperv_initialized(void) return hyperv_initialized; } EXPORT_SYMBOL_GPL(hv_is_hyperv_initialized); + +static void (*vmbus_percpu_handler)(void); +void hv_setup_percpu_vmbus_handler(void (*handler)(void)) +{ + vmbus_percpu_handler =3D handler; +} + +irqreturn_t vmbus_percpu_isr(int irq, void *dev_id) +{ + if (vmbus_percpu_handler) + vmbus_percpu_handler(); + return IRQ_HANDLED; +} diff --git a/drivers/hv/hv_common.c b/drivers/hv/hv_common.c index d1ebc0ebd08f..a5064f558bf6 100644 --- a/drivers/hv/hv_common.c +++ b/drivers/hv/hv_common.c @@ -759,6 +759,17 @@ void __weak hv_setup_vmbus_handler(void (*handler)(voi= d)) } EXPORT_SYMBOL_GPL(hv_setup_vmbus_handler); =20 +irqreturn_t __weak vmbus_percpu_isr(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(vmbus_percpu_isr); + +void __weak hv_setup_percpu_vmbus_handler(void (*handler)(void)) +{ +} +EXPORT_SYMBOL_GPL(hv_setup_percpu_vmbus_handler); + void __weak hv_remove_vmbus_handler(void) { } diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index bc4fc1951ae1..f99d4f2d3862 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -1413,12 +1413,6 @@ void vmbus_isr(void) } EXPORT_SYMBOL_FOR_MODULES(vmbus_isr, "mshv_vtl"); =20 -static irqreturn_t vmbus_percpu_isr(int irq, void *dev_id) -{ - vmbus_isr(); - return IRQ_HANDLED; -} - static void vmbus_percpu_work(struct work_struct *work) { unsigned int cpu =3D smp_processor_id(); @@ -1520,6 +1514,7 @@ static int vmbus_bus_init(void) if (vmbus_irq =3D=3D -1) { hv_setup_vmbus_handler(vmbus_isr); } else { + hv_setup_percpu_vmbus_handler(vmbus_isr); ret =3D request_percpu_irq(vmbus_irq, vmbus_percpu_isr, "Hyper-V VMbus", &vmbus_evt); if (ret) { diff --git a/include/asm-generic/mshyperv.h b/include/asm-generic/mshyperv.h index 108f135d4fd9..b147a12085e4 100644 --- a/include/asm-generic/mshyperv.h +++ b/include/asm-generic/mshyperv.h @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -179,6 +180,8 @@ static inline u64 hv_generate_guest_id(u64 kernel_versi= on) =20 int hv_get_hypervisor_version(union hv_hypervisor_version_info *info); =20 +irqreturn_t vmbus_percpu_isr(int irq, void *dev_id); +void hv_setup_percpu_vmbus_handler(void (*handler)(void)); void hv_setup_vmbus_handler(void (*handler)(void)); void hv_remove_vmbus_handler(void); void hv_setup_stimer0_handler(void (*handler)(void)); --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DC4E13947A9; Mon, 16 Mar 2026 12:13:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; 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dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="NmhsNMT3" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id 81DE620B7007; Mon, 16 Mar 2026 05:13:15 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 81DE620B7007 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663202; bh=VIfrvp2Zb15HPzlWDtLGtp19d8nVZNMxlBCH9dINgV0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NmhsNMT3vtDvTLmAulaPhShGIoyisK20C/XW23aNcZ0GbqGZpFjYFykKgDIt/a2ZQ pc+kmM4mwT3eyIhpTAXiHrQG1NAxFbO7ABh+nraQPR3oiTFOCzOfw/FaPNSy2vvEKd 6irJWUMbFuUGiksS/f63PhfsyqVSImzD9OQiBZs0= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 04/11] Drivers: hv: Refactor mshv_vtl for ARM64 support to be added Date: Mon, 16 Mar 2026 12:12:34 +0000 Message-ID: <20260316121241.910764-5-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor MSHV_VTL driver to move some of the x86 specific code to arch specific files, and add corresponding functions for arm64. Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/arm64/include/asm/mshyperv.h | 10 +++ arch/x86/hyperv/hv_vtl.c | 98 ++++++++++++++++++++++++++++ arch/x86/include/asm/mshyperv.h | 1 + drivers/hv/mshv_vtl_main.c | 102 +----------------------------- 4 files changed, 111 insertions(+), 100 deletions(-) diff --git a/arch/arm64/include/asm/mshyperv.h b/arch/arm64/include/asm/msh= yperv.h index b721d3134ab6..804068e0941b 100644 --- a/arch/arm64/include/asm/mshyperv.h +++ b/arch/arm64/include/asm/mshyperv.h @@ -60,6 +60,16 @@ static inline u64 hv_get_non_nested_msr(unsigned int reg) ARM_SMCCC_SMC_64, \ ARM_SMCCC_OWNER_VENDOR_HYP, \ HV_SMCCC_FUNC_NUMBER) +#ifdef CONFIG_HYPERV_VTL_MODE +/* + * Get/Set the register. If the function returns `1`, that must be done via + * a hypercall. Returning `0` means success. + */ +static inline int hv_vtl_get_set_reg(struct hv_register_assoc *regs, bool = set, u64 shared) +{ + return 1; +} +#endif =20 #include =20 diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 9b6a9bc4ab76..72a0bb4ae0c7 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include <../kernel/smpboot.h> #include "../../kernel/fpu/legacy.h" @@ -281,3 +283,99 @@ void mshv_vtl_return_call(struct mshv_vtl_cpu_context = *vtl0) kernel_fpu_end(); } EXPORT_SYMBOL(mshv_vtl_return_call); + +/* Static table mapping register names to their corresponding actions */ +static const struct { + enum hv_register_name reg_name; + int debug_reg_num; /* -1 if not a debug register */ + u32 msr_addr; /* 0 if not an MSR */ +} reg_table[] =3D { + /* Debug registers */ + {HV_X64_REGISTER_DR0, 0, 0}, + {HV_X64_REGISTER_DR1, 1, 0}, + {HV_X64_REGISTER_DR2, 2, 0}, + {HV_X64_REGISTER_DR3, 3, 0}, + {HV_X64_REGISTER_DR6, 6, 0}, + /* MTRR MSRs */ + {HV_X64_REGISTER_MSR_MTRR_CAP, -1, MSR_MTRRcap}, + {HV_X64_REGISTER_MSR_MTRR_DEF_TYPE, -1, MSR_MTRRdefType}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0, -1, MTRRphysBase_MSR(0)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1, -1, MTRRphysBase_MSR(1)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2, -1, MTRRphysBase_MSR(2)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3, -1, MTRRphysBase_MSR(3)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4, -1, MTRRphysBase_MSR(4)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5, -1, MTRRphysBase_MSR(5)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6, -1, MTRRphysBase_MSR(6)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7, -1, MTRRphysBase_MSR(7)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8, -1, MTRRphysBase_MSR(8)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9, -1, MTRRphysBase_MSR(9)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA, -1, MTRRphysBase_MSR(0xa)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB, -1, MTRRphysBase_MSR(0xb)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC, -1, MTRRphysBase_MSR(0xc)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASED, -1, MTRRphysBase_MSR(0xd)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE, -1, MTRRphysBase_MSR(0xe)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF, -1, MTRRphysBase_MSR(0xf)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0, -1, MTRRphysMask_MSR(0)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1, -1, MTRRphysMask_MSR(1)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2, -1, MTRRphysMask_MSR(2)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3, -1, MTRRphysMask_MSR(3)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4, -1, MTRRphysMask_MSR(4)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5, -1, MTRRphysMask_MSR(5)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6, -1, MTRRphysMask_MSR(6)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7, -1, MTRRphysMask_MSR(7)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8, -1, MTRRphysMask_MSR(8)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9, -1, MTRRphysMask_MSR(9)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA, -1, MTRRphysMask_MSR(0xa)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB, -1, MTRRphysMask_MSR(0xb)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC, -1, MTRRphysMask_MSR(0xc)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD, -1, MTRRphysMask_MSR(0xd)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE, -1, MTRRphysMask_MSR(0xe)}, + {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF, -1, MTRRphysMask_MSR(0xf)}, + {HV_X64_REGISTER_MSR_MTRR_FIX64K00000, -1, MSR_MTRRfix64K_00000}, + {HV_X64_REGISTER_MSR_MTRR_FIX16K80000, -1, MSR_MTRRfix16K_80000}, + {HV_X64_REGISTER_MSR_MTRR_FIX16KA0000, -1, MSR_MTRRfix16K_A0000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KC0000, -1, MSR_MTRRfix4K_C0000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KC8000, -1, MSR_MTRRfix4K_C8000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KD0000, -1, MSR_MTRRfix4K_D0000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KD8000, -1, MSR_MTRRfix4K_D8000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KE0000, -1, MSR_MTRRfix4K_E0000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KE8000, -1, MSR_MTRRfix4K_E8000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KF0000, -1, MSR_MTRRfix4K_F0000}, + {HV_X64_REGISTER_MSR_MTRR_FIX4KF8000, -1, MSR_MTRRfix4K_F8000}, +}; + +int hv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set, u64 share= d) +{ + u64 *reg64; + enum hv_register_name gpr_name; + int i; + + gpr_name =3D regs->name; + reg64 =3D ®s->value.reg64; + + /* Search for the register in the table */ + for (i =3D 0; i < ARRAY_SIZE(reg_table); i++) { + if (reg_table[i].reg_name !=3D gpr_name) + continue; + if (reg_table[i].debug_reg_num !=3D -1) { + /* Handle debug registers */ + if (gpr_name =3D=3D HV_X64_REGISTER_DR6 && !shared) + goto hypercall; + if (set) + native_set_debugreg(reg_table[i].debug_reg_num, *reg64); + else + *reg64 =3D native_get_debugreg(reg_table[i].debug_reg_num); + } else { + /* Handle MSRs */ + if (set) + wrmsrl(reg_table[i].msr_addr, *reg64); + else + rdmsrl(reg_table[i].msr_addr, *reg64); + } + return 0; + } + +hypercall: + return 1; +} +EXPORT_SYMBOL(hv_vtl_get_set_reg); diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyper= v.h index f64393e853ee..d5355a5b7517 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -304,6 +304,7 @@ void mshv_vtl_return_call(struct mshv_vtl_cpu_context *= vtl0); void mshv_vtl_return_call_init(u64 vtl_return_offset); void mshv_vtl_return_hypercall(void); void __mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0); +int hv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set, u64 share= d); #else static inline void __init hv_vtl_init_platform(void) {} static inline int __init hv_vtl_early_init(void) { return 0; } diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index 5856975f32e1..b607b6e7e121 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -19,10 +19,8 @@ #include #include #include -#include #include #include -#include #include #include =20 @@ -505,102 +503,6 @@ static int mshv_vtl_ioctl_set_poll_file(struct mshv_v= tl_set_poll_file __user *us return 0; } =20 -/* Static table mapping register names to their corresponding actions */ -static const struct { - enum hv_register_name reg_name; - int debug_reg_num; /* -1 if not a debug register */ - u32 msr_addr; /* 0 if not an MSR */ -} reg_table[] =3D { - /* Debug registers */ - {HV_X64_REGISTER_DR0, 0, 0}, - {HV_X64_REGISTER_DR1, 1, 0}, - {HV_X64_REGISTER_DR2, 2, 0}, - {HV_X64_REGISTER_DR3, 3, 0}, - {HV_X64_REGISTER_DR6, 6, 0}, - /* MTRR MSRs */ - {HV_X64_REGISTER_MSR_MTRR_CAP, -1, MSR_MTRRcap}, - {HV_X64_REGISTER_MSR_MTRR_DEF_TYPE, -1, MSR_MTRRdefType}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0, -1, MTRRphysBase_MSR(0)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1, -1, MTRRphysBase_MSR(1)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2, -1, MTRRphysBase_MSR(2)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3, -1, MTRRphysBase_MSR(3)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4, -1, MTRRphysBase_MSR(4)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5, -1, MTRRphysBase_MSR(5)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6, -1, MTRRphysBase_MSR(6)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7, -1, MTRRphysBase_MSR(7)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8, -1, MTRRphysBase_MSR(8)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9, -1, MTRRphysBase_MSR(9)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA, -1, MTRRphysBase_MSR(0xa)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB, -1, MTRRphysBase_MSR(0xb)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC, -1, MTRRphysBase_MSR(0xc)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASED, -1, MTRRphysBase_MSR(0xd)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE, -1, MTRRphysBase_MSR(0xe)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF, -1, MTRRphysBase_MSR(0xf)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0, -1, MTRRphysMask_MSR(0)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1, -1, MTRRphysMask_MSR(1)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2, -1, MTRRphysMask_MSR(2)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3, -1, MTRRphysMask_MSR(3)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4, -1, MTRRphysMask_MSR(4)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5, -1, MTRRphysMask_MSR(5)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6, -1, MTRRphysMask_MSR(6)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7, -1, MTRRphysMask_MSR(7)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8, -1, MTRRphysMask_MSR(8)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9, -1, MTRRphysMask_MSR(9)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA, -1, MTRRphysMask_MSR(0xa)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB, -1, MTRRphysMask_MSR(0xb)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC, -1, MTRRphysMask_MSR(0xc)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD, -1, MTRRphysMask_MSR(0xd)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE, -1, MTRRphysMask_MSR(0xe)}, - {HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF, -1, MTRRphysMask_MSR(0xf)}, - {HV_X64_REGISTER_MSR_MTRR_FIX64K00000, -1, MSR_MTRRfix64K_00000}, - {HV_X64_REGISTER_MSR_MTRR_FIX16K80000, -1, MSR_MTRRfix16K_80000}, - {HV_X64_REGISTER_MSR_MTRR_FIX16KA0000, -1, MSR_MTRRfix16K_A0000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KC0000, -1, MSR_MTRRfix4K_C0000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KC8000, -1, MSR_MTRRfix4K_C8000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KD0000, -1, MSR_MTRRfix4K_D0000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KD8000, -1, MSR_MTRRfix4K_D8000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KE0000, -1, MSR_MTRRfix4K_E0000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KE8000, -1, MSR_MTRRfix4K_E8000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KF0000, -1, MSR_MTRRfix4K_F0000}, - {HV_X64_REGISTER_MSR_MTRR_FIX4KF8000, -1, MSR_MTRRfix4K_F8000}, -}; - -static int mshv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set) -{ - u64 *reg64; - enum hv_register_name gpr_name; - int i; - - gpr_name =3D regs->name; - reg64 =3D ®s->value.reg64; - - /* Search for the register in the table */ - for (i =3D 0; i < ARRAY_SIZE(reg_table); i++) { - if (reg_table[i].reg_name !=3D gpr_name) - continue; - if (reg_table[i].debug_reg_num !=3D -1) { - /* Handle debug registers */ - if (gpr_name =3D=3D HV_X64_REGISTER_DR6 && - !mshv_vsm_capabilities.dr6_shared) - goto hypercall; - if (set) - native_set_debugreg(reg_table[i].debug_reg_num, *reg64); - else - *reg64 =3D native_get_debugreg(reg_table[i].debug_reg_num); - } else { - /* Handle MSRs */ - if (set) - wrmsrl(reg_table[i].msr_addr, *reg64); - else - rdmsrl(reg_table[i].msr_addr, *reg64); - } - return 0; - } - -hypercall: - return 1; -} - static void mshv_vtl_return(struct mshv_vtl_cpu_context *vtl0) { struct hv_vp_assist_page *hvp; @@ -720,7 +622,7 @@ mshv_vtl_ioctl_get_regs(void __user *user_args) sizeof(reg))) return -EFAULT; =20 - ret =3D mshv_vtl_get_set_reg(®, false); + ret =3D hv_vtl_get_set_reg(®, false, mshv_vsm_capabilities.dr6_shared); if (!ret) goto copy_args; /* No need of hypercall */ ret =3D vtl_get_vp_register(®); @@ -751,7 +653,7 @@ mshv_vtl_ioctl_set_regs(void __user *user_args) if (copy_from_user(®, (void __user *)args.regs_ptr, sizeof(reg))) return -EFAULT; =20 - ret =3D mshv_vtl_get_set_reg(®, true); + ret =3D hv_vtl_get_set_reg(®, true, mshv_vsm_capabilities.dr6_shared); if (!ret) return ret; /* No need of hypercall */ ret =3D vtl_set_vp_register(®); --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3B1D539478C; Mon, 16 Mar 2026 12:13:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663211; cv=none; b=VxgOZfg0DX9wZ6GiN++LbsaisnjGTtKiFt3/BkILtaronMOq0Vb9POH2KuXOeDDZec1/qK5+DRVXcT1jcQ+5u1nKX4PegxstpW/8nxMcanN0Emaj5IFMdL3Ik2HPS5LRPpI1ml3Nq1g1znHEkIfrNFqzY1zEYKSqlI6a4jX6lPE= ARC-Message-Signature: i=1; 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Mon, 16 Mar 2026 05:13:23 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4E24E20B7017 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663210; bh=46FOvu173yz/45+2tHFqqCdlI7TqogjbgR44sdGBrs4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RJON6Msr3CvOqx1hzDUbXbmZABaCXsa+3ownuDxRU5dOGsJXmHBboZyW6LhEMVD8C 3+WLu8gfADivo5Dzhgz41DqONk3JZej3vYsDY2zh+6LlrYw+zYD+Nqeo7MV72M3uMK yAhikSYcK6VeSBPcdw0Awn+wjuhIDKlbjSdjQtww= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 05/11] drivers: hv: Export vmbus_interrupt for mshv_vtl module Date: Mon, 16 Mar 2026 12:12:35 +0000 Message-ID: <20260316121241.910764-6-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vmbus_interrupt is used in mshv_vtl_main.c to set the SINT vector. When CONFIG_MSHV_VTL=3Dm and CONFIG_HYPERV_VMBUS=3Dy (built-in), the module cannot access vmbus_interrupt at load time since it is not exported. Export it using EXPORT_SYMBOL_FOR_MODULES consistent with the existing pattern used for vmbus_isr. Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- drivers/hv/vmbus_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index f99d4f2d3862..de191799a8f6 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -57,6 +57,7 @@ static DEFINE_PER_CPU(long, vmbus_evt); /* Values parsed from ACPI DSDT */ int vmbus_irq; int vmbus_interrupt; +EXPORT_SYMBOL_FOR_MODULES(vmbus_interrupt, "mshv_vtl"); =20 /* * If the Confidential VMBus is used, the data on the "wire" is not --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BB6D726D4DD; Mon, 16 Mar 2026 12:13:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663218; cv=none; b=lMNuEi0HUR4PGpbIS7CrcFI8MhJ+M5K+WoNpd8sS9selhLtnG/rgRv1IO05eGZNHncsxb0foK9e3ozMRAImlOQBTHJB+M7IZNIqhMZzxPYCPxSI4if4tQujnAIEC4HIXgaXcSNoWgCb5qv81Q2gN4fqT4QZ6IKcCDbXWzB1A5Co= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663218; c=relaxed/simple; bh=qCyY3pKjxPVQikljorU7QNeL/LYi64ZDGCIxpmrYkuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EZoeBeT+TmtfOVYgG/w0/VpIutoo4TrZEX4gwqpo4J1SN46WYrYz1RXGLAIBxlfZSkLW2BBvIf5YPh5Qj4cb5wNIWZCgHK0I+iKgp5RCP8wHI64n++frsMyxFrQflccEC3ng/R9s2u6SBM8pkMfwYewO6mEd+2ib3Q5yOZSa2Mo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=kCmKGzvY; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="kCmKGzvY" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id AE44A20B700D; Mon, 16 Mar 2026 05:13:30 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com AE44A20B700D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663217; bh=qxNzXROiVNr7+UUfLEumcf/CNbcQ/TPD3rd4fIb/4jg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kCmKGzvYncQUiJWqt/Z+9Vj+di6RNMWorU0zQ9qy98ppbIh3yfCTkOqXutmuqfRuQ OoH54gVCHkASeGsnZT/6YU3F/B9laj8xfw9AUZW00PHzw1Qk8Fp19j9waS1QC/2cKz Y4hKnRWh7cuVVoAHR6tNkmU20pZZ+K6ceIejoD4g= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 06/11] Drivers: hv: Make sint vector architecture neutral in MSHV_VTL Date: Mon, 16 Mar 2026 12:12:36 +0000 Message-ID: <20260316121241.910764-7-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Generalize Synthetic interrupt source vector (sint) to use vmbus_interrupt variable instead, which automatically takes care of architectures where HYPERVISOR_CALLBACK_VECTOR is not present (arm64). Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- drivers/hv/mshv_vtl_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index b607b6e7e121..91517b45d526 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -234,7 +234,7 @@ static void mshv_vtl_synic_enable_regs(unsigned int cpu) union hv_synic_sint sint; =20 sint.as_uint64 =3D 0; - sint.vector =3D HYPERVISOR_CALLBACK_VECTOR; + sint.vector =3D vmbus_interrupt; sint.masked =3D false; sint.auto_eoi =3D hv_recommend_using_aeoi(); =20 @@ -753,7 +753,7 @@ static void mshv_vtl_synic_mask_vmbus_sint(void *info) const u8 *mask =3D info; =20 sint.as_uint64 =3D 0; - sint.vector =3D HYPERVISOR_CALLBACK_VECTOR; + sint.vector =3D vmbus_interrupt; sint.masked =3D (*mask !=3D 0); sint.auto_eoi =3D hv_recommend_using_aeoi(); =20 --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 529E4393DC8; Mon, 16 Mar 2026 12:13:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663226; cv=none; b=G/kCCaaNu6qic6Fn+fCEq+X6yZJ5k7Wxkvy/aYcoRvaJyhLjEh/20+sXmdvoECE2qqQwcsOXcpSdIvPmUf6yF1z5ErIuiF0RWG45V3CQkvehv6CRUYCdWc4IVGB4rCaZ9N3G05NCEXSNwhqu5uGKvUl+rjhKZBW0+JMLPxppQtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663226; c=relaxed/simple; bh=ew4OLXaKa/VEOhywLww/RwOwY/l6rGyQoPvsHI1OtH8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ddsK9FfwRopwcT0erJfF7MlyN0Q9m0KJTe2sI4JjT7kWVB/vZaCW95oxZrukeeeIs2L4Lw9bP5yzRD89/QwIQOVxirEcZHVY/7HKVPRPNtYkLz60N574kUhUmtZDhdZWpoDiaFUmOHrFfxBUAp/xQRM52xR/A4mgeax+55dqZz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=CZal1OYp; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="CZal1OYp" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id 33D3E20B703B; Mon, 16 Mar 2026 05:13:38 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 33D3E20B703B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663224; bh=GwjABt8xrFvoH7ZbgJDHm6kXbTG4KspJ2spl33ai+WY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CZal1OYpxJYAztHQ7f79dut5iyAY+Y2ZHXrECTf0ilMhwSmgfQkMwJrVRp/W+lLoR 8AXcLyQuytXiVlQP+x6XF9OA7NfN4J2XmytqA12ilnmQl6Dx66NcZVti1b9XfpikCP STY5cXWemVOfEbXBKMSuEvelqdIWQU7wvKC0n4Hw= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 07/11] arch: arm64: Add support for mshv_vtl_return_call Date: Mon, 16 Mar 2026 12:12:37 +0000 Message-ID: <20260316121241.910764-8-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for arm64 specific variant of mshv_vtl_return_call function to be able to add support for arm64 in MSHV_VTL driver. This would help enable the transition between Virtual Trust Levels (VTL) in MSHV_VTL when the kernel acts as a paravisor. Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/arm64/hyperv/Makefile | 1 + arch/arm64/hyperv/hv_vtl.c | 144 ++++++++++++++++++++++++++++++ arch/arm64/include/asm/mshyperv.h | 13 +++ 3 files changed, 158 insertions(+) create mode 100644 arch/arm64/hyperv/hv_vtl.c diff --git a/arch/arm64/hyperv/Makefile b/arch/arm64/hyperv/Makefile index 87c31c001da9..9701a837a6e1 100644 --- a/arch/arm64/hyperv/Makefile +++ b/arch/arm64/hyperv/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-y :=3D hv_core.o mshyperv.o +obj-$(CONFIG_HYPERV_VTL_MODE) +=3D hv_vtl.o diff --git a/arch/arm64/hyperv/hv_vtl.c b/arch/arm64/hyperv/hv_vtl.c new file mode 100644 index 000000000000..66318672c242 --- /dev/null +++ b/arch/arm64/hyperv/hv_vtl.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Microsoft, Inc. + * + * Authors: + * Roman Kisel + * Naman Jain + */ + +#include +#include +#include + +void mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0) +{ + u64 base_ptr =3D (u64)vtl0->x; + + /* + * VTL switch for ARM64 platform - managing VTL0's CPU context. + * We explicitly use the stack to save the base pointer, and use x16 + * as our working register for accessing the context structure. + * + * Register Handling: + * - X0-X17: Saved/restored (general-purpose, shared for VTL communicatio= n) + * - X18: NOT touched - hypervisor-managed per-VTL (platform register) + * - X19-X30: Saved/restored (part of VTL0's execution context) + * - Q0-Q31: Saved/restored (128-bit NEON/floating-point registers, share= d) + * - SP: Not in structure, hypervisor-managed per-VTL + * + * Note: X29 (FP) and X30 (LR) are in the structure and must be saved/res= tored + * as part of VTL0's complete execution state. + */ + asm __volatile__ ( + /* Save base pointer to stack explicitly, then load into x16 */ + "str %0, [sp, #-16]!\n\t" /* Push base pointer onto stack */ + "mov x16, %0\n\t" /* Load base pointer into x16 */ + /* Volatile registers (Windows ARM64 ABI: x0-x15) */ + "ldp x0, x1, [x16]\n\t" + "ldp x2, x3, [x16, #(2*8)]\n\t" + "ldp x4, x5, [x16, #(4*8)]\n\t" + "ldp x6, x7, [x16, #(6*8)]\n\t" + "ldp x8, x9, [x16, #(8*8)]\n\t" + "ldp x10, x11, [x16, #(10*8)]\n\t" + "ldp x12, x13, [x16, #(12*8)]\n\t" + "ldp x14, x15, [x16, #(14*8)]\n\t" + /* x16 will be loaded last, after saving base pointer */ + "ldr x17, [x16, #(17*8)]\n\t" + /* x18 is hypervisor-managed per-VTL - DO NOT LOAD */ + + /* General-purpose registers: x19-x30 */ + "ldp x19, x20, [x16, #(19*8)]\n\t" + "ldp x21, x22, [x16, #(21*8)]\n\t" + "ldp x23, x24, [x16, #(23*8)]\n\t" + "ldp x25, x26, [x16, #(25*8)]\n\t" + "ldp x27, x28, [x16, #(27*8)]\n\t" + + /* Frame pointer and link register */ + "ldp x29, x30, [x16, #(29*8)]\n\t" + + /* Shared NEON/FP registers: Q0-Q31 (128-bit) */ + "ldp q0, q1, [x16, #(32*8)]\n\t" + "ldp q2, q3, [x16, #(32*8 + 2*16)]\n\t" + "ldp q4, q5, [x16, #(32*8 + 4*16)]\n\t" + "ldp q6, q7, [x16, #(32*8 + 6*16)]\n\t" + "ldp q8, q9, [x16, #(32*8 + 8*16)]\n\t" + "ldp q10, q11, [x16, #(32*8 + 10*16)]\n\t" + "ldp q12, q13, [x16, #(32*8 + 12*16)]\n\t" + "ldp q14, q15, [x16, #(32*8 + 14*16)]\n\t" + "ldp q16, q17, [x16, #(32*8 + 16*16)]\n\t" + "ldp q18, q19, [x16, #(32*8 + 18*16)]\n\t" + "ldp q20, q21, [x16, #(32*8 + 20*16)]\n\t" + "ldp q22, q23, [x16, #(32*8 + 22*16)]\n\t" + "ldp q24, q25, [x16, #(32*8 + 24*16)]\n\t" + "ldp q26, q27, [x16, #(32*8 + 26*16)]\n\t" + "ldp q28, q29, [x16, #(32*8 + 28*16)]\n\t" + "ldp q30, q31, [x16, #(32*8 + 30*16)]\n\t" + + /* Now load x16 itself */ + "ldr x16, [x16, #(16*8)]\n\t" + + /* Return to the lower VTL */ + "hvc #3\n\t" + + /* Save context after return - reload base pointer from stack */ + "stp x16, x17, [sp, #-16]!\n\t" /* Save x16, x17 temporarily */ + "ldr x16, [sp, #16]\n\t" /* Reload base pointer (skip saved x16,x= 17) */ + + /* Volatile registers */ + "stp x0, x1, [x16]\n\t" + "stp x2, x3, [x16, #(2*8)]\n\t" + "stp x4, x5, [x16, #(4*8)]\n\t" + "stp x6, x7, [x16, #(6*8)]\n\t" + "stp x8, x9, [x16, #(8*8)]\n\t" + "stp x10, x11, [x16, #(10*8)]\n\t" + "stp x12, x13, [x16, #(12*8)]\n\t" + "stp x14, x15, [x16, #(14*8)]\n\t" + "ldp x0, x1, [sp], #16\n\t" /* Recover saved x16, x17 */ + "stp x0, x1, [x16, #(16*8)]\n\t" + /* x18 is hypervisor-managed - DO NOT SAVE */ + + /* General-purpose registers: x19-x30 */ + "stp x19, x20, [x16, #(19*8)]\n\t" + "stp x21, x22, [x16, #(21*8)]\n\t" + "stp x23, x24, [x16, #(23*8)]\n\t" + "stp x25, x26, [x16, #(25*8)]\n\t" + "stp x27, x28, [x16, #(27*8)]\n\t" + "stp x29, x30, [x16, #(29*8)]\n\t" /* Frame pointer and link register */ + + /* Shared NEON/FP registers: Q0-Q31 (128-bit) */ + "stp q0, q1, [x16, #(32*8)]\n\t" + "stp q2, q3, [x16, #(32*8 + 2*16)]\n\t" + "stp q4, q5, [x16, #(32*8 + 4*16)]\n\t" + "stp q6, q7, [x16, #(32*8 + 6*16)]\n\t" + "stp q8, q9, [x16, #(32*8 + 8*16)]\n\t" + "stp q10, q11, [x16, #(32*8 + 10*16)]\n\t" + "stp q12, q13, [x16, #(32*8 + 12*16)]\n\t" + "stp q14, q15, [x16, #(32*8 + 14*16)]\n\t" + "stp q16, q17, [x16, #(32*8 + 16*16)]\n\t" + "stp q18, q19, [x16, #(32*8 + 18*16)]\n\t" + "stp q20, q21, [x16, #(32*8 + 20*16)]\n\t" + "stp q22, q23, [x16, #(32*8 + 22*16)]\n\t" + "stp q24, q25, [x16, #(32*8 + 24*16)]\n\t" + "stp q26, q27, [x16, #(32*8 + 26*16)]\n\t" + "stp q28, q29, [x16, #(32*8 + 28*16)]\n\t" + "stp q30, q31, [x16, #(32*8 + 30*16)]\n\t" + + /* Clean up stack - pop base pointer */ + "add sp, sp, #16\n\t" + + : /* No outputs */ + : /* Input */ "r"(base_ptr) + : /* Clobber list - x16 used as base, x18 is hypervisor-managed (not tou= ched) */ + "memory", "cc", + "x0", "x1", "x2", "x3", "x4", "x5", + "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", + "x14", "x15", "x16", "x17", "x19", "x20", "x21", + "x22", "x23", "x24", "x25", "x26", "x27", "x28", + "x29", "x30", + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); +} +EXPORT_SYMBOL(mshv_vtl_return_call); diff --git a/arch/arm64/include/asm/mshyperv.h b/arch/arm64/include/asm/msh= yperv.h index 804068e0941b..de7f3a41a8ea 100644 --- a/arch/arm64/include/asm/mshyperv.h +++ b/arch/arm64/include/asm/mshyperv.h @@ -60,6 +60,17 @@ static inline u64 hv_get_non_nested_msr(unsigned int reg) ARM_SMCCC_SMC_64, \ ARM_SMCCC_OWNER_VENDOR_HYP, \ HV_SMCCC_FUNC_NUMBER) + +struct mshv_vtl_cpu_context { +/* + * NOTE: x18 is managed by the hypervisor. It won't be reloaded from this = array. + * It is included here for convenience in the common case. + */ + __u64 x[31]; + __u64 rsvd; + __uint128_t q[32]; +}; + #ifdef CONFIG_HYPERV_VTL_MODE /* * Get/Set the register. If the function returns `1`, that must be done via @@ -69,6 +80,8 @@ static inline int hv_vtl_get_set_reg(struct hv_register_a= ssoc *regs, bool set, u { return 1; } + +void mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0); #endif =20 #include --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1DB7839448D; Mon, 16 Mar 2026 12:13:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663234; cv=none; b=p7TSJtbpUYbfroKSnLJlQGwqVtD8w8LtNlFN+mGjFWf4daILq/ZfD+X0N8oRt4+lDg1zrMXc31UxznD+Xi/0mOS86H4uTwdUtlbjqrFT0Y2I6MDEcwdKBj0ntoycgu0KRUTJutYzDlt/u6M47+fQTjtEVxD+5bV9gfh6uEgzcKo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663234; c=relaxed/simple; bh=xObn5BR89Oo8C2UbIZEan/6TxA4L35AviXUECDEMVZU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uRspL0megxmAlkg9ZDDy6CxirxkCQcNhmZwufWGUKBZaFpwLyHxwQ6AyafGLdwL+22pTIvb/GxWAT+eJ89cGHwomezMFsUNxHTnO/Qx9v0/0Iu/B9gccNljRiWhN4Al3tYUY7rr9KRhaxoBiZ2wr05jRtsrLcz8iC/g8S4pjuc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=Hj+uRwP4; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="Hj+uRwP4" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id DFB7C20B6F08; Mon, 16 Mar 2026 05:13:45 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com DFB7C20B6F08 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663232; bh=brR9theQCqP7K9pyo73r1JXfQPBuayIYZqSB2HUPid4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hj+uRwP4UTcKRFjAytMxjsCb5OQgvzAillEr6r8JYoXSqL83gJgbvUxTmaw//IEI4 aLRPdgDzTT28clUSYxT5RwVDnYcP1HNo4j0vdaJCWiuS0mKk/VHRh4BVHu0q3XXHzF 3agYTN2tB/AsoUCbiwtVkL6eomJxukXxrUFRYbes= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 08/11] Drivers: hv: mshv_vtl: Move register page config to arch-specific files Date: Mon, 16 Mar 2026 12:12:38 +0000 Message-ID: <20260316121241.910764-9-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move mshv_vtl_configure_reg_page() implementation from drivers/hv/mshv_vtl_main.c to arch-specific files: - arch/x86/hyperv/hv_vtl.c: full implementation with register page setup - arch/arm64/hyperv/hv_vtl.c: stub implementation (unsupported) Move common type definitions to include/asm-generic/mshyperv.h: - struct mshv_vtl_per_cpu - union hv_synic_overlay_page_msr Move hv_call_get_vp_registers() and hv_call_set_vp_registers() declarations to include/asm-generic/mshyperv.h since these functions are used by multiple modules. While at it, remove the unnecessary stub implementations in #else case for mshv_vtl_return* functions in arch/x86/include/asm/mshyperv.h. This is essential for adding support for ARM64 in MSHV_VTL. Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/arm64/hyperv/hv_vtl.c | 8 +++++ arch/arm64/include/asm/mshyperv.h | 3 ++ arch/x86/hyperv/hv_vtl.c | 32 ++++++++++++++++++++ arch/x86/include/asm/mshyperv.h | 7 ++--- drivers/hv/mshv.h | 8 ----- drivers/hv/mshv_vtl_main.c | 49 +++---------------------------- include/asm-generic/mshyperv.h | 42 ++++++++++++++++++++++++++ 7 files changed, 92 insertions(+), 57 deletions(-) diff --git a/arch/arm64/hyperv/hv_vtl.c b/arch/arm64/hyperv/hv_vtl.c index 66318672c242..d699138427c1 100644 --- a/arch/arm64/hyperv/hv_vtl.c +++ b/arch/arm64/hyperv/hv_vtl.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 void mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0) { @@ -142,3 +143,10 @@ void mshv_vtl_return_call(struct mshv_vtl_cpu_context = *vtl0) "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); } EXPORT_SYMBOL(mshv_vtl_return_call); + +bool hv_vtl_configure_reg_page(struct mshv_vtl_per_cpu *per_cpu) +{ + pr_debug("Register page not supported on ARM64\n"); + return false; +} +EXPORT_SYMBOL_GPL(hv_vtl_configure_reg_page); diff --git a/arch/arm64/include/asm/mshyperv.h b/arch/arm64/include/asm/msh= yperv.h index de7f3a41a8ea..36803f0386cc 100644 --- a/arch/arm64/include/asm/mshyperv.h +++ b/arch/arm64/include/asm/mshyperv.h @@ -61,6 +61,8 @@ static inline u64 hv_get_non_nested_msr(unsigned int reg) ARM_SMCCC_OWNER_VENDOR_HYP, \ HV_SMCCC_FUNC_NUMBER) =20 +struct mshv_vtl_per_cpu; + struct mshv_vtl_cpu_context { /* * NOTE: x18 is managed by the hypervisor. It won't be reloaded from this = array. @@ -82,6 +84,7 @@ static inline int hv_vtl_get_set_reg(struct hv_register_a= ssoc *regs, bool set, u } =20 void mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0); +bool hv_vtl_configure_reg_page(struct mshv_vtl_per_cpu *per_cpu); #endif =20 #include diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 72a0bb4ae0c7..ede290985d41 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -20,6 +20,7 @@ #include #include #include +#include #include <../kernel/smpboot.h> #include "../../kernel/fpu/legacy.h" =20 @@ -259,6 +260,37 @@ int __init hv_vtl_early_init(void) return 0; } =20 +static const union hv_input_vtl input_vtl_zero; + +bool hv_vtl_configure_reg_page(struct mshv_vtl_per_cpu *per_cpu) +{ + struct hv_register_assoc reg_assoc =3D {}; + union hv_synic_overlay_page_msr overlay =3D {}; + struct page *reg_page; + + reg_page =3D alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_RETRY_MAYFAIL); + if (!reg_page) { + WARN(1, "failed to allocate register page\n"); + return false; + } + + overlay.enabled =3D 1; + overlay.pfn =3D page_to_hvpfn(reg_page); + reg_assoc.name =3D HV_X64_REGISTER_REG_PAGE; + reg_assoc.value.reg64 =3D overlay.as_uint64; + + if (hv_call_set_vp_registers(HV_VP_INDEX_SELF, HV_PARTITION_ID_SELF, + 1, input_vtl_zero, ®_assoc)) { + WARN(1, "failed to setup register page\n"); + __free_page(reg_page); + return false; + } + + per_cpu->reg_page =3D reg_page; + return true; +} +EXPORT_SYMBOL_GPL(hv_vtl_configure_reg_page); + DEFINE_STATIC_CALL_NULL(__mshv_vtl_return_hypercall, void (*)(void)); =20 void mshv_vtl_return_call_init(u64 vtl_return_offset) diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyper= v.h index d5355a5b7517..d592fea49cdb 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -271,6 +271,8 @@ static inline u64 hv_get_non_nested_msr(unsigned int re= g) { return 0; } static inline int hv_apicid_to_vp_index(u32 apic_id) { return -EINVAL; } #endif /* CONFIG_HYPERV */ =20 +struct mshv_vtl_per_cpu; + struct mshv_vtl_cpu_context { union { struct { @@ -305,13 +307,10 @@ void mshv_vtl_return_call_init(u64 vtl_return_offset); void mshv_vtl_return_hypercall(void); void __mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0); int hv_vtl_get_set_reg(struct hv_register_assoc *regs, bool set, u64 share= d); +bool hv_vtl_configure_reg_page(struct mshv_vtl_per_cpu *per_cpu); #else static inline void __init hv_vtl_init_platform(void) {} static inline int __init hv_vtl_early_init(void) { return 0; } -static inline void mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0)= {} -static inline void mshv_vtl_return_call_init(u64 vtl_return_offset) {} -static inline void mshv_vtl_return_hypercall(void) {} -static inline void __mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl= 0) {} #endif =20 #include diff --git a/drivers/hv/mshv.h b/drivers/hv/mshv.h index d4813df92b9c..0fcb7f9ba6a9 100644 --- a/drivers/hv/mshv.h +++ b/drivers/hv/mshv.h @@ -14,14 +14,6 @@ memchr_inv(&((STRUCT).MEMBER), \ 0, sizeof_field(typeof(STRUCT), MEMBER)) =20 -int hv_call_get_vp_registers(u32 vp_index, u64 partition_id, u16 count, - union hv_input_vtl input_vtl, - struct hv_register_assoc *registers); - -int hv_call_set_vp_registers(u32 vp_index, u64 partition_id, u16 count, - union hv_input_vtl input_vtl, - struct hv_register_assoc *registers); - int hv_call_get_partition_property(u64 partition_id, u64 property_code, u64 *property_value); =20 diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index 91517b45d526..c79d24317b8e 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -78,21 +78,6 @@ struct mshv_vtl { u64 id; }; =20 -struct mshv_vtl_per_cpu { - struct mshv_vtl_run *run; - struct page *reg_page; -}; - -/* SYNIC_OVERLAY_PAGE_MSR - internal, identical to hv_synic_simp */ -union hv_synic_overlay_page_msr { - u64 as_uint64; - struct { - u64 enabled: 1; - u64 reserved: 11; - u64 pfn: 52; - } __packed; -}; - static struct mutex mshv_vtl_poll_file_lock; static union hv_register_vsm_page_offsets mshv_vsm_page_offsets; static union hv_register_vsm_capabilities mshv_vsm_capabilities; @@ -201,34 +186,6 @@ static struct page *mshv_vtl_cpu_reg_page(int cpu) return *per_cpu_ptr(&mshv_vtl_per_cpu.reg_page, cpu); } =20 -static void mshv_vtl_configure_reg_page(struct mshv_vtl_per_cpu *per_cpu) -{ - struct hv_register_assoc reg_assoc =3D {}; - union hv_synic_overlay_page_msr overlay =3D {}; - struct page *reg_page; - - reg_page =3D alloc_page(GFP_KERNEL | __GFP_ZERO | __GFP_RETRY_MAYFAIL); - if (!reg_page) { - WARN(1, "failed to allocate register page\n"); - return; - } - - overlay.enabled =3D 1; - overlay.pfn =3D page_to_hvpfn(reg_page); - reg_assoc.name =3D HV_X64_REGISTER_REG_PAGE; - reg_assoc.value.reg64 =3D overlay.as_uint64; - - if (hv_call_set_vp_registers(HV_VP_INDEX_SELF, HV_PARTITION_ID_SELF, - 1, input_vtl_zero, ®_assoc)) { - WARN(1, "failed to setup register page\n"); - __free_page(reg_page); - return; - } - - per_cpu->reg_page =3D reg_page; - mshv_has_reg_page =3D true; -} - static void mshv_vtl_synic_enable_regs(unsigned int cpu) { union hv_synic_sint sint; @@ -329,8 +286,10 @@ static int mshv_vtl_alloc_context(unsigned int cpu) if (!per_cpu->run) return -ENOMEM; =20 - if (mshv_vsm_capabilities.intercept_page_available) - mshv_vtl_configure_reg_page(per_cpu); + if (mshv_vsm_capabilities.intercept_page_available) { + if (hv_vtl_configure_reg_page(per_cpu)) + mshv_has_reg_page =3D true; + } =20 mshv_vtl_synic_enable_regs(cpu); =20 diff --git a/include/asm-generic/mshyperv.h b/include/asm-generic/mshyperv.h index b147a12085e4..b53fcc071596 100644 --- a/include/asm-generic/mshyperv.h +++ b/include/asm-generic/mshyperv.h @@ -383,8 +383,50 @@ static inline int hv_deposit_memory(u64 partition_id, = u64 status) return hv_deposit_memory_node(NUMA_NO_NODE, partition_id, status); } =20 +#if IS_ENABLED(CONFIG_MSHV_ROOT) || IS_ENABLED(CONFIG_MSHV_VTL) +int hv_call_get_vp_registers(u32 vp_index, u64 partition_id, u16 count, + union hv_input_vtl input_vtl, + struct hv_register_assoc *registers); + +int hv_call_set_vp_registers(u32 vp_index, u64 partition_id, u16 count, + union hv_input_vtl input_vtl, + struct hv_register_assoc *registers); +#else +static inline int hv_call_get_vp_registers(u32 vp_index, u64 partition_id, + u16 count, + union hv_input_vtl input_vtl, + struct hv_register_assoc *registers) +{ + return -EOPNOTSUPP; +} + +static inline int hv_call_set_vp_registers(u32 vp_index, u64 partition_id, + u16 count, + union hv_input_vtl input_vtl, + struct hv_register_assoc *registers) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_MSHV_ROOT || CONFIG_MSHV_VTL */ + #define HV_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 + #if IS_ENABLED(CONFIG_HYPERV_VTL_MODE) +struct mshv_vtl_per_cpu { + struct mshv_vtl_run *run; + struct page *reg_page; +}; + +/* SYNIC_OVERLAY_PAGE_MSR - internal, identical to hv_synic_simp */ +union hv_synic_overlay_page_msr { + u64 as_uint64; + struct { + u64 enabled: 1; + u64 reserved: 11; + u64 pfn: 52; + } __packed; +}; + u8 __init get_vtl(void); #else static inline u8 get_vtl(void) { return 0; } --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 746D639479A; Mon, 16 Mar 2026 12:14:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; 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dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="jDcEUB6i" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id 98A1E20B6F01; Mon, 16 Mar 2026 05:13:53 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 98A1E20B6F01 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663240; bh=1tIeJ9SsYHVdstCDU1TnP5bpNkiYnZ9fn1VYje8AQcA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jDcEUB6im4iHNa8UvsB4S4VtwoaL8MA54GDurzLy2wS1TLb6GLd7swVaNI/GDOj3O DgRGqXyFlAmfNAeDLRqe/DAoy5Ya+8ntTJ1+stBVGLZAFrGKlkQUTRptJ2qkiwZjVv 6HcItX5fK4bfExTmAX7cU7AX7sm8X1Uy4UYy1+1s= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 09/11] Drivers: hv: mshv_vtl: Let userspace do VSM configuration Date: Mon, 16 Mar 2026 12:12:39 +0000 Message-ID: <20260316121241.910764-10-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kernel currently sets the VSM configuration register, thereby imposing certain VSM configuration on the userspace (OpenVMM). The userspace (OpenVMM) has the capability to configure this register, and it is already doing it using the generic hypercall interface. The configuration can vary based on the use case or architectures, so let userspace take care of configuring it and remove this logic in the kernel driver. Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- drivers/hv/mshv_vtl_main.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index c79d24317b8e..4c9ae65ad3e8 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -222,30 +222,6 @@ static int mshv_vtl_get_vsm_regs(void) return ret; } =20 -static int mshv_vtl_configure_vsm_partition(struct device *dev) -{ - union hv_register_vsm_partition_config config; - struct hv_register_assoc reg_assoc; - - config.as_uint64 =3D 0; - config.default_vtl_protection_mask =3D HV_MAP_GPA_PERMISSIONS_MASK; - config.enable_vtl_protection =3D 1; - config.zero_memory_on_reset =3D 1; - config.intercept_vp_startup =3D 1; - config.intercept_cpuid_unimplemented =3D 1; - - if (mshv_vsm_capabilities.intercept_page_available) { - dev_dbg(dev, "using intercept page\n"); - config.intercept_page =3D 1; - } - - reg_assoc.name =3D HV_REGISTER_VSM_PARTITION_CONFIG; - reg_assoc.value.reg64 =3D config.as_uint64; - - return hv_call_set_vp_registers(HV_VP_INDEX_SELF, HV_PARTITION_ID_SELF, - 1, input_vtl_zero, ®_assoc); -} - static void mshv_vtl_vmbus_isr(void) { struct hv_per_cpu_context *per_cpu; @@ -1168,11 +1144,6 @@ static int __init mshv_vtl_init(void) ret =3D -ENODEV; goto free_dev; } - if (mshv_vtl_configure_vsm_partition(dev)) { - dev_emerg(dev, "VSM configuration failed !!\n"); - ret =3D -ENODEV; - goto free_dev; - } =20 mshv_vtl_return_call_init(mshv_vsm_page_offsets.vtl_return_offset); ret =3D hv_vtl_setup_synic(); --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 74C253909A0; Mon, 16 Mar 2026 12:14:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663249; cv=none; b=aMreI+stFGOzM5DStZE457E9HPswJ4I/z3vBhWrnlNh8+y51tMe+0oxRmMMIj3J8FSJ3J2s9RVQblyUjQfmwKTkKRUYS7sHxqxZ4SGBuT2bMWmfgwGbm/rRZjgKrgmH08fddUylR2DGVnClmWJErVPf0XJ/C3gzSPnQnjOhOX7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663249; c=relaxed/simple; bh=Aosphk+esZ+v58Q9WvRh97SsPNb//Li8JvZOSif4gXQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lwktJgwUe5UbgLOlcHdsZJ/uektWh1Y4OJxqGpxDbjpC9QT+j2U1eTk0lFu69scBTZ10KdScKjTZm6ePHNq0NIzUDm2Isjhuu2aKWerWQFvWyiMUUgUbklkFptbX77d9oLs0UC4vznebIsaUgNx480Cxw3o5ONnivYcX2IaCZOE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com; spf=pass smtp.mailfrom=linux.microsoft.com; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b=cSQ16MVj; arc=none smtp.client-ip=13.77.154.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.microsoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.microsoft.com header.i=@linux.microsoft.com header.b="cSQ16MVj" Received: from CPC-namja-026ON.redmond.corp.microsoft.com (unknown [4.213.232.19]) by linux.microsoft.com (Postfix) with ESMTPSA id 1219420B6F12; Mon, 16 Mar 2026 05:14:00 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 1219420B6F12 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663247; bh=jB+RemL3Pk8PFFcu2obc8ovkfjIzseACUPlWgi1xPjo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cSQ16MVj4newgvduGvn6HO5LY8y/IM488Ga/wfFvNxsMmRIrMVhJbDA0bFdOGID8j 01S3ewI3UDGQTajSrNTPDhUwZPxE/ErNp/QuudR67eGucLFjbSFhYtwssr5mtWtjFL qarbXKOqrRPQCEJeNtLfBJeb0FSsf0JoDU5lmdHk= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 10/11] Drivers: hv: Add support for arm64 in MSHV_VTL Date: Mon, 16 Mar 2026 12:12:40 +0000 Message-ID: <20260316121241.910764-11-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add necessary support to make MSHV_VTL work for arm64 architecture. * Add stub implementation for mshv_vtl_return_call_init(): not required for arm64 * Remove fpu/legacy.h header inclusion, as this is not required * handle HV_REGISTER_VSM_CODE_PAGE_OFFSETS register: not supported in arm64 * Configure custom percpu_vmbus_handler by using hv_setup_percpu_vmbus_handler() * Handle hugepage functions by config checks Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- arch/arm64/include/asm/mshyperv.h | 2 ++ drivers/hv/mshv_vtl_main.c | 21 ++++++++++++++------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/mshyperv.h b/arch/arm64/include/asm/msh= yperv.h index 36803f0386cc..027a7f062d70 100644 --- a/arch/arm64/include/asm/mshyperv.h +++ b/arch/arm64/include/asm/mshyperv.h @@ -83,6 +83,8 @@ static inline int hv_vtl_get_set_reg(struct hv_register_a= ssoc *regs, bool set, u return 1; } =20 +static inline void mshv_vtl_return_call_init(u64 vtl_return_offset) {} + void mshv_vtl_return_call(struct mshv_vtl_cpu_context *vtl0); bool hv_vtl_configure_reg_page(struct mshv_vtl_per_cpu *per_cpu); #endif diff --git a/drivers/hv/mshv_vtl_main.c b/drivers/hv/mshv_vtl_main.c index 4c9ae65ad3e8..5702fe258500 100644 --- a/drivers/hv/mshv_vtl_main.c +++ b/drivers/hv/mshv_vtl_main.c @@ -23,8 +23,6 @@ #include #include #include - -#include "../../kernel/fpu/legacy.h" #include "mshv.h" #include "mshv_vtl.h" #include "hyperv_vmbus.h" @@ -206,18 +204,21 @@ static void mshv_vtl_synic_enable_regs(unsigned int c= pu) static int mshv_vtl_get_vsm_regs(void) { struct hv_register_assoc registers[2]; - int ret, count =3D 2; + int ret, count =3D 0; =20 - registers[0].name =3D HV_REGISTER_VSM_CODE_PAGE_OFFSETS; - registers[1].name =3D HV_REGISTER_VSM_CAPABILITIES; + registers[count++].name =3D HV_REGISTER_VSM_CAPABILITIES; + /* Code page offset register is not supported on ARM */ + if (IS_ENABLED(CONFIG_X86_64)) + registers[count++].name =3D HV_REGISTER_VSM_CODE_PAGE_OFFSETS; =20 ret =3D hv_call_get_vp_registers(HV_VP_INDEX_SELF, HV_PARTITION_ID_SELF, count, input_vtl_zero, registers); if (ret) return ret; =20 - mshv_vsm_page_offsets.as_uint64 =3D registers[0].value.reg64; - mshv_vsm_capabilities.as_uint64 =3D registers[1].value.reg64; + mshv_vsm_capabilities.as_uint64 =3D registers[0].value.reg64; + if (IS_ENABLED(CONFIG_X86_64)) + mshv_vsm_page_offsets.as_uint64 =3D registers[1].value.reg64; =20 return ret; } @@ -280,10 +281,13 @@ static int hv_vtl_setup_synic(void) =20 /* Use our isr to first filter out packets destined for userspace */ hv_setup_vmbus_handler(mshv_vtl_vmbus_isr); + /* hv_setup_vmbus_handler() is stubbed for ARM64, add per-cpu VMBus handl= ers instead */ + hv_setup_percpu_vmbus_handler(mshv_vtl_vmbus_isr); =20 ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "hyperv/vtl:online", mshv_vtl_alloc_context, NULL); if (ret < 0) { + hv_setup_percpu_vmbus_handler(vmbus_isr); hv_setup_vmbus_handler(vmbus_isr); return ret; } @@ -296,6 +300,7 @@ static int hv_vtl_setup_synic(void) static void hv_vtl_remove_synic(void) { cpuhp_remove_state(mshv_vtl_cpuhp_online); + hv_setup_percpu_vmbus_handler(vmbus_isr); hv_setup_vmbus_handler(vmbus_isr); } =20 @@ -1080,10 +1085,12 @@ static vm_fault_t mshv_vtl_low_huge_fault(struct vm= _fault *vmf, unsigned int ord ret =3D vmf_insert_pfn_pmd(vmf, pfn, vmf->flags & FAULT_FLAG_WRITE); return ret; =20 +#if defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD) case PUD_ORDER: if (can_fault(vmf, PUD_SIZE, &pfn)) ret =3D vmf_insert_pfn_pud(vmf, pfn, vmf->flags & FAULT_FLAG_WRITE); return ret; +#endif =20 default: return VM_FAULT_SIGBUS; --=20 2.43.0 From nobody Tue Apr 7 04:18:29 2026 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 503EA3932C3; Mon, 16 Mar 2026 12:14:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=13.77.154.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773663257; cv=none; b=Q6hr5/LWFlQvwkCvsRlMfEbLQ/ZiXGliLAq5C2nvmFyqK6TujU7P9hSyRqpXyyogEUn9Y8pmXXsb87aWysdj0vJiieh8mskeazkSM8j330wvp3CVWJr5gvTnHl50EffZ4oFv/9B2f8VdHGjX1lj0qymvcoly9RHXGIUO1805qF4= ARC-Message-Signature: i=1; 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Mon, 16 Mar 2026 05:14:08 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com EDB4720B6F1B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1773663255; bh=RkE3+qElIZaIEZKSD/Ld3HbKTw73INK8ayuUxF+uJxQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s9CD2tDnG6tFpkuyB5dr6TborVEmEhSrR6Y8mXyzKLjUKHktvqTTPJaIKQrjL/zc6 oOb2+6CxUKPPPUNQgjiq9fmMtREq1URhAKprDqXBrnsic6rUfo53g99NrAGB5rPrRg mP6kAUCgdZEQxBnaQJvRb7+6G0m2SBMscKd9jixc= From: Naman Jain To: "K . Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Catalin Marinas , Will Deacon , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Arnd Bergmann , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Marc Zyngier , Timothy Hayes , Lorenzo Pieralisi , mrigendrachaubey , Naman Jain , ssengar@linux.microsoft.com, Michael Kelley , linux-hyperv@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 11/11] Drivers: hv: Kconfig: Add ARM64 support for MSHV_VTL Date: Mon, 16 Mar 2026 12:12:41 +0000 Message-ID: <20260316121241.910764-12-namjain@linux.microsoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316121241.910764-1-namjain@linux.microsoft.com> References: <20260316121241.910764-1-namjain@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable ARM64 support in MSHV_VTL Kconfig now that all the necessary support is present. Signed-off-by: Roman Kisel Signed-off-by: Naman Jain Reviewed-by: Roman Kisel --- drivers/hv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hv/Kconfig b/drivers/hv/Kconfig index 7937ac0cbd0f..393cef272590 100644 --- a/drivers/hv/Kconfig +++ b/drivers/hv/Kconfig @@ -87,7 +87,7 @@ config MSHV_ROOT =20 config MSHV_VTL tristate "Microsoft Hyper-V VTL driver" - depends on X86_64 && HYPERV_VTL_MODE + depends on (X86_64 || ARM64) && HYPERV_VTL_MODE depends on HYPERV_VMBUS # Mapping VTL0 memory to a userspace process in VTL2 is supported in Open= HCL. # VTL2 for OpenHCL makes use of Huge Pages to improve performance on VMs, --=20 2.43.0