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Mon, 16 Mar 2026 02:46:32 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Cosmin Ratiu Subject: [PATCH net 1/3] net/mlx5: qos: Restrict RTNL area to avoid a lock cycle Date: Mon, 16 Mar 2026 11:46:01 +0200 Message-ID: <20260316094603.6999-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316094603.6999-1-tariqt@nvidia.com> References: <20260316094603.6999-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06A:EE_|CH3PR12MB8659:EE_ X-MS-Office365-Filtering-Correlation-Id: 6fe7e4a6-f6cb-4520-dde9-08de8340f2d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: rBmGG7rQBMqj+fk3kgK6EWbI5fE+L9L0EOk1q5N+P8a5ozqzJsKobV1V29Z9vuR1ZUAoDOlWwIrFIke+GpxuzLUxbvP5ggtbLs0zu40w9oa0qRVfAUiXaH+jhjSQanD5rE6ltsrwcn8iicsQud6HhioBIrIPLY2YEsJ8krOqhkeeVH/Yt0BDyTV8OBYdLPTsgDAR1XuINGR/7X9lTK7LtUDy+FSWJvxdNzvUfEc7XE4elmtX9T3ZIsjYC/QSKkRvkfWnAuAg6w9sHnT9PJDX6JGVmnXPhUFbUJKV+uqrdi2Eyd1u4NLtk0UyARFJqXuPYgyi9XnTOrDb/RXczXD8SVl/1y/yo4tG/ugcWnVJlcL870jqgxdMB+XZ0ejJ03U2gfPhyaNcAtwhSJyxGAanlqKrGRFt6o9t8mnkKmHVqveKyewAzfh+vXhBgwDwoXInaH9PSF/zq9UwWUrVyQp+WRyCKDIJuIrAkEYOe25HfGdM1M0rGzDmlnUAf4ag4H5oYI2HhKNaH/n4higDPvafzd8n5/l7182+3/rpVz1t5WOrjCXOQZ9Amgrsa5D70BWMAb0C7Y7Ju90DoQb6Zzfm+f4aqYa3BhJP+a6rgFBROkQuR5mJpR1s82FVUMDe0Lm5TZgTePOBSCp/C8+hfpLD1QnqmqinZMSu3GG7/mSSdOsx1x+vP1sicNnyosfDj4v4i5s0o6Niut6dwbbAOMTLrio6A7McNHC7hfTtMp+kBlyWcotlasJqcFHpqDecuTg5LMmu38GNAkz0ouXTdt7dWw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Rka54KdIG7Ws0zZGWs+uGHvNhsI6+d5HyfKAVY4FCN72y83u2ahp21h3IiM4MzqgDGV/psxbd1wk2Ku4p1snkMd6GW1u+M26sC351uomc6OCS72uEv/24WpOOQCP9+SzNUe5OmERNIT2NpLjsEIjjhaKm0f0kKNkR/nbXrvNguEGISEw5FQ2CcfvL3ELViIM4k9YU5OkRAE6DfBdQbia/wIUDoJBCu3Nlo23naMfVJZ6rFPtnLKISKe35d1WvmGtApDw5eMs8m1bU1SpEmEgE373e7qFGsTQSuZq0/0TtoBt2sj3m+W5WVBD1jnBT1HW4VauhQ0JTrXZlxKA0hhZKFsfaDl65MEUNvQmkexSX1dWd7uY2MSMJAbtxoSOH78IB9FZerj9QoeILOmbqY2uTXF+7N2jTdRDFMZmGh3bmY8kXiJFe6eubqnOmaV48wyz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 09:46:50.6085 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6fe7e4a6-f6cb-4520-dde9-08de8340f2d0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8659 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu A lock dependency cycle exists where: 1. mlx5_ib_roce_init -> mlx5_core_uplink_netdev_event_replay -> mlx5_blocking_notifier_call_chain (takes notifier_rwsem) -> mlx5e_mdev_notifier_event -> mlx5_netdev_notifier_register -> register_netdevice_notifier_dev_net (takes rtnl) =3D> notifier_rwsem -> rtnl 2. mlx5e_probe -> _mlx5e_probe -> mlx5_core_uplink_netdev_set (takes uplink_netdev_lock) -> mlx5_blocking_notifier_call_chain (takes notifier_rwsem) =3D> uplink_netdev_lock -> notifier_rwsem 3: devlink_nl_rate_set_doit -> devlink_nl_rate_set -> mlx5_esw_devlink_rate_leaf_tx_max_set -> esw_qos_devlink_rate_to_mbps -> mlx5_esw_qos_max_link_speed_get (takes rtnl) -> mlx5_esw_qos_lag_link_speed_get_locked -> mlx5_uplink_netdev_get (takes uplink_netdev_lock) =3D> rtnl -> uplink_netdev_lock =3D> BOOM! (lock cycle) Fix that by restricting the rtnl-protected section to just the necessary part, the call to netdev_master_upper_dev_get and speed querying, so that the last lock dependency is avoided and the cycle doesn't close. This is safe because mlx5_uplink_netdev_get uses netdev_hold to keep the uplink netdev alive while its master device is queried. Use this opportunity to rename the ambiguously-named "hold_rtnl_lock" argument to "take_rtnl" and remove the "_locked" suffix from mlx5_esw_qos_lag_link_speed_get_locked. Fixes: 6b4be64fd9fe ("net/mlx5e: Harden uplink netdev access against device= unbind") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 23 ++++++++----------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 26178d0bac92..faccc60fc93a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -1489,24 +1489,24 @@ static int esw_qos_node_enable_tc_arbitration(struc= t mlx5_esw_sched_node *node, return err; } =20 -static u32 mlx5_esw_qos_lag_link_speed_get_locked(struct mlx5_core_dev *md= ev) +static u32 mlx5_esw_qos_lag_link_speed_get(struct mlx5_core_dev *mdev, + bool take_rtnl) { struct ethtool_link_ksettings lksettings; struct net_device *slave, *master; u32 speed =3D SPEED_UNKNOWN; =20 - /* Lock ensures a stable reference to master and slave netdevice - * while port speed of master is queried. - */ - ASSERT_RTNL(); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Jianbo Liu , Leon Romanovsky Subject: [PATCH net 2/3] net/mlx5e: Prevent concurrent access to IPSec ASO context Date: Mon, 16 Mar 2026 11:46:02 +0200 Message-ID: <20260316094603.6999-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316094603.6999-1-tariqt@nvidia.com> References: <20260316094603.6999-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06A:EE_|BN5PR12MB9512:EE_ X-MS-Office365-Filtering-Correlation-Id: 7869108c-9001-4b80-90a1-08de8340f4af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: awBM3ljdfegmskZWzjGV+aIUZx+GkeFnquzA3Unz21KFif2tNsHCpaclsXbCi2dEuT8BppoqIsuPgzKXfVYiDAJTPCGC1q+3u5NaTTtIMiMBUXnI1YIwsph74suJJKRPTYR+a828MnBt5pXQuvOF9a7Nk/eiFkJ5lluvtqpgIVh2MlzK7vzb/jjk6ElPz9ePMq32Gxr3VL7HvEGyjpgJas7MNvFMEPma9353wwGIg9uEvQOFIelECQJ1uW1bqFQWQKVk8fWIAR45QF3cmBJ229ICke/Lhff5mQ/9bB1yXl/W6rR8RrkidBLyMkN7Tx/lqJgh8/mL3/0GKN6xS5k/eFbr8WSbwfV4LeIt3KZEp6O5zAij+W6T1De2+q4bWbRZCOauCdeTFL+0EF1fJfBvsHJVB6f+hG6UKxEoJ+ZHBQk+Jnd8tY3BhErCItJUZoHlU70JB1ROSTsdk1ouZyvUDU42kkPq1qsVLEXyeV/Zi7QH/mpAqX0TxaJsWsJkQL2CabS48WB4JeAiX7fF51mD8CJOY6vVQrTrsmt/K9Dqt5CJGC95PSEPvEily13tY5AB5Qg/hiRD6nesqcGlRbKYyjRlXh4mL3/wWExEFNF0NdHAP8bS4bKiTq252mt8IyIv+atyL45ivFbNOLfJojKpjztFm2zfthSsuNSX/eGyYOM2Bz2zDevuFmLaCWNNRZi01OKFaGI+qcMqLv/xvveNsFOO57oTKpEw3z4tlDVUUxSGSQa8EIMWvGJw/jkECX36+77M5wDCjQsI3TRioG9WnA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: J7xR12jxNXbjRmX4AWEg1HFyyr2ajkAncQ6EPxzTUX50g6VS05P0WRCrKBn0fCRIxMTs6dS993Ky51la4uIkIMbVx580nLgA1aH1Uq9ClKTXawiOROoaj2QXdvX+X748hhiMWEWgHVKyUpYbATIggI1+KOLe0Q7SyPJj85dE1JRZiAMu9w5kWbmwur953BRaTm6ZrkDojR3WxsdqNE+TDhJ+Gij6Q60mxP4VkUxwU+nZRUvOzWi2HEL7FDpHxFuIqdrEl5iobeZvnsV42+Yzg+Zspa2ivyvmRorf+NouBGKBqDf3kexYEyQUwG9Eb6zsmldXNMYlK/hXmA04yPjO7fhEw8n22rhum7qwFmey3JDdCOYnZMvgsGOiku08K1qYEDd0BZUYf9YjFwtco5oL0xDQ3OFEUVtmGpim+mvFh2WElpYb3DfO0DinU5xOiv7T X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 09:46:53.7071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7869108c-9001-4b80-90a1-08de8340f4af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9512 Content-Type: text/plain; charset="utf-8" From: Jianbo Liu The query or updating IPSec offload object is through Access ASO WQE. The driver uses a single mlx5e_ipsec_aso struct for each PF, which contains a shared DMA-mapped context for all ASO operations. A race condition exists because the ASO spinlock is released before the hardware has finished processing WQE. If a second operation is initiated immediately after, it overwrites the shared context in the DMA area. When the first operation's completion is processed later, it reads this corrupted context, leading to unexpected behavior and incorrect results. This commit fixes the race by introducing a private context within each IPSec offload object. The shared ASO context is now copied to this private context while the ASO spinlock is held. Subsequent processing uses this saved, per-object context, ensuring its integrity is maintained. Fixes: 1ed78fc03307 ("net/mlx5e: Update IPsec soft and hard limits") Signed-off-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.h | 1 + .../mellanox/mlx5/core/en_accel/ipsec_offload.c | 17 ++++++++--------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/dri= vers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index f8eaaf37963b..abcbd38db9db 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -287,6 +287,7 @@ struct mlx5e_ipsec_sa_entry { struct mlx5e_ipsec_dwork *dwork; struct mlx5e_ipsec_limits limits; u32 rx_mapped_id; + u8 ctx[MLX5_ST_SZ_BYTES(ipsec_aso)]; }; =20 struct mlx5_accel_pol_xfrm_attrs { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload= .c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 33344e00719b..71222f7247f1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -370,20 +370,18 @@ static void mlx5e_ipsec_aso_update_soft(struct mlx5e_= ipsec_sa_entry *sa_entry, static void mlx5e_ipsec_handle_limits(struct mlx5e_ipsec_sa_entry *sa_entr= y) { struct mlx5_accel_esp_xfrm_attrs *attrs =3D &sa_entry->attrs; - struct mlx5e_ipsec *ipsec =3D sa_entry->ipsec; - struct mlx5e_ipsec_aso *aso =3D ipsec->aso; bool soft_arm, hard_arm; u64 hard_cnt; =20 lockdep_assert_held(&sa_entry->x->lock); =20 - soft_arm =3D !MLX5_GET(ipsec_aso, aso->ctx, soft_lft_arm); - hard_arm =3D !MLX5_GET(ipsec_aso, aso->ctx, hard_lft_arm); + soft_arm =3D !MLX5_GET(ipsec_aso, sa_entry->ctx, soft_lft_arm); + hard_arm =3D !MLX5_GET(ipsec_aso, sa_entry->ctx, hard_lft_arm); if (!soft_arm && !hard_arm) /* It is not lifetime event */ return; =20 - hard_cnt =3D MLX5_GET(ipsec_aso, aso->ctx, remove_flow_pkt_cnt); + hard_cnt =3D MLX5_GET(ipsec_aso, sa_entry->ctx, remove_flow_pkt_cnt); if (!hard_cnt || hard_arm) { /* It is possible to see packet counter equal to zero without * hard limit event armed. Such situation can be if packet @@ -454,10 +452,8 @@ static void mlx5e_ipsec_handle_event(struct work_struc= t *_work) container_of(_work, struct mlx5e_ipsec_work, work); struct mlx5e_ipsec_sa_entry *sa_entry =3D work->data; struct mlx5_accel_esp_xfrm_attrs *attrs; - struct mlx5e_ipsec_aso *aso; int ret; =20 - aso =3D sa_entry->ipsec->aso; attrs =3D &sa_entry->attrs; =20 spin_lock_bh(&sa_entry->x->lock); @@ -466,8 +462,9 @@ static void mlx5e_ipsec_handle_event(struct work_struct= *_work) goto unlock; =20 if (attrs->replay_esn.trigger && - !MLX5_GET(ipsec_aso, aso->ctx, esn_event_arm)) { - u32 mode_param =3D MLX5_GET(ipsec_aso, aso->ctx, mode_parameter); + !MLX5_GET(ipsec_aso, sa_entry->ctx, esn_event_arm)) { + u32 mode_param =3D MLX5_GET(ipsec_aso, sa_entry->ctx, + mode_parameter); =20 mlx5e_ipsec_update_esn_state(sa_entry, mode_param); } @@ -629,6 +626,8 @@ int mlx5e_ipsec_aso_query(struct mlx5e_ipsec_sa_entry *= sa_entry, /* We are in atomic context */ udelay(10); } while (ret && time_is_after_jiffies(expires)); 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Mon, 16 Mar 2026 02:46:44 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 16 Mar 2026 02:46:41 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Dragos Tatulea , Jianbo Liu , Leon Romanovsky Subject: [PATCH net 3/3] net/mlx5e: Fix race condition during IPSec ESN update Date: Mon, 16 Mar 2026 11:46:03 +0200 Message-ID: <20260316094603.6999-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260316094603.6999-1-tariqt@nvidia.com> References: <20260316094603.6999-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|BY5PR12MB4242:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f189443-d8e6-4e4e-887f-08de8340f4bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: bJv+PZio7SrsXExXn7CfVLK2HFJu0dITvBStS3trMeWYGjEcddajgItGLj4sGSybV3oZziYGujEBXW6BTM3/hqDV2XsIR2lryosZCvd3081Ca8qXVEm2k6DZ5L5Eby4bc+l6IPcF31lFtPHaocmMoKKfS3NJNAv7bqA+F/4QZBOfNN8otm9mPOtuMD6iXt+PyglWys05xJuLfmJCbyNK4F+ME+wmXBhu22iL/qO1prlzA3U0/1bD13KWtILiFbiejauNa/bSD2ArLrp22XM+tsUyMQKMLwWUyhaF17wKuwYOdORlkXDsyRheKf9Iw9IExAqtwUOPT/wDopDDiDqcLzwl0piOQ/7x5R9iYTQEpeq3ITlN1CSLPvWw/vV5gZ/oEL/CMgx70Qz4q9+HFDGUeElxK9AgyZrfn2ltq/xvaKASwfNdqCP275eLaQa4ShkXnJJIvykNsEUytGZa8FXnyF895JFOHmvZrUFQdJh/0CtXhly9JFqci3RmlD9133mLYuiDRzIt4ZCtnUJCg/ozLtzNB3536dApLvTu7Ntu/cCYahYVZbcKu93GJ2UdnjReo41QRGAr8b3DQrIy9++XfS5qbfcpkkIbDUQMUxyicPw75vkj84QCOT04f2kaTq6Ec2ssTTENT2DinRF2lof5d4HYOs1L/6qstq4flB8FT87Nlzq12jFlEiwgJK4uEuR49hjV1bxj50fB+C98+uCxa5dGxBZSPeoH3ZP+GgRGElAjyOvH45j2EWwvfieOXwhVlXSC6u6NXkec31mqtlpeCQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Mgo3750cIQCNwkdahuzCIr8LEg+8VTHABB2VDfTljqkQiqxhlMOLzk0cGgTGstfrwouCk5MsW8+T/ZS915rueeaxgUK3vCi7GE+cuvrCbvlO7OkhG9PCl4qc3yAnntB0Dxv3EOk5a1cq4DnUusyU8DkKajY3ijKJL36zjQVCRnm7OzzYE/FMQJ9yXes9d1GwuR00UZg7ld+o2GWvdNPsRjuElRfZGmmE8f6qBU9DrjNdYt47cfEZQ+1tGZsxa79sAP0O9Lw06qgCe9HDOl+rFiHKoKF4KgHgamn2oahuO+DI7cSflwl2MCpMCj56pJtQlnJeoaRYv6veaDY1RLjL77LxHzyhG6+/Vb6v8JGel1EqGS7O0oF3UAs/pNHZcaoIrMeI9D06XD1BB5xAJ0dHpVNLALEcC08ENegPYZhDH5iNbtwvOcHIv7BwLWlR8ZB4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 09:46:53.8825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f189443-d8e6-4e4e-887f-08de8340f4bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4242 Content-Type: text/plain; charset="utf-8" From: Jianbo Liu In IPSec full offload mode, the device reports an ESN (Extended Sequence Number) wrap event to the driver. The driver validates this event by querying the IPSec ASO and checking that the esn_event_arm field is 0x0, which indicates an event has occurred. After handling the event, the driver must re-arm the context by setting esn_event_arm back to 0x1. A race condition exists in this handling path. After validating the event, the driver calls mlx5_accel_esp_modify_xfrm() to update the kernel's xfrm state. This function temporarily releases and re-acquires the xfrm state lock. So, need to acknowledge the event first by setting esn_event_arm to 0x1. This prevents the driver from reprocessing the same ESN update if the hardware sends events for other reason. Since the next ESN update only occurs after nearly 2^31 packets are received, there's no risk of missing an update, as it will happen long after this handling has finished. Processing the event twice causes the ESN high-order bits (esn_msb) to be incremented incorrectly. The driver then programs the hardware with this invalid ESN state, which leads to anti-replay failures and a complete halt of IPSec traffic. Fix this by re-arming the ESN event immediately after it is validated, before calling mlx5_accel_esp_modify_xfrm(). This ensures that any spurious, duplicate events are correctly ignored, closing the race window. Fixes: fef06678931f ("net/mlx5e: Fix ESN update kernel panic") Signed-off-by: Jianbo Liu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan --- .../mlx5/core/en_accel/ipsec_offload.c | 33 ++++++++----------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload= .c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 71222f7247f1..05faad5083d9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -310,10 +310,11 @@ static void mlx5e_ipsec_aso_update(struct mlx5e_ipsec= _sa_entry *sa_entry, mlx5e_ipsec_aso_query(sa_entry, data); } =20 -static void mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_e= ntry, - u32 mode_param) +static void +mlx5e_ipsec_update_esn_state(struct mlx5e_ipsec_sa_entry *sa_entry, + u32 mode_param, + struct mlx5_accel_esp_xfrm_attrs *attrs) { - struct mlx5_accel_esp_xfrm_attrs attrs =3D {}; struct mlx5_wqe_aso_ctrl_seg data =3D {}; =20 if (mode_param < MLX5E_IPSEC_ESN_SCOPE_MID) { @@ -323,18 +324,7 @@ static void mlx5e_ipsec_update_esn_state(struct mlx5e_= ipsec_sa_entry *sa_entry, sa_entry->esn_state.overlap =3D 1; } =20 - mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &attrs); - - /* It is safe to execute the modify below unlocked since the only flows - * that could affect this HW object, are create, destroy and this work. - * - * Creation flow can't co-exist with this modify work, the destruction - * flow would cancel this work, and this work is a single entity that - * can't conflict with it self. - */ - spin_unlock_bh(&sa_entry->x->lock); - mlx5_accel_esp_modify_xfrm(sa_entry, &attrs); - spin_lock_bh(&sa_entry->x->lock); + mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, attrs); =20 data.data_offset_condition_operand =3D MLX5_IPSEC_ASO_REMOVE_FLOW_PKT_CNT_OFFSET; @@ -451,7 +441,9 @@ static void mlx5e_ipsec_handle_event(struct work_struct= *_work) struct mlx5e_ipsec_work *work =3D container_of(_work, struct mlx5e_ipsec_work, work); struct mlx5e_ipsec_sa_entry *sa_entry =3D work->data; + struct mlx5_accel_esp_xfrm_attrs tmp =3D {}; struct mlx5_accel_esp_xfrm_attrs *attrs; + bool need_modify =3D false; int ret; =20 attrs =3D &sa_entry->attrs; @@ -461,19 +453,22 @@ static void mlx5e_ipsec_handle_event(struct work_stru= ct *_work) if (ret) goto unlock; =20 + if (attrs->lft.soft_packet_limit !=3D XFRM_INF) + mlx5e_ipsec_handle_limits(sa_entry); + if (attrs->replay_esn.trigger && !MLX5_GET(ipsec_aso, sa_entry->ctx, esn_event_arm)) { u32 mode_param =3D MLX5_GET(ipsec_aso, sa_entry->ctx, mode_parameter); =20 - mlx5e_ipsec_update_esn_state(sa_entry, mode_param); + mlx5e_ipsec_update_esn_state(sa_entry, mode_param, &tmp); + need_modify =3D true; } =20 - if (attrs->lft.soft_packet_limit !=3D XFRM_INF) - mlx5e_ipsec_handle_limits(sa_entry); - unlock: spin_unlock_bh(&sa_entry->x->lock); + if (need_modify) + mlx5_accel_esp_modify_xfrm(sa_entry, &tmp); kfree(work); } =20 --=20 2.44.0