From nobody Tue Apr 7 06:30:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3350234E769 for ; Mon, 16 Mar 2026 07:19:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773645569; cv=none; b=HxltK6YZXM6E9nX03ON2YWmFn1AdjmI2Pi52F3lYyql4H0RXhJnw1RNx/rhbFNIWvNj2i8Rd2DP17Cy4GXMC+B381AjmhpXD/OvOAaid4XncXcOfVxAQ8d8KiYkXrWH5yjeJgCms8SO4Q+zLEAdz8Z7KG5g9uDHX6o1XC08aybU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773645569; c=relaxed/simple; bh=jXEehlLu4eHg/cJ7PweERZHLCJv+lrqKpY3LFWQ8Gw8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RdKlzrL4EqSPkArdUifqqBZqOji35+Cvt0QF/737HZ94Rs8B05mssNol63W9f+vvAmLIrF6CurOqA9ZManpNoh3wVVChAIhPrd2h4zE1HShWK+cNZWJKJbEPKdFN4PUJyop50aCvM7xAiY8otWMfUJqIhwLb9e6k6JXjqf9Px6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ipFBsYEv; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ipFBsYEv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773645568; x=1805181568; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jXEehlLu4eHg/cJ7PweERZHLCJv+lrqKpY3LFWQ8Gw8=; b=ipFBsYEvZqOjLMy4JIEkZbb7ukNtbzzc76E8wL/FKsSBvQi2CTZTF6yi ReUTKZV6Hj8jWHXOR7WG1JRsc3NDlY3dj1gTF8/GqEyTU/IyG+zOtkbzB rLCWf2vgC5HwLH1mPVUuSGck7wczdURYqPvRCTZoXv3WsGwpk1rIvT4m+ qoVIvk8cwpe83qy1bg79lwzuIKbhSY7I06EK7yZEJaeK7kMX9mVUvZ1zJ KRpia38FwM99supafY6L4/PpNokZc6SP6SiSasEiokz778DQy430OQLaX zJa1owgPEfKV9MYb0GgatjmngE/v+3GdeMrY53hNCqkgy0DYgXSh0CHGt g==; X-CSE-ConnectionGUID: wHnCS3ofQPe4XR72FoD6gA== X-CSE-MsgGUID: /h8QoN4GS9+USUiIaRTOEQ== X-IronPort-AV: E=McAfee;i="6800,10657,11730"; a="92038595" X-IronPort-AV: E=Sophos;i="6.23,123,1770624000"; d="scan'208";a="92038595" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 00:19:27 -0700 X-CSE-ConnectionGUID: cDjNQQh4Q4+3JKTP00aB8A== X-CSE-MsgGUID: V3HV3I1NSzyLLpM7AfRRXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,123,1770624000"; d="scan'208";a="226496923" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa005.fm.intel.com with ESMTP; 16 Mar 2026 00:19:26 -0700 From: Lu Baolu To: Joerg Roedel Cc: Guanghui Feng , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] iommu/vt-d: Only handle IOPF for SVA when PRI is supported Date: Mon, 16 Mar 2026 15:16:40 +0800 Message-ID: <20260316071640.347227-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316071640.347227-1-baolu.lu@linux.intel.com> References: <20260316071640.347227-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In intel_svm_set_dev_pasid(), the driver unconditionally manages the IOPF handling during a domain transition. However, commit a86fb7717320 ("iommu/vt-d: Allow SVA with device-specific IOPF") introduced support for SVA on devices that handle page faults internally without utilizing the PCI PRI. On such devices, the IOMMU-side IOPF infrastructure is not required. Calling iopf_for_domain_replace() on these devices is incorrect and can lead to unexpected failures during PASID attachment or unwinding. Add a check for info->pri_supported to ensure that the IOPF queue logic is only invoked for devices that actually rely on the IOMMU's PRI-based fault handling. Fixes: 17fce9d2336d ("iommu/vt-d: Put iopf enablement in domain attach path= ") Cc: stable@vger.kernel.org Suggested-by: Kevin Tian Reviewed-by: Kevin Tian Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20260310075520.295104-1-baolu.lu@linux.inte= l.com --- drivers/iommu/intel/svm.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index fea10acd4f02..57cd1db7207a 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -164,9 +164,12 @@ static int intel_svm_set_dev_pasid(struct iommu_domain= *domain, if (IS_ERR(dev_pasid)) return PTR_ERR(dev_pasid); =20 - ret =3D iopf_for_domain_replace(domain, old, dev); - if (ret) - goto out_remove_dev_pasid; + /* SVA with non-IOMMU/PRI IOPF handling is allowed. */ + if (info->pri_supported) { + ret =3D iopf_for_domain_replace(domain, old, dev); + if (ret) + goto out_remove_dev_pasid; + } =20 /* Setup the pasid table: */ sflags =3D cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0; @@ -181,7 +184,8 @@ static int intel_svm_set_dev_pasid(struct iommu_domain = *domain, =20 return 0; out_unwind_iopf: - iopf_for_domain_replace(old, domain, dev); + if (info->pri_supported) + iopf_for_domain_replace(old, domain, dev); out_remove_dev_pasid: domain_remove_dev_pasid(domain, dev, pasid); return ret; --=20 2.43.0