From nobody Tue Apr 7 06:30:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 077FC34BA57 for ; Mon, 16 Mar 2026 07:19:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773645568; cv=none; b=DeBhTiPrzN1D/P6jqbdX91XF4mqFennMpS4yJ8Xu82fT9G6gcbbDRPe71Yl80lj93ldj+eMtSwZ2bbpoDnSlDKcQINkhZEJfwcSy03fK+bWXCTenl7YS75qgmbr8I+G3bjiC0pJfG8bARB5y6vC1p5MgR7MBZzw/bu59krwSBmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773645568; c=relaxed/simple; bh=KcrkEcAHRJGoEZcd0jSIO3ktYh4GA0Y9wKxIbHTPAGE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RYBTfZCqbaudsO9zyREVJrihbPRVmTszPy7F6mbJ/7jP8WgV7G6Iv8FDN3GpaVPryBKUGSm+yTO4+r+WjqRAnMUyUz0K9o1zSjeeSkDj70IK4eXShqyHb6tibBkCYaTtLYKHQUM/IDKPeG7W7FHJNfJJ7kb7UTPsA5vCwLg/AR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EorgcUb3; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EorgcUb3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773645567; x=1805181567; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KcrkEcAHRJGoEZcd0jSIO3ktYh4GA0Y9wKxIbHTPAGE=; b=EorgcUb3AcKgRJ9SMlwwS5flqYfolDvSlEqTSsadM3E4jlprA5p+3hD2 IgjiEeouifrK6xx//pFuQaqDO1stQZaMe9/Oj+px0UEHMUYl/JHe4rbQm oASXByNRjzselvJRuxxeNvjA3YqUz52MH9EL+MqsQ5iQus3ds0JH0C7er n45yGLZAo4A+KmRu9aHZIzmX+BUeTF8I09SD7kM0CgYoKYWkckUaEVngK 7z30fOLUtzDib5hGTIi7R8kTF4neyYzcmJZUQOdubGe2SkA76Kuk6UGqS 39RyAMJ+tNBkjtu5Z3qwcQGYjAvqFczHzxw+yRtxVHTygJYK2Mq5AZ4Tb g==; X-CSE-ConnectionGUID: DpcMtD5KTfSAVA60t1SdQQ== X-CSE-MsgGUID: 1dwWG6HbTTqC1FMLmCyPBw== X-IronPort-AV: E=McAfee;i="6800,10657,11730"; a="92038581" X-IronPort-AV: E=Sophos;i="6.23,123,1770624000"; d="scan'208";a="92038581" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 00:19:26 -0700 X-CSE-ConnectionGUID: Agf/ehajRI+OzkAxDs6cqw== X-CSE-MsgGUID: SfKe6tiyTECkMkP8ZrF1sw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,123,1770624000"; d="scan'208";a="226496920" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa005.fm.intel.com with ESMTP; 16 Mar 2026 00:19:24 -0700 From: Lu Baolu To: Joerg Roedel Cc: Guanghui Feng , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] iommu/vt-d: Fix intel iommu iotlb sync hardlockup and retry Date: Mon, 16 Mar 2026 15:16:39 +0800 Message-ID: <20260316071640.347227-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260316071640.347227-1-baolu.lu@linux.intel.com> References: <20260316071640.347227-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Guanghui Feng During the qi_check_fault process after an IOMMU ITE event, requests at odd-numbered positions in the queue are set to QI_ABORT, only satisfying single-request submissions. However, qi_submit_sync now supports multiple simultaneous submissions, and can't guarantee that the wait_desc will be at an odd-numbered position. Therefore, if an item times out, IOMMU can't re-initiate the request, resulting in an infinite polling wait. This modifies the process by setting the status of all requests already fetched by IOMMU and recorded as QI_IN_USE status (including wait_desc requests) to QI_ABORT, thus enabling multiple requests to be resubmitted. Fixes: 8a1d82462540 ("iommu/vt-d: Multiple descriptors per qi_submit_sync()= ") Cc: stable@vger.kernel.org Signed-off-by: Guanghui Feng Tested-by: Shuai Xue Reviewed-by: Shuai Xue Reviewed-by: Samiullah Khawaja Link: https://lore.kernel.org/r/20260306101516.3885775-1-guanghuifeng@linux= .alibaba.com Signed-off-by: Lu Baolu --- drivers/iommu/intel/dmar.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index d68c06025cac..69222dbd2af0 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1314,7 +1314,6 @@ static int qi_check_fault(struct intel_iommu *iommu, = int index, int wait_index) if (fault & DMA_FSTS_ITE) { head =3D readl(iommu->reg + DMAR_IQH_REG); head =3D ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; - head |=3D 1; tail =3D readl(iommu->reg + DMAR_IQT_REG); tail =3D ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; =20 @@ -1331,7 +1330,7 @@ static int qi_check_fault(struct intel_iommu *iommu, = int index, int wait_index) do { if (qi->desc_status[head] =3D=3D QI_IN_USE) qi->desc_status[head] =3D QI_ABORT; - head =3D (head - 2 + QI_LENGTH) % QI_LENGTH; + head =3D (head - 1 + QI_LENGTH) % QI_LENGTH; } while (head !=3D tail); =20 /* --=20 2.43.0