From nobody Tue Apr 7 04:41:54 2026 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38AEC349B1F for ; Mon, 16 Mar 2026 07:05:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644755; cv=none; b=rvsjKS+VFjtK1MgEtRWxTEKrfjK+iekGkbHjXgzAQmHttsRudBWxR36a07jZ7dL/5Uw9JMZ3UB1KXelY+ZnREU1W2FmeaUi/19OtM3wv61L97+4GTtmthVtWjRf9GCx7cSLqXntogbBmrHr19wbTl01FHDebjCClnPKzMUcbGVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644755; c=relaxed/simple; bh=iKOTiWuxtHnqgEUoB0jQIio7TepUaLlC/w9x0+mrdqc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZbGnjQwQusKpf7uMC7hhLtBUByqaI3Ct3Fnp52QNDJVcDiF3hmpETT6PB/xX79FHzP2VIncl3ducapq8e2zwiBArdqZ4zjODPvcZVNNkV3/03Qg7DEfPpx2WYL0MlMXO4kTcQiZWaX20RjX6ARkWWysd6iL5HmiwBgapZpph06w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=ZZ6lPJqc; arc=none smtp.client-ip=185.136.64.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="ZZ6lPJqc" Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 2026031607054178dbb5c584000207d3 for ; Mon, 16 Mar 2026 08:05:41 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=iMmUMDZrYnEz/CbNgCyWMh1qW53DcWwSxTsAKK1B7Rc=; b=ZZ6lPJqcW02dDWMMEConDNy30m9XX+2yRbXm/FA6paPKFtJuLlcUE2yknRPk50UXSgWbzt PSsEFLpLv4Ke8YS1zlKloV1KhGtlGrr8q9ruOrw9vbeTR5JhiRtNE5I/+MPQTgiO+HBiKlkf 1U6N8ohxdSLCp51tWs5WHoFdtqL2mCsKuFt/0n82kfP4f8vs6pReiMnsnc5w4HYQ95Og2Sj4 vqB9gKmq9SYOlEqsiBgu86D/rPO2PvTkYaDmLqzFlkSDHfH6KBxibyBaXhXNsVmWPphxkHrL iw8LilA8j0Y575oyve0V9/7RNOeLTjS/m4KoavWolrwLnE3ZUwPvzbTg==; From: "A. Sverdlin" To: linux-arm-kernel@lists.infradead.org Cc: Alexander Sverdlin , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Santosh Shilimkar , Andrew Davis , Jayesh Choudhary , Siddharth Vadapalli , Abraham I , Roger Quadros , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: mfd: syscon: add binding for TI K3 platforms reset registers Date: Mon, 16 Mar 2026 08:04:23 +0100 Message-ID: <20260316070429.1545707-2-alexander.sverdlin@siemens.com> In-Reply-To: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> References: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add DT binding for Texas Instruments K3 Multicore SoC platforms reset registers present on AM64x and newer members of the K3 family and consist of the RST_CTRL, RST_STAT, RST_SRC and RST_MAGIC_WORD. The planned usage is to provide reset reason information. Signed-off-by: Alexander Sverdlin --- Changelog: v2: amended mfd/syscon.yaml instead of separate reset/ti,am64-rst.yaml Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + .../bindings/soc/ti/ti,j721e-system-controller.yaml | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index e57add2bacd30..564fcb153a688 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -240,6 +240,7 @@ properties: - ti,am62-usb-phy-ctrl - ti,am625-dss-oldi-io-ctrl - ti,am62p-cpsw-mac-efuse + - ti,am64-rst - ti,am654-dss-oldi-io-ctrl - ti,j784s4-acspcie-proxy-ctrl - ti,j784s4-pcie-ctrl diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-contr= oller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-contr= oller.yaml index f3bd0be3b279f..b8063548f50ad 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.y= aml +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.y= aml @@ -86,6 +86,12 @@ patternProperties: description: This is the DSS OLDI CTRL region. =20 + "^rst@[0-9a-f]+$": + type: object + $ref: /schemas/mfd/syscon.yaml# + description: + The node corresponding to SoC reset registers block. + required: - compatible - reg @@ -133,5 +139,10 @@ examples: compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; reg =3D <0x4070 0x4>; }; + + rst@18170 { + compatible =3D "ti,am64-rst"; + reg =3D <0x18170 0x10>; + }; }; ... --=20 2.52.0 From nobody Tue Apr 7 04:41:54 2026 Received: from mta-64-225.siemens.flowmailer.net (mta-64-225.siemens.flowmailer.net [185.136.64.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8577279324 for ; Mon, 16 Mar 2026 07:05:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644754; cv=none; b=qoVPS2bNz83l0bc9jOAtKVtRKkdXMeZ4ee7S04vjUW65J5YOBMEKfGZ6Xuq99YFMhxqHZ32wlGU9pqksnWHbbwyaRZM82FOyefKvdB48zHka5bXQr3OKPR9lHf67NYF1OVsOqGjiYZwXPKxHzXPkf9QeqNSwEkC5kNekBwAUBf8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644754; c=relaxed/simple; bh=mU3EnCLp/bFBNlT0RunECJqGrJPRXHTVr6sTpYFK+Hg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jDS56iIF2mi7BKJHelJoW/9s1xkkwgwIoPtNSExdEobKOVrhfZQGY7eb+XmlOl7FOlUeY4QaCxkwK24ypPryFd+hNwOdrhBsaGHMGm7yscd9Y3w/rmBT852HhRwlgTXQQu6QuzsIM7Lv0C9i3tzQcFSZeJSm3Fa9BJ3aujxXecQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=Em3apcim; arc=none smtp.client-ip=185.136.64.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="Em3apcim" Received: by mta-64-225.siemens.flowmailer.net with ESMTPSA id 20260316070541eb21c2976800020733 for ; Mon, 16 Mar 2026 08:05:42 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=nCp2IUyZSG3Ta11plRL9Oe3OMExs/bvEcTbIRdbhTkU=; b=Em3apcim3nacc0cVwHG+50ghzpRjqkyScqAVHKOk86YY7Hss06CSOHMabwFWagDL1snWns DlKDyEtoKwKJyWT1kB8ojv2kT7rcMw327pJflYDVMTEBSGuUGgBTBj5nvSdJCVwmj3HEpA6v RCa2VobW1ob4KP8GJGF2V8P4QTQxtycpy54p6EtXrf9zsAqWUKT3pZSVYzzHOMrHvTVgRYZ7 TT6OLjx4svGPRomFz/OmLExK6yclk/xM+fJoloqbue0vgUO/zrxZg0CVn0HbXls6+Qah2Ilr hE7fCI5JtfnQgfzz7tnBCxb4v3x04tDtYq46Ic0Bg+JwRo2oo5G+Nlog==; From: "A. Sverdlin" To: linux-arm-kernel@lists.infradead.org Cc: Alexander Sverdlin , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Santosh Shilimkar , Andrew Davis , Jayesh Choudhary , Siddharth Vadapalli , Abraham I , Roger Quadros , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] arm64: dts: ti: k3-*: Add am64x and newer reset registers Date: Mon, 16 Mar 2026 08:04:24 +0100 Message-ID: <20260316070429.1545707-3-alexander.sverdlin@siemens.com> In-Reply-To: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> References: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add the reset registers present on AM64x and newer SoCs carrying reset cause information. Signed-off-by: Alexander Sverdlin --- Changelog: v2: no changes arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 75aed3a88284d..954130e8f37ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -41,6 +41,11 @@ usb1_phy_ctrl: syscon@4018 { compatible =3D "ti,am62-usb-phy-ctrl", "syscon"; reg =3D <0x4018 0x4>; }; + + rst@18170 { + compatible =3D "ti,am64-rst"; + reg =3D <0x18170 0x10>; + }; }; =20 target-module@2b300050 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index 23877dadc98dc..7c94e6e16c069 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -39,6 +39,11 @@ usb1_phy_ctrl: syscon@4018 { compatible =3D "ti,am62-usb-phy-ctrl", "syscon"; reg =3D <0x4018 0x4>; }; + + rst@18170 { + compatible =3D "ti,am64-rst"; + reg =3D <0x18170 0x10>; + }; }; =20 target-module@2b300050 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 1b1d3970888b8..acbc7243cb16a 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -74,6 +74,11 @@ epwm_tbclk: clock-controller@4130 { reg =3D <0x4130 0x4>; #clock-cells =3D <1>; }; + + rst@18170 { + compatible =3D "ti,am64-rst"; + reg =3D <0x18170 0x10>; + }; }; =20 gic500: interrupt-controller@1800000 { --=20 2.52.0 From nobody Tue Apr 7 04:41:54 2026 Received: from mta-64-225.siemens.flowmailer.net (mta-64-225.siemens.flowmailer.net [185.136.64.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E3EA34B1A1 for ; Mon, 16 Mar 2026 07:05:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644755; cv=none; b=MFdK+bHKrKZ1lwRbKTrMLdwjU/9GMf4ar/Sj/YtW0TVNbwsFt+vjfdRoU7mHjbLtDhtCwraJRfWplK8nVG9U3G1r7pOy6iRc/sLYuEoRkML6R4lSjCXs+PSbW3wlN/N6vZFOEOC2iLM86hfl2lfOUrha9G+EX0ASxgsJSXRakAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644755; c=relaxed/simple; bh=AKyxp5Owb55QcnIoyeAfKcR7uO+dojDomwowHlnfO3M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lhWHqcaDQ3Jct4BKSMxYY4aE9tmvLIIGyXyva60GtrEgzbb4DDFHPlh11h1Clli8VWuSUqpFw2SInpIt8j1IkOdia1bLA2grtyCbUC8ait7gM9GtNVowucHxbAsIBgdpPq4n0d2zV3f24aI9rQhzbMLUYOughZ+Ujp/7N/eXVdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=TbFNW1Dx; arc=none smtp.client-ip=185.136.64.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="TbFNW1Dx" Received: by mta-64-225.siemens.flowmailer.net with ESMTPSA id 2026031607054233adf975ef0002072b for ; Mon, 16 Mar 2026 08:05:42 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=6vGAJVpZ1jpQDkOyacjMdeipgp709TifBFgj8Np5dLw=; b=TbFNW1DxAFl2RX3wTAh1skXmbZ9eD1YCqF8vA6rhSICghukMCpENByqULSz0EPckxAM8CX P627luJfeH6MYOjyABVydvAwq9JTjcUC7uOW+3RhRmmaZils4MxzSkLAzLYkmBBFMSJ9wEQf GtUlvX/E8CzRUknJasdu8Wyxky8CwZXswp5+THloQpnFagYUvAlHLdMqimhF9QTFzglvL3LS LvWFZ93YFzBPR2aseLPpNQefO93lsfXUEuLKj8lze4y6rqde244sgLdrAockXbRdIVL8Cxgd e2reS17M/ygqIt5mmbb9rdxdw2jsmWbLeHRZZRmGGupiIEdPiOp471Ow==; From: "A. Sverdlin" To: linux-arm-kernel@lists.infradead.org Cc: Alexander Sverdlin , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Santosh Shilimkar , Andrew Davis , Jayesh Choudhary , Siddharth Vadapalli , Abraham I , Roger Quadros , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] soc: ti: k3-socinfo: Provide reset reason information Date: Mon, 16 Mar 2026 08:04:25 +0100 Message-ID: <20260316070429.1545707-4-alexander.sverdlin@siemens.com> In-Reply-To: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> References: <20260316070429.1545707-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add reset_reason attribute decoging the RST_SRC register present in AM64x and later SoCs of K3 family. Textual representation of the bits was taken from the AM62x Processors Technical Reference Manual, except the POR, which is not signalled explicitly by the reset module. Signed-off-by: Alexander Sverdlin --- Changelog: v2: no changes drivers/soc/ti/k3-socinfo.c | 88 +++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index 676041879eca3..3736c982fd0c8 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -45,6 +45,8 @@ #define JTAG_ID_PARTNO_J722S 0xBBA0 #define JTAG_ID_PARTNO_AM62LX 0xBBA7 =20 +#define CTRL_MMR_RST_SRC 8 + static const struct k3_soc_id { unsigned int id; const char *family_name; @@ -123,6 +125,90 @@ static const struct regmap_config k3_chipinfo_regmap_c= fg =3D { .reg_stride =3D 4, }; =20 +static u32 k3_reset_source; +static const char *const k3_reset_sources[] =3D { + [0] =3D "Reset Caused by MCU Reset Pin", + [1] =3D "Power On Reset", /* Reserved in HW */ + [2] =3D "Main Reset Pin", + [4] =3D "Thermal Reset", + [8] =3D "Debug Subsystem Initiated Reset", + [12] =3D "SMS Cold Reset", + [13] =3D "SMS Warm Reset", + [16] =3D "Software Warm Reset", + [20] =3D "Software Main Warm Reset From MCU CTRL MMR", + [21] =3D "Software Main Warm Reset from MAIN CTRL MMR", + [22] =3D "Watchdog Initiated Reset", + [24] =3D "Software Main Power On Reset From MCU CTRL MMR", + [25] =3D "Software Main Power On Reset From MAIN CTRL MMR", + [30] =3D "Reset Caused by Main ESM Error", + [31] =3D "Reset Caused by MCU ESM Error", +}; + +static ssize_t reset_reason_show(struct device *dev, struct device_attribu= te *attr, char *buf) +{ + int ret, i; + int total =3D 0; + + for (i =3D ARRAY_SIZE(k3_reset_sources); i >=3D 0; i--) { + if (!k3_reset_sources[i] || !(k3_reset_source & BIT(i))) + continue; + + ret =3D sprintf(buf + total, "%s\n", k3_reset_sources[i]); + if (ret < 0) + return ret; + total +=3D ret; + /* Note that several reset sources may be active simultaneously */ + } + + return total; +} + +static DEVICE_ATTR_RO(reset_reason); + +static struct attribute *k3_soc_attrs[] =3D { + &dev_attr_reset_reason.attr, + NULL +}; + +ATTRIBUTE_GROUPS(k3_soc); + +static const struct of_device_id k3_rst_id_table[] =3D { + { + .compatible =3D "ti,am64-rst", + }, + {} +}; + +static void k3_reset_reason_read(struct soc_device_attribute *soc_dev_attr) +{ + struct device_node *node =3D of_find_matching_node(NULL, k3_rst_id_table); + struct regmap *regmap; + + /* AM65x/J721E do not have similar registers */ + if (!node) + return; + + regmap =3D device_node_to_regmap(node); + of_node_put(node); + if (IS_ERR(regmap)) { + pr_err("Cannot obtain %s regmap\n", k3_rst_id_table[0].compatible); + return; + } + + regmap_read(regmap, CTRL_MMR_RST_SRC, &k3_reset_source); + /* + * The register is only being cleared on POR, so we have to clear reset + * source of the current boot manually + */ + regmap_write(regmap, CTRL_MMR_RST_SRC, k3_reset_source); + + /* Simplify the code a bit and use HW-reserved bit for POR indication */ + if (!k3_reset_source) + k3_reset_source |=3D BIT(1); + + soc_dev_attr->custom_attr_group =3D k3_soc_groups[0]; +} + static int k3_chipinfo_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; @@ -183,6 +269,8 @@ static int k3_chipinfo_probe(struct platform_device *pd= ev) of_property_read_string(node, "model", &soc_dev_attr->machine); of_node_put(node); =20 + k3_reset_reason_read(soc_dev_attr); + soc_dev =3D soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { ret =3D PTR_ERR(soc_dev); --=20 2.52.0