From nobody Tue Apr 7 06:33:45 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 065A07263B; Mon, 16 Mar 2026 01:46:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773625566; cv=none; b=SDUBYo+15u+ILDQb8qZX01h8bRIGPV6Fw+1oCbnQmT38f/DUSA5HQjsTj3ruRk5ljmpaSn9Vv2WONrEw2VNv+Bkrx91X6/IGm2HtFZwpC80HdFHq4uAWseyTy4lAv7on/XRDAxb7iFFUZzilZrbz60V0IYg6ERh1R1Ulh6/a14g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773625566; c=relaxed/simple; bh=I+PKHQSn71O3QlN/Tv3HXaKh0pO3w67j0AsZofuNA08=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eb7ztwClcVcZ2GR4eIzJb5MAVfYxDGhmj5Kc9Rw5qIo5u0sN55Wj1we/TgT5/0LLb/ZkPBAFFgQ0L6sJg/Cl0aMqpLowmkZPVdB+1nvBYnQSOhYEkwDvDsztY+83JuP0Cx3zS1sVF9rLuppsuW4hA+PQEKgV1J+Tr36ZulBE8H4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from fric.. (unknown [210.73.43.101]) by APP-01 (Coremail) with SMTP id qwCowAC3XWm+YLdpa+wzCg--.590S3; Mon, 16 Mar 2026 09:45:35 +0800 (CST) From: Jiakai Xu To: kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Jiakai Xu , Jiakai Xu , Andrew Jones Subject: [PATCH v5 1/2] RISC-V: KVM: Fix array out-of-bounds in pmu_ctr_read() and pmu_fw_ctr_read_hi() Date: Mon, 16 Mar 2026 01:45:32 +0000 Message-Id: <20260316014533.2312254-2-xujiakai2025@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260316014533.2312254-1-xujiakai2025@iscas.ac.cn> References: <20260316014533.2312254-1-xujiakai2025@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowAC3XWm+YLdpa+wzCg--.590S3 X-Coremail-Antispam: 1UD129KBjvJXoWxCF1fCFW8Xw1rtF4kZw13Arb_yoW5Ww18pr 47Kw1Yq395trs2vw1Yyw1Duw4Uta1kK3yDGrW7WF18Aw13Wry3JFyqg3sIqF43AF4Yqa4x tw1Iq3WxCFy5Xa7anT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUdFb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280 aVCY1x0267AKxVWxJr0_GcWlnxkEFVAIw20F6cxK64vIFxWle2I262IYc4CY6c8Ij28IcV AaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JF0_Jw1lYx0E x4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI 8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_ GFv_Wrylc2xSY4AK67AK6w4l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr 1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE 14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7 IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2 z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnU UI43ZEXa7IU8XJ55UUUUU== X-CM-SenderInfo: 50xmxthndljiysv6x2xfdvhtffof0/1tbiDAYICWm3WYgougAAsW Content-Type: text/plain; charset="utf-8" When a guest invokes SBI_EXT_PMU_COUNTER_FW_READ or SBI_EXT_PMU_COUNTER_FW_READ_HI on a firmware counter that has not been configured via SBI_EXT_PMU_COUNTER_CFG_MATCH, the pmc->event_idx remains SBI_PMU_EVENT_IDX_INVALID (0xFFFFFFFF). get_event_code() extracts the lower 16 bits, yielding 0xFFFF (65535), which is then used to index into kvpmu->fw_event[]. Since fw_event is only RISCV_KVM_MAX_FW_CTRS (32) entries, this triggers an array-index-out-of-bounds: UBSAN: array-index-out-of-bounds in arch/riscv/kvm/vcpu_pmu.c:255:37 index 65535 is out of range for type 'kvm_fw_event [32]' Add a check for the known unconfigured case (SBI_PMU_EVENT_IDX_INVALID) and a WARN_ONCE guard for any unexpected out-of-bounds event codes, returning -EINVAL in both cases. Fixes: badc386869e2c ("RISC-V: KVM: Support firmware events") Fixes: 08fb07d6dcf71 ("RISC-V: KVM: Support 64 bit firmware counters on RV3= 2") Signed-off-by: Jiakai Xu Signed-off-by: Jiakai Xu Reviewed-by: Andrew Jones --- V3 -> V4: - Fixed WARN_ONCE argument alignment. V2 -> V3: - Added check for SBI_PMU_EVENT_IDX_INVALID. - Added WARN_ONCE for unexpected out-of-bounds event codes. V1 -> V2: - Merged the fixes for pmu_ctr_read() and pmu_fw_ctr_read_hi() into a single commit. - Removed the pr_warn, simply returning -EINVAL instead. --- arch/riscv/kvm/vcpu_pmu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index e873430e596b..ca86c0000809 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -226,7 +226,14 @@ static int pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, u= nsigned long cidx, if (pmc->cinfo.type !=3D SBI_PMU_CTR_TYPE_FW) return -EINVAL; =20 + if (pmc->event_idx =3D=3D SBI_PMU_EVENT_IDX_INVALID) + return -EINVAL; + fevent_code =3D get_event_code(pmc->event_idx); + if (WARN_ONCE(fevent_code >=3D SBI_PMU_FW_MAX, + "Invalid firmware event code: %d\n", fevent_code)) + return -EINVAL; + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; =20 *out_val =3D pmc->counter_val >> 32; @@ -251,7 +258,14 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigne= d long cidx, pmc =3D &kvpmu->pmc[cidx]; =20 if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + if (pmc->event_idx =3D=3D SBI_PMU_EVENT_IDX_INVALID) + return -EINVAL; + fevent_code =3D get_event_code(pmc->event_idx); + if (WARN_ONCE(fevent_code >=3D SBI_PMU_FW_MAX, + "Invalid firmware event code: %d\n", fevent_code)) + return -EINVAL; + pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; } else if (pmc->perf_event) { pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &= running); --=20 2.34.1 From nobody Tue Apr 7 06:33:45 2026 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED48A5CDF1; Mon, 16 Mar 2026 01:46:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773625567; cv=none; b=mfnT8qN/eOIxwwyc7V6awWuCwt4w2L/NuuURoWZHLfxOs3bC1wLv0wOXf48DDMtNsT+IthdQdqg6+EPYbNT/hQ+s6YrPhnUUKMALRs1vohxRFkFkkxXhGY6KexeWGSSnxFvhyGiPRRcLejpeUPGIJyNVI0EsyY+Mkf/lcDdwnQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773625567; c=relaxed/simple; bh=nh6GZhHYYdkesS9Wzkv1OE5SuICdD1chqsQfvUsN3dE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tC+5dRXgLcvnNDDdhXHk5lWjBQhiC5kBKZN7cOjlA0MVRPcS/FMPmLpFJW/jwo4vXxOX5heJ3KLYjC6Dmhm/Wm4Kquo6LYeZpeDKJlwvX8XX9wthOTsHxA77VtNJ9hlTnyh4aSUaraJkO1AbzXD4V7f7wKo+TjYjuD+sVQkoGH8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from fric.. (unknown [210.73.43.101]) by APP-01 (Coremail) with SMTP id qwCowAC3XWm+YLdpa+wzCg--.590S4; Mon, 16 Mar 2026 09:45:35 +0800 (CST) From: Jiakai Xu To: kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Albert Ou , Alexandre Ghiti , Andrew Jones , Anup Patel , Atish Patra , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , Jiakai Xu , Jiakai Xu , Andrew Jones , Nutty Liu Subject: [PATCH v5 2/2] RISC-V: KVM: selftests: Fix firmware counter read in sbi_pmu_test Date: Mon, 16 Mar 2026 01:45:33 +0000 Message-Id: <20260316014533.2312254-3-xujiakai2025@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260316014533.2312254-1-xujiakai2025@iscas.ac.cn> References: <20260316014533.2312254-1-xujiakai2025@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qwCowAC3XWm+YLdpa+wzCg--.590S4 X-Coremail-Antispam: 1UD129KBjvJXoWxGw4ftFW7ZFWkXFWDZF1DWrg_yoWrCry7pF WkGFWYkrWrtrnFyFy3A3ZFgr1UXan3ZasrKrW7Wry2yr4UXryfXrsIgF9Fyan8CFZYg343 Aw1Iga1rCFsxJF7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHE14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxd M2kKe7AKxVWUXVWUAwAac4AC62xK8xCEY4vEwIxC4wAS0I0E0xvYzxvE52x082IY62kv04 87Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280 aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67 IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWr XwCY02Avz4vE14v_KwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s 026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_ GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20x vEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv 67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyT uYvjTRJZ2-DUUUU X-CM-SenderInfo: 50xmxthndljiysv6x2xfdvhtffof0/1tbiBwwICWm3WbMoEgAAsE Content-Type: text/plain; charset="utf-8" The current sbi_pmu_test attempts to read firmware counters without configuring them first with SBI_EXT_PMU_COUNTER_CFG_MATCH. Previously this did not fail because KVM incorrectly allowed the read and accessed fw_event[] with an out-of-bounds index when the counter was unconfigured. After fixing that bug, the read now correctly returns SBI_ERR_INVALID_PARAM, causing the selftest to fail. Update the test to configure a firmware event before reading the counter. Also add a negative test to ensure that attempting to read an unconfigured firmware counter fails gracefully. Signed-off-by: Jiakai Xu Signed-off-by: Jiakai Xu Reviewed-by: Andrew Jones Reviewed-by: Nutty Liu --- V4 -> V5: - Fixed alignment of fw_eidx assignment. V2 -> V3: - Removed unnecessary BIT(ret.value) & counter_mask_available check. - Asserted ret.value =3D=3D i after successful CFG_MATCH. - Fixed eidx construction in SBI_EXT_PMU_COUNTER_CFG_MATCH. --- .../testing/selftests/kvm/include/riscv/sbi.h | 37 +++++++++++++++++++ .../selftests/kvm/riscv/sbi_pmu_test.c | 20 +++++++++- 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testin= g/selftests/kvm/include/riscv/sbi.h index 046b432ae896..16f1815ac48f 100644 --- a/tools/testing/selftests/kvm/include/riscv/sbi.h +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -97,6 +97,43 @@ enum sbi_pmu_hw_generic_events_t { SBI_PMU_HW_GENERAL_MAX, }; =20 +enum sbi_pmu_fw_generic_events_t { + SBI_PMU_FW_MISALIGNED_LOAD =3D 0, + SBI_PMU_FW_MISALIGNED_STORE =3D 1, + SBI_PMU_FW_ACCESS_LOAD =3D 2, + SBI_PMU_FW_ACCESS_STORE =3D 3, + SBI_PMU_FW_ILLEGAL_INSN =3D 4, + SBI_PMU_FW_SET_TIMER =3D 5, + SBI_PMU_FW_IPI_SENT =3D 6, + SBI_PMU_FW_IPI_RCVD =3D 7, + SBI_PMU_FW_FENCE_I_SENT =3D 8, + SBI_PMU_FW_FENCE_I_RCVD =3D 9, + SBI_PMU_FW_SFENCE_VMA_SENT =3D 10, + SBI_PMU_FW_SFENCE_VMA_RCVD =3D 11, + SBI_PMU_FW_SFENCE_VMA_ASID_SENT =3D 12, + SBI_PMU_FW_SFENCE_VMA_ASID_RCVD =3D 13, + + SBI_PMU_FW_HFENCE_GVMA_SENT =3D 14, + SBI_PMU_FW_HFENCE_GVMA_RCVD =3D 15, + SBI_PMU_FW_HFENCE_GVMA_VMID_SENT =3D 16, + SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD =3D 17, + + SBI_PMU_FW_HFENCE_VVMA_SENT =3D 18, + SBI_PMU_FW_HFENCE_VVMA_RCVD =3D 19, + SBI_PMU_FW_HFENCE_VVMA_ASID_SENT =3D 20, + SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD =3D 21, + SBI_PMU_FW_MAX, +}; + +/* SBI PMU event types */ +enum sbi_pmu_event_type { + SBI_PMU_EVENT_TYPE_HW =3D 0x0, + SBI_PMU_EVENT_TYPE_CACHE =3D 0x1, + SBI_PMU_EVENT_TYPE_RAW =3D 0x2, + SBI_PMU_EVENT_TYPE_RAW_V2 =3D 0x3, + SBI_PMU_EVENT_TYPE_FW =3D 0xf, +}; + /* SBI PMU counter types */ enum sbi_pmu_ctr_type { SBI_PMU_CTR_TYPE_HW =3D 0x0, diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testi= ng/selftests/kvm/riscv/sbi_pmu_test.c index 924a335d2262..cec1621ace23 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -436,6 +436,7 @@ static void test_pmu_basic_sanity(void) struct sbiret ret; int num_counters =3D 0, i; union sbi_pmu_ctr_info ctrinfo; + unsigned long fw_eidx; =20 probe =3D guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); GUEST_ASSERT(probe && out_val =3D=3D 1); @@ -461,7 +462,24 @@ static void test_pmu_basic_sanity(void) pmu_csr_read_num(ctrinfo.csr); GUEST_ASSERT(illegal_handler_invoked); } else if (ctrinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { - read_fw_counter(i, ctrinfo); + /* Read without configure should fail */ + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, + i, 0, 0, 0, 0, 0); + GUEST_ASSERT(ret.error =3D=3D SBI_ERR_INVALID_PARAM); + + /* + * Try to configure with a common firmware event. + * If configuration succeeds, verify we can read it. + */ + fw_eidx =3D ((unsigned long)SBI_PMU_EVENT_TYPE_FW << 16) | + SBI_PMU_FW_ACCESS_LOAD; + + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, + i, 1, 0, fw_eidx, 0, 0); + if (ret.error =3D=3D 0) { + GUEST_ASSERT(ret.value =3D=3D i); + read_fw_counter(i, ctrinfo); + } } } =20 --=20 2.34.1