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Sun, 15 Mar 2026 18:12:53 -0700 (PDT) From: Bryan O'Donoghue Date: Mon, 16 Mar 2026 01:12:45 +0000 Subject: [PATCH v2 03/11] arm64: dts: qcom: x1e80100: Add CAMSS block definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-x1e-camss-csi2-phy-dtsi-v2-3-859f3fa55790@linaro.org> References: <20260316-x1e-camss-csi2-phy-dtsi-v2-0-859f3fa55790@linaro.org> In-Reply-To: <20260316-x1e-camss-csi2-phy-dtsi-v2-0-859f3fa55790@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=11119; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=hEF2lN1urW8zssRTsEXfW+Q2/UUrb+UsBDx6A7JIpcw=; b=owEBbQKS/ZANAwAKASJxO7Ohjcg6AcsmYgBpt1kZTf8O5Wx1HVkb2CYmFUCoVtHoUqAFB05Vv ZAnf4QI76OJAjMEAAEKAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCabdZGQAKCRAicTuzoY3I OrlpEACVhaB+UlzQc3cmoyjHH8OlKi7gCQIWQLVwILOKtvUuUyS3fnBEwHRwxMV8bk2gDXVtxuG /7yycak2tho9aPl1Thwk0q/AY2/FJ8OIoI++nXEZZ1f6AjHIDK0dc1AlVSPA2TvDoWgV112+V1M 9+rNcwqm4HxzJ/Sva+2FSq28tpG2N4hzyRo7YAX0nAYW7iXSKGvVkG7UtMkO1uZsLWkRVJlAmyg s5AtFUpcFgJ9a6rIqgc24GhL1PdDRiqKO1s7VwU8BsUYM6VsmYLeD9fFMOzCXUX1bS8VqoYI5rZ 9ZFTzI+KECkMMEtJV3EGKcW43/dow5iprWEZfJMeUl9dzgxmBewLlIC2SxJJ8tEITu/HM/CogFg qnoseoWZc2YHm0s1SBrnSlSwsIjgMyAiLTLR+9oYab83AkweyKxSrShRfs7xSd0pobNVFmYwjTX 29agVhowlnwMtvMlcDCqaLtAPpUc4ohVcReL7fgYSmdPRngXKkhQT6Ie0AkoQ1qyosIT63pPAHE L4Gpi32LTQBmG4XJFh85ENRVBIUm4/WgUZFXRe0Gr7QXduwfl7fT5p98cLXzyx6niOcR3syl87o y7Dg1lHZNe17Oz2BPkAsWnOfavz/8gBev1diy+i4LpjRjrm3qOOZtHXj8zXLTy3NVn6MBzp0vDY VE57N24JXCVfoDw== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A Add dtsi to describe the xe180100 CAMSS block 4 x CSIPHY 3 x TPG 2 x CSID 2 x CSID Lite 2 x IFE 2 x IFE Lite Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 367 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 38f9da6ad9ca5..c62187856a451 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -5543,6 +5544,372 @@ cci1_i2c1: i2c-bus@1 { }; }; =20 + camss: isp@acb7000 { + compatible =3D "qcom,x1e80100-camss", "simple-mfd"; + + reg =3D <0 0x0acb7000 0 0x2000>, + <0 0x0acb9000 0 0x2000>, + <0 0x0acbb000 0 0x2000>, + <0 0x0acc6000 0 0x1000>, + <0 0x0acca000 0 0x1000>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x1000>, + <0 0x0ace6000 0 0x1000>, + <0 0x0ace8000 0 0x1000>, + <0 0x0acec000 0 0x4000>, + <0 0x0acf6000 0 0x1000>, + <0 0x0acf7000 0 0x1000>, + <0 0x0acf8000 0 0x1000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0acc7000 0 0x2000>, + <0 0x0accb000 0 0x2000>; + + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe_lite", + "cphy_rx_clk_src", + "csid", + "csid_csiphy_rx", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy4", + "csiphy4_timer", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy4", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x800 0x60>, + <&apps_smmu 0x820 0x60>, + <&apps_smmu 0x840 0x60>, + <&apps_smmu 0x860 0x60>, + <&apps_smmu 0x18a0 0x0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + phys =3D <&csiphy0 PHY_TYPE_DPHY>, <&csiphy1 PHY_TYPE_DPHY>, + <&csiphy2 PHY_TYPE_DPHY>, <&csiphy4 PHY_TYPE_DPHY>; + phy-names =3D "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + + power-domains =3D <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "ife0", + "ife1", + "top"; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + camss_csiphy0_inep0: endpoint@0 { + reg =3D <0>; + }; + }; + + port@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + camss_csiphy1_inep0: endpoint@0 { + reg =3D <0>; + }; + }; + + port@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + camss_csiphy2_inep0: endpoint@0 { + reg =3D <0>; + }; + }; + + port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + camss_csiphy4_inep0: endpoint@0 { + reg =3D <0>; + }; + }; + }; + + csiphy0: phy@ace4000 { + compatible =3D "qcom,x1e80100-csi2-phy"; + reg =3D <0 0x0ace4000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names =3D "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "top", + "mx", + "mmcx"; + + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + + csiphy1: phy@ace6000 { + compatible =3D "qcom,x1e80100-csi2-phy"; + reg =3D <0 0x0ace6000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names =3D "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "top", + "mx", + "mmcx"; + + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + + csiphy2: phy@ace8000 { + compatible =3D "qcom,x1e80100-csi2-phy"; + reg =3D <0 0x0ace8000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names =3D "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 =3D <&csiphy_mxc_opp_table>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "top", + "mx", + "mmcx"; + + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + + csiphy4: phy@acec000 { + compatible =3D "qcom,x1e80100-csi2-phy"; + reg =3D <0 0x0acec000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>; + clock-names =3D "csiphy", + "csiphy_timer", + "camnoc_axi", + "cpas_ahb"; + + operating-points-v2 =3D <&csiphy_mxa_opp_table>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "top", + "mx", + "mmcx"; + + #phy-cells =3D <1>; + + status =3D "disabled"; + }; + + csiphy_mxc_opp_table: opp-table-mxc { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + + csiphy_mxa_opp_table: opp-table-mxa { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,x1e80100-camcc"; reg =3D <0 0x0ade0000 0 0x20000>; --=20 2.52.0