From nobody Tue Apr 7 08:15:22 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FFFE23AB87 for ; Mon, 16 Mar 2026 01:12:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773623576; cv=none; b=NxmzlZg29EdhkyJvmAjsgTp6FuKfmBdh/jEzrEofdBujFBzHhcB7fLRPfFbJePw1s219yaEFayipLU1tpaPnnmRsI+0fxkW8kxM0MFZ1VmR8pOzNvHj8N4rW100x33es6MbS0EnXgupn4q+9hdm6+0rQnfH1jtIrO+8RI8kSMjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773623576; c=relaxed/simple; bh=89pCG9foB/aUmIOQftGcQVpa85kxE85oYki4tXopqsk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=advGdrqRAfT9hP11NRC6CSY64DEwYJp/TFAWHJqioC5b6brGJ+Lir647arQS/8JACHg9bqKpgekgu459j8guXwDcfZIF8RzLwQ3xUAPCfKCl10mmInkzcogjpIy9cbMalxJsxk4cB15eoPDEuEaHVXOx7YwhxDHNq0p2FGLDONQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Yw0pgsoH; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Yw0pgsoH" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4853f2826f7so43223565e9.1 for ; Sun, 15 Mar 2026 18:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1773623573; x=1774228373; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KvhMcTkFeg87VPIJT1Cy/Iqmh/F0pkytp6qTG1E/Oh4=; b=Yw0pgsoHCP5JEPyStciVDHBwaioHO+vJlOQ1dJMAbNH35gas1gpJyQU76R3op4FPAr dyNZVGWWDrtpLb6z/DRJNV7DzV/AT1SoN2f5JhkYbFsGuaRq2n+/7gjVtr2f3ep5eu9t 9gCv1U+eKfSOuEbqqF6fvV51UzVC9ljipeq9qljNeG+3CtOMdjBeCwbQ0r2i/SbPoMJ1 T4w39X7MOAFo4l+EL/cltFdXdFm/xzKPuFojI92qol9KwcovhnjP+I1WbpqsHiq4BKq4 Wy+7NXWr0PeCBBSYvVEeXYw8WfT+FdfhzSo+Z/1yDjl0o9MgSZSG6b4TQkphSz0tYlKq BYng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773623573; x=1774228373; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=KvhMcTkFeg87VPIJT1Cy/Iqmh/F0pkytp6qTG1E/Oh4=; b=ZwF5z4TnENHqiyyxYWsPTRr6xDF1p1kFtjnTuQFUHyUkDXuTCHpI9rcGeVuUFPcmOt MI5e9qMNjsH4RD27x+DZwShwvkRzz0PMyBiU+G3gUksjZWPC+yodaUnjM62Z0rLyJbNk 4/qRNYuo6oiEMh0udxspuwsof1+XMdxq4kIAwYTGw0Xvc2oEcu63TLg6la3puSoXreDK PAki9BYzNb699pym5VuoxzLPOUmYugkl6yuUnFnVTLkM4jbofbmTmduGJt6EouTM3UlB neUpoC2xzGCf/QJcNL7EPNrZzg0etbKwA3TLVvvLMhZbk8qmh9SPDRHdnEG6imL4F4hy wDDg== X-Forwarded-Encrypted: i=1; AJvYcCUpEw+sfo+jbVbvS87PIcKVxRvktmh663BZtpVZVxWpWvLWoTSLZCr7ZHyXY5+Oa4QXKk2TjpelFI/vOl4=@vger.kernel.org X-Gm-Message-State: AOJu0YzGubwHXlko2UvYuPGlJZ5xrkF+ZXAnXVm3/N4/qrrdnMf5HVtr R88getIQSXD7i01r32gsvO6rq30ySqMV47c7XBONTkCi931bGDig0zISxUodZtzUnEE= X-Gm-Gg: ATEYQzwDf/jNSz3gaJROsyn9cwBN05Wx/MRTaHgCVm62HIh87QWHJrFfIkMWdrAodNE pp2QeV6IcWIXDryx1nWpVYXzYRjNyxoUkm+HaZS8VozawL5ULR1I4dA57mjuxUrDDyWifqQ4Ssx kd1Nmh30JV724rTtZdyx0Uq5qLsNpdZZpJbj+kl26YXGgBw0sHKVHYRvJkBgXamLapHAmwndYDE r+cVV2zYddz/vnqT6Tl7s8uwFTxsuikDwpFirYb4P1IT3e191Di7WtZFMSJSh5SvPSmh+OGUVXl /ongH9/DLvyRKO3wHH5zvjpv/XHr9F5/R6Oyg3GgpAUu12UTqKS02QYZ85GHctEVkrPxz+7oJK+ wf3DvDmJzfsZrI7moSGXBK2WjLAIyY9jmgUouVKTiQIEkH7KXIA23x0xI0i47sWHGMFtLShY0kD +uQYIpabyrMfRLYqaHdaDc6WWjC2szU1w1o88= X-Received: by 2002:a05:600c:c8d:b0:485:39d4:2dd9 with SMTP id 5b1f17b1804b1-48556711e98mr181894855e9.33.1773623573090; Sun, 15 Mar 2026 18:12:53 -0700 (PDT) Received: from [192.168.0.35] ([109.76.190.215]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48541aba60esm560918225e9.5.2026.03.15.18.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Mar 2026 18:12:51 -0700 (PDT) From: Bryan O'Donoghue Date: Mon, 16 Mar 2026 01:12:44 +0000 Subject: [PATCH v2 02/11] arm64: dts: qcom: x1e80100: Add CCI definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-x1e-camss-csi2-phy-dtsi-v2-2-859f3fa55790@linaro.org> References: <20260316-x1e-camss-csi2-phy-dtsi-v2-0-859f3fa55790@linaro.org> In-Reply-To: <20260316-x1e-camss-csi2-phy-dtsi-v2-0-859f3fa55790@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Konrad Dybcio , Vladimir Zapolskiy X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5073; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=89pCG9foB/aUmIOQftGcQVpa85kxE85oYki4tXopqsk=; b=owEBbQKS/ZANAwAKASJxO7Ohjcg6AcsmYgBpt1kZacTF1LuRO6Z6KnPeg91x2OYB39LuJnGRJ M7dAE5ebguJAjMEAAEKAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCabdZGQAKCRAicTuzoY3I OrttD/oCHB2RG1P3vynPmokNxiXWOghFaN3WbNt+slQm2gMnZ9SzdccxYuKYEdzOh86dslRvuEn QH1/VuTYYjunLMV2lqFujrTs6BazBANQOkQLSjezCzDYEdGoGQRUMdb+/EBrflvIcMNOnmQECcg CTfFWytYw1tApr6ohpGl7eJP5f+Om34LsWlGJ7Yi9nC+3RtuvOcfKTP5lx2J1YN81gRq6ga8bkC TrBKhjc6IXBuzUtJlPSYcxKtgiMIHbtD+QVQxTb7d7+QtF4eIfs8u22VUXduG5vDXaknbEUIkFE 92ertnqyKvAFqXHdguRJIjoB+GGPtHaupINwUCdotT31J8BGt109JqctRiDqWPKDXdE3cfD4gde NT2W1bszLcPuAdPM4C4lzgCdyiE3TJhp6qV1uiuUsWd5HdjFPe/0o1qEUUlYcUq2MlI7ZIVywyo t1YGw+UOVJ4hQfLX/P6jtL+8/f5wHh5Z4O4vLWiNQvKVTYH0g9EbTKbxtoV+UdTXjPu6N57p6TJ TuZeSSNxxySqdXVGbXkACDfVTTFxFDEOqf6rMxEYHIIyqWhHcPoquieq8UO8B4VQhKGThRN077U 09FkZgSqOt3e7oCBm6YZLSpHLJ1L6ihqmaKtBmku+GbQJa7oZLESZyqCk7PBXuH92xw2Fzn7PpV WdnUW1VTImBzi2w== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A Add in two CCI buses. One bus has two CCI bus master pinouts: cci_i2c_sda0 =3D gpio101 cci_i2c_scl0 =3D gpio102 cci_i2c_sda1 =3D gpio103 cci_i2c_scl1 =3D gpio104 The second bus has two CCI bus master pinouts: cci_i2c_sda2 =3D gpio105 cci_i2c_scl2 =3D gpio106 aon_cci_i2c_sda3 =3D gpio235 aon_cci_i2c_scl3 =3D gpio236 Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 150 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 029ec012d0a94..38f9da6ad9ca5 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5465,6 +5465,84 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac15000 { + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac15000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_default>; + pinctrl-1 =3D <&cci0_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac16000 { + compatible =3D "qcom,x1e80100-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac16000 0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_default>; + pinctrl-1 =3D <&cci1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,x1e80100-camcc"; reg =3D <0 0x0ade0000 0 0x20000>; @@ -6115,6 +6193,78 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 239>; wakeup-parent =3D <&pdc>; =20 + cci0_default: cci0-default-state { + cci0_i2c0_default: cci0-i2c0-default-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio101", "gpio102"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci0_i2c1_default: cci0-i2c1-default-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio103", "gpio104"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci0_sleep: cci0-sleep-state { + cci0_i2c0_sleep: cci0-i2c0-sleep-pins { + /* cci_i2c_sda0, cci_i2c_scl0 */ + pins =3D "gpio101", "gpio102"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep-pins { + /* cci_i2c_sda1, cci_i2c_scl1 */ + pins =3D "gpio103", "gpio104"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_default: cci1-default-state { + cci1_i2c0_default: cci1-i2c0-default-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio105", "gpio106"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci1_i2c1_default: cci1-i2c1-default-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins =3D "gpio235", "gpio236"; + function =3D "aon_cci"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + cci1_sleep: cci1-sleep-state { + cci1_i2c0_sleep: cci1-i2c0-sleep-pins { + /* cci_i2c_sda2, cci_i2c_scl2 */ + pins =3D "gpio105", "gpio106"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep-pins { + /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */ + pins =3D "gpio235", "gpio236"; + function =3D "aon_cci"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + edp0_hpd_default: edp0-hpd-default-state { pins =3D "gpio119"; function =3D "edp0_hot"; --=20 2.52.0