From nobody Tue Apr 7 06:21:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDC7034B1A1; Mon, 16 Mar 2026 07:08:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644924; cv=none; b=CGp7BV/40MpqiLmcOrkYv6nTcSBqjkLsSUz5d0RQywagM3S3+2SWlSCtQPAzm7l8OQ+2i5+aUGagRvSpsOF2/76kIksAQCxQYF+PwVjivpEnSB7xmfSOAaPTeD9XJYMDlw48cjUXNVTdP4D1pLeRDZajtDfVWJAJRhl4UW3oAyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773644924; c=relaxed/simple; bh=7JNa/azXas/8ygI+nuLDHtgvWG1Ojpx/lGt6T8WknJo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OiLd+WkuqAqRXyOOJdE7DaPhVFPlGDxdZFTDYfumAzGqUBonOc0AF6ZuwgVD6v9h6ycc5ouFX+QOuFsn9X+f6BWwrZEadPfMQ8wdxvenXMh88neAm0TQRJHJ6KrGsklgLrXCUD8rPMKfYFbYTkRncvzT2qcR1FrcehTaeZyVeyI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hccsN/Dn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hccsN/Dn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8BFDAC2BCAF; Mon, 16 Mar 2026 07:08:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773644924; bh=7JNa/azXas/8ygI+nuLDHtgvWG1Ojpx/lGt6T8WknJo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hccsN/DnyEWEOIURVhoJRyNNjcfHePsiiDfETb0VKyssK3ATbtaRk7hTtDI5bF1In d+5XrSMob6SOKx1yQbB+mcRNh2jFgP2cFoSk4D3TgJBoDZDgjr29acVJ1mpqQXWiJt RWTlGh7mpXk2tw90IaXKLBbgsKkuK16q5j9ejnnvH6DBwnE9coI2STfg+1wiQyCGCn F7OSIDWcWohYxy3FiG/GgTn2iCw+eC9LrsZTh36Y8tr/jpYWdT6vwFNDwYsp5+fVpt 6qQGxnSnhbvMKDmuRRiSNmqVXxzRpWJ9w3z/GRVUZpKOC0Ah+qRzrF3penR1NIsJBj bRiaUncpBmurw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 827DBEFCBDD; Mon, 16 Mar 2026 07:08:44 +0000 (UTC) From: Jia Wang via B4 Relay Date: Mon, 16 Mar 2026 15:07:00 +0800 Subject: [PATCH 4/4] PCI: dwc: Add UltraRISC DP1000 PCIe rc driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-ultrarisc-pcie-v1-4-ef2946ede698@ultrarisc.com> References: <20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com> In-Reply-To: <20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han , Xincheng Zhang , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Jia Wang X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1773644922; l=9411; i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id; bh=tSfhKfbr5/q5BnKydlotmuXWfmzyfzz7sJS5AJBU+XI=; b=afXZZOlq52qEbho3/d36SucpTBSbGpASGiqFD1YQYpstpuOVXbwJsd8PaN4wZT6/FtpTgil43 RvSJdOaINjVCJL77kZPyGxcS1vKDQmZXwF2Qe7RQ6kg/JrfifLn+qix X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260309 with auth_id=682 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Xincheng Zhang Add DP1000 soc PCIe rc driver. Signed-off-by: Xincheng Zhang Signed-off-by: Jia Wang --- drivers/pci/controller/dwc/Kconfig | 15 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware.h | 22 +++ drivers/pci/controller/dwc/pcie-ultrarisc.c | 202 +++++++++++++++++++++++= ++++ 4 files changed, 240 insertions(+) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index d0aa031397fa..0a33891bf7ef 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -548,4 +548,19 @@ config PCIE_VISCONTI_HOST Say Y here if you want PCIe controller support on Toshiba Visconti SoC. This driver supports TMPV7708 SoC. =20 +config PCIE_ULTRARISC + bool "UltraRISC PCIe host controller" + depends on ARCH_ULTRARISC || COMPILE_TEST + select PCIE_DW_HOST + select PCI_MSI + default y if ARCH_ULTRARISC + help + Enables support for the PCIe controller in the UltraRISC SoC. + This driver supports UR-DP1000 SoC. When selected, it automatically + enables both `PCIE_DW_HOST` and `PCI_MSI`, ensuring proper support + for MSI-based interrupt handling in the PCIe controller. + By default, this symbol is enabled when `ARCH_ULTRARISC` is active, + requiring no further configuration on that platform. + + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 67ba59c02038..884c46b78e01 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) +=3D pcie-rcar-gen4.o obj-$(CONFIG_PCIE_SPACEMIT_K1) +=3D pcie-spacemit-k1.o obj-$(CONFIG_PCIE_STM32_HOST) +=3D pcie-stm32.o obj-$(CONFIG_PCIE_STM32_EP) +=3D pcie-stm32-ep.o +obj-$(CONFIG_PCIE_ULTRARISC) +=3D pcie-ultrarisc.o =20 # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ae6389dd9caa..8f2ed86cb5c5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -69,6 +69,8 @@ =20 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_FORCE 0x708 +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ +#define PORT_LINK_NUM_MASK GENMASK(7, 0) #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) =20 #define PCIE_PORT_AFR 0x70C @@ -96,6 +98,26 @@ #define PCIE_PORT_LANE_SKEW 0x714 #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) =20 +/* + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number Reg= ister. + * This register holds the ack frequency, latency, replay, fast link scali= ng timers, + * and max function number values. + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. + * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). + * When the LTSSM is in Config or L12 Entry State, 1ms + * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. + * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) + * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) + * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) + */ +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 +#define PORT_FLT_SF_MASK GENMASK(30, 29) +#define PORT_FLT_SF(n) FIELD_PREP(PORT_FLT_SF_MASK, n) +#define PORT_FLT_SF_1024 PORT_FLT_SF(0x0) +#define PORT_FLT_SF_256 PORT_FLT_SF(0x1) +#define PORT_FLT_SF_64 PORT_FLT_SF(0x2) +#define PORT_FLT_SF_16 PORT_FLT_SF(0x3) + #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f #define PORT_LOGIC_LTSSM_STATE_L0 0x11 diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c new file mode 100644 index 000000000000..64cbf16d3ff7 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DWC PCIe RC driver for UltraRISC DP1000 SoC + * + * Copyright (C) 2023 UltraRISC + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define PCIE_CUS_CORE 0x400000 + +#define LTSSM_ENABLE BIT(7) +#define FAST_LINK_MODE BIT(12) +#define HOLD_PHY_RST BIT(14) +#define L1SUB_DISABLE BIT(15) + +struct ultrarisc_pcie { + struct dw_pcie *pci; + u32 irq_mask[MAX_MSI_CTRLS]; +}; + +static const struct of_device_id ultrarisc_pcie_of_match[]; + +static struct pci_ops ultrarisc_pci_ops =3D { + .map_bus =3D dw_pcie_own_conf_map_bus, + .read =3D pci_generic_config_read32, + .write =3D pci_generic_config_write32, +}; + +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct pci_host_bridge *bridge =3D pp->bridge; + + /* Set the bus ops */ + bridge->ops =3D &ultrarisc_pci_ops; + + return 0; +} + +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops =3D { + .init =3D ultrarisc_pcie_host_init, +}; + +static int ultrarisc_pcie_establish_link(struct dw_pcie *pci) +{ + u32 val; + u8 cap_exp; + + val =3D dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val &=3D ~FAST_LINK_MODE; + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + val =3D dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); + val &=3D ~PORT_FLT_SF_MASK; + val |=3D PORT_FLT_SF_64; + dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); + + cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); + val &=3D ~PCI_EXP_LNKCTL2_TLS; + val |=3D PCI_EXP_LNKCTL2_TLS_16_0GT; + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); + + val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); + val &=3D ~PORT_LINK_NUM_MASK; + dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); + + val =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); + val &=3D ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; + val |=3D 0x6; + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); + + val =3D dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val &=3D ~(HOLD_PHY_RST | L1SUB_DISABLE); + val |=3D LTSSM_ENABLE; + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D ultrarisc_pcie_establish_link, +}; + +static int ultrarisc_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ultrarisc_pcie *ultrarisc_pcie; + struct dw_pcie *pci; + struct dw_pcie_rp *pp; + int ret; + + ultrarisc_pcie =3D devm_kzalloc(dev, sizeof(*ultrarisc_pcie), GFP_KERNEL); + if (!ultrarisc_pcie) + return -ENOMEM; + + pci =3D devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev =3D dev; + pci->ops =3D &dw_pcie_ops; + + /* Set a default value suitable for at most 16 in and 16 out windows */ + pci->atu_size =3D SZ_8K; + + ultrarisc_pcie->pci =3D pci; + + pp =3D &pci->pp; + + platform_set_drvdata(pdev, ultrarisc_pcie); + + pp->irq =3D platform_get_irq(pdev, 1); + if (pp->irq < 0) + return pp->irq; + + pp->num_vectors =3D MAX_MSI_IRQS; + pp->ops =3D &ultrarisc_pcie_host_ops; + + ret =3D dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Failed to initialize host\n"); + return ret; + } + + return 0; +} + +static int ultrarisc_pcie_suspend(struct platform_device *pdev, pm_message= _t state) +{ + struct ultrarisc_pcie *ultrarisc_pcie =3D platform_get_drvdata(pdev); + struct dw_pcie *pci =3D ultrarisc_pcie->pci; + struct dw_pcie_rp *pp =3D &pci->pp; + int num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + unsigned long flags; + int ctrl; + + raw_spin_lock_irqsave(&pp->lock, flags); + + for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) + ultrarisc_pcie->irq_mask[ctrl] =3D pp->irq_mask[ctrl]; + + raw_spin_unlock_irqrestore(&pp->lock, flags); + + return 0; +} + +static int ultrarisc_pcie_resume(struct platform_device *pdev) +{ + struct ultrarisc_pcie *ultrarisc_pcie =3D platform_get_drvdata(pdev); + struct dw_pcie *pci =3D ultrarisc_pcie->pci; + struct dw_pcie_rp *pp =3D &pci->pp; + int num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + unsigned long flags; + int ctrl; + + raw_spin_lock_irqsave(&pp->lock, flags); + + for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) { + pp->irq_mask[ctrl] =3D ultrarisc_pcie->irq_mask[ctrl]; + dw_pcie_writel_dbi(pci, + PCIE_MSI_INTR0_MASK + + ctrl * MSI_REG_CTRL_BLOCK_SIZE, + pp->irq_mask[ctrl]); + } + + raw_spin_unlock_irqrestore(&pp->lock, flags); + + return 0; +} + +static const struct of_device_id ultrarisc_pcie_of_match[] =3D { + { + .compatible =3D "ultrarisc,dp1000-pcie", + }, + {}, +}; + +static struct platform_driver ultrarisc_pcie_driver =3D { + .driver =3D { + .name =3D "ultrarisc-pcie", + .of_match_table =3D ultrarisc_pcie_of_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D ultrarisc_pcie_probe, + .suspend =3D ultrarisc_pcie_suspend, + .resume =3D ultrarisc_pcie_resume, +}; +builtin_platform_driver(ultrarisc_pcie_driver); --=20 2.34.1