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Mon, 16 Mar 2026 20:10:59 +0100 (CET) Received: by jupiter.universe (Postfix, from userid 1000) id A3F9C480035; Mon, 16 Mar 2026 20:10:58 +0100 (CET) From: Sebastian Reichel Date: Mon, 16 Mar 2026 20:10:52 +0100 Subject: [PATCH RFC v5 8/8] PCI: dw-rockchip: port some suspend code from vendor kernel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-rockchip-pcie-system-suspend-v5-8-5bb5ad37d643@collabora.com> References: <20260316-rockchip-pcie-system-suspend-v5-0-5bb5ad37d643@collabora.com> In-Reply-To: <20260316-rockchip-pcie-system-suspend-v5-0-5bb5ad37d643@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Rockchip's vendor kernel does these calls before starting the actual process of going into L2 state. I'm not sure about the rationale, hopefully Shawn can help out with that. Cc: Shawn Lin Signed-off-by: Sebastian Reichel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 3be83feccecb..fbdde82c95b6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -74,6 +74,9 @@ #define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0) #define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1) =20 +/* General Debug Register */ +#define PCIE_CLIENT_GENERAL_DEBUG 0x104 + /* RASDES TBA information */ #define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154 #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4) @@ -776,6 +779,11 @@ static int rockchip_pcie_probe(struct platform_device = *pdev) return ret; } =20 +static inline void rockchip_pcie_link_status_clear(struct rockchip_pcie *r= ockchip) +{ + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_GENERAL_DEBUG, 0x0); +} + static int rockchip_pcie_suspend(struct device *dev) { struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); @@ -789,6 +797,11 @@ static int rockchip_pcie_suspend(struct device *dev) =20 rockchip->intx =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MAS= K_LEGACY); =20 + /* All sub-devices are in D3hot by PCIe stack */ + dw_pcie_dbi_ro_wr_dis(pci); + + rockchip_pcie_link_status_clear(rockchip); + ret =3D dw_pcie_suspend_noirq(pci); if (ret) return ret; --=20 2.51.0