From nobody Tue Apr 7 04:21:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 662DB3EDABD; Mon, 16 Mar 2026 19:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773688264; cv=none; b=F8KmkfUBD1LoUocP25kZoY+aEsLSlR4BAovUNB/HsM2SE55DV1HSj9CRvTv+GEZTsPsxv3qpEYTwI5TBypuxKfJk6reSR35ykVeFq8zoB9AIuScFJAaaHENSxjRAJwYtSW45Ethn4OIa5aYiF/SCY46rRdoDV237xm3h3igmjKk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773688264; c=relaxed/simple; bh=VmFPKdenj3QFsYbLP0ILMBFLE2Mcejoa2t1BOAKrK+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ajoJCxXC5TUAcR0lhmh54vumY0uw42+uDMJQHcRQh3SP7HqjRtpjr1XdiviImYAx5qppk9M8DsuR9lKXxUAisXw5G9VUSssA2kQd53VDm0al4xYn8Y2WuU0uXfAurkxzxLY9cJRo3DbN3LIYfF3gvUigDnfM7sXfCYHfR+O4o24= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QCFudlw+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QCFudlw+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1773688259; bh=VmFPKdenj3QFsYbLP0ILMBFLE2Mcejoa2t1BOAKrK+k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QCFudlw+FYNmjsNVUY55FuI6Uv+hGDglS4rn8tZoRthRiZBpVVJYM4OZWBHopRhYr XgoYxhKUCp9j/QZLfbuXo4gUrdfBFKDjkpNFxl6N9uPVMTMmuzU9Qq+Ldrld8hhlf6 1BX7TnsVHOEmja5kw5JwLw8F4WAhFE7tkO41VR6gd1qgCTqtuV29y366YONt6XNcBy hfE47+KQD7SiErY0m66l5/LOsz5jU8mAlY6OS0GyJNHCs7XVztuyH/T19rmhfIgEdD he2qUH98FLS3hiKxg98uQ20s+qPdXf2FyMnMDWk9Ddnu8ZmLos/CJFDQhB++PcCF6y DRKwQDijk+/6Q== Received: from jupiter.universe (dyndsl-091-248-189-119.ewe-ip-backbone.de [91.248.189.119]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4ECEE17E1525; Mon, 16 Mar 2026 20:10:59 +0100 (CET) Received: by jupiter.universe (Postfix, from userid 1000) id A3436480031; Mon, 16 Mar 2026 20:10:58 +0100 (CET) From: Sebastian Reichel Date: Mon, 16 Mar 2026 20:10:51 +0100 Subject: [PATCH v5 7/8] PCI: dw-rockchip: Add system PM support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-rockchip-pcie-system-suspend-v5-7-5bb5ad37d643@collabora.com> References: <20260316-rockchip-pcie-system-suspend-v5-0-5bb5ad37d643@collabora.com> In-Reply-To: <20260316-rockchip-pcie-system-suspend-v5-0-5bb5ad37d643@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4482; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=VmFPKdenj3QFsYbLP0ILMBFLE2Mcejoa2t1BOAKrK+k=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGm4VcIjnhQdxoD++5bjt1A4x2JyA6ob8cWxr h3uWMtEdM4fwYkCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJpuFXCAAoJENju1/PI O/qa5IAP/i1HIAFdpdeL08mlUd6WO2+90E9km0y2etMPWJ3Xk6yAUliDhuGID86smEUNWPhZQPI 8rsTG9JH5hLlpmfyYkhUmStmwzwMOaZ95/2wBMNBxCpoEC8gsfE1cFEdJCTjQDheOOLweFmoYDK US6UqC75fxUtC+v56ICEALKYv2ssSUmamF151QPzV4fUY7U0D3H3nTvB7O1tqkFiqH3ty8UlS/L wopXLKSpd9+Bl0kNko2kKc/Aa70/BCi6nscgnfFNwIlrDWK3Zgnb5UwHCmupkz5iYPpyAB9Zvja gDSWpwZXVtufENBbm1cfgZfXaSM4/N1ZkwQtSV3Ovtnu3M6UvC7f4uINXeEMfqfVsu2SsxGYkFg 9rBTzenbeoynKwdMchHg83zGHHd/9yqufgCHE984++CzA3IrutXeG9Wc4Ipzh+b7ILSV85TFJC6 Z+tuL7OUPrHWb4IVKosDQxvMAWMkJZZ47bZ+3zQnKKXE+tCmfonls9A/eIeaL38oYlz/8IMvkl9 65tqdIhkGVFdb8g8f+PwjeixoPIwT5zJ2ddbp6+77omf9W5djvifdWXDGMmaqU+se2ekTbd4OKY MoGzlhhf6dI86x0SMAwZ6XcN5tP7gGBG3QcLvmvY/oyTfnJBssIblriGjFUTCtfgQG458wcKWif QpBk0QcpIsN+LkkLyMvo0dQ== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Add system PM support for Rockchip PCIe Designware Controllers. I've tested this on the Rockchip RK3576 EVB1, the Radxa ROCK 4D and the ArmSom Sige5 boards. While I haven't experienced any issues, most of my tests have been done without any devices attached (i.e. default board without any extras), so there _might_ still be some problems. As system suspend does not work at all right now, I think it makes sense to get at least the basic configurations working as soon as possible as it will allow us to catch regressions by enabling system suspend in CI systems like KernelCI. Co-developed-by: Shawn Lin Signed-off-by: Shawn Lin Signed-off-by: Sebastian Reichel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 93 +++++++++++++++++++++++= ++++ 1 file changed, 93 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 147add66db15..3be83feccecb 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -103,6 +103,7 @@ struct rockchip_pcie { struct gpio_desc *rst_gpio; struct regulator *vpcie3v3; struct irq_domain *irq_domain; + u32 intx; const struct rockchip_pcie_of_data *data; bool supports_clkreq; }; @@ -775,6 +776,92 @@ static int rockchip_pcie_probe(struct platform_device = *pdev) return ret; } =20 +static int rockchip_pcie_suspend(struct device *dev) +{ + struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &rockchip->pci; + int ret; + + if (rockchip->data->mode =3D=3D DW_PCIE_EP_TYPE) { + dev_err(dev, "suspend is not supported in EP mode\n"); + return -EOPNOTSUPP; + } + + rockchip->intx =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_MAS= K_LEGACY); + + ret =3D dw_pcie_suspend_noirq(pci); + if (ret) + return ret; + + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); + rockchip_pcie_phy_deinit(rockchip); + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); + reset_control_assert(rockchip->rst); + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); + + return 0; +} + +static int rockchip_pcie_resume(struct device *dev) +{ + struct rockchip_pcie *rockchip =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &rockchip->pci; + int ret; + + if (rockchip->data->mode =3D=3D DW_PCIE_EP_TYPE) { + dev_err(dev, "resume is not supported in EP mode\n"); + return -EOPNOTSUPP; + } + + ret =3D clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks); + if (ret) { + dev_err(dev, "clock init failed: %d\n", ret); + return ret; + } + + if (rockchip->vpcie3v3) { + ret =3D regulator_enable(rockchip->vpcie3v3); + if (ret) + goto err_disable_clk; + } + + ret =3D rockchip_pcie_phy_init(rockchip); + if (ret) { + dev_err(dev, "phy init failed: %d\n", ret); + goto err_disable_regulator; + } + + reset_control_deassert(rockchip->rst); + + rockchip_pcie_writel_apb(rockchip, FIELD_PREP_WM16(0xffff, rockchip->intx= ), + PCIE_CLIENT_INTR_MASK_LEGACY); + + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, 0); + rockchip_pcie_set_controller_mode(rockchip, PCIE_CLIENT_MODE_RC); + rockchip_pcie_unmask_dll_indicator(rockchip); + + gpiod_set_value_cansleep(rockchip->rst_gpio, 1); + + ret =3D dw_pcie_resume_noirq(pci); + if (ret) { + dev_err(dev, "failed to resume: %d\n", ret); + goto err_deinit_phy; + } + + return 0; + +err_deinit_phy: + gpiod_set_value_cansleep(rockchip->rst_gpio, 0); + rockchip_pcie_phy_deinit(rockchip); +err_disable_regulator: + if (rockchip->vpcie3v3) + regulator_disable(rockchip->vpcie3v3); +err_disable_clk: + clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); + return ret; +} + static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = =3D { .mode =3D DW_PCIE_RC_TYPE, }; @@ -805,11 +892,17 @@ static const struct of_device_id rockchip_pcie_of_mat= ch[] =3D { {}, }; =20 +static const struct dev_pm_ops rockchip_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_pcie_suspend, + rockchip_pcie_resume) +}; + static struct platform_driver rockchip_pcie_driver =3D { .driver =3D { .name =3D "rockchip-dw-pcie", .of_match_table =3D rockchip_pcie_of_match, .suppress_bind_attrs =3D true, + .pm =3D &rockchip_pcie_pm_ops, }, .probe =3D rockchip_pcie_probe, }; --=20 2.51.0