From nobody Tue Apr 7 04:36:15 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D9E139B4A2 for ; Mon, 16 Mar 2026 14:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773669874; cv=none; b=OMOfhuqEGEh0uWAd88Dgk6Xswrh1kor6/APfjJ50krvFNdmlwzCODyT2fFg9I3/gIpm5zVNqe3D1AFaaJkDZl49+wyw12kkgHPS6a3Dss7RzNU0TX870CdeUPXSeR6t/1iZEW3NlVYqCpSZYGaXkYo4memSnJrufO+GwiHIg7VE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773669874; c=relaxed/simple; bh=EIbrLuhe1ooGthxEgQtJO7e+J6yAKFsxYGpGpHEbBow=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F5CphJE8G0HvTDTbnb0voh/q6aA/5SZHbzfDEx8NPIPFTS2QmHtsrnEnFzQHeU6bdLaPqvMWJt6BjGLa6KpvGoDRkngIR+37jVDwKRBNKBSt+mc1oENPzQ4JSvvY4jh1Xu2/PfW1HVHm8BZbCm+MT021C21F2lSvU8ftCAAFQSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GaDgUCxy; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GaDgUCxy" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-439b9b1900bso2995661f8f.1 for ; Mon, 16 Mar 2026 07:04:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773669871; x=1774274671; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9V4OY+Uejyw2avNrbAtAaf1qtY8TrzCMiBRo5m6knWA=; b=GaDgUCxydsqiBf5Cey9KAqo2GzIm1m6RH7HMMhpQ5/RHFqzKD9WjRWJuRh58VZC0rB ZBz6ZzQYrsJsB48mFdlOxe59Igj3iTG4yd9KuzuYXMERRT80AJEz/OxjbdCo7xeGxGXB mNO5Qhx1naafHWa12EJ3qrVKntnduUs0RO5nL+5qRUliGw6GBV77UDUCeyFRtCALKcsk SAzHDReBR24ABHWQ5OlsxK/kAuyoNtUAjGAYfaRfi14JFGerwgWO07S5NU2Gtj6dt4nz Y7rALaOEU67FkK0HelhYS8R2MggyuwRSJnDHRODfwCXCOyGrGkibTmcGzcbBZe6fYKIw Yjgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773669871; x=1774274671; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=9V4OY+Uejyw2avNrbAtAaf1qtY8TrzCMiBRo5m6knWA=; b=W767XxxsplhKLvSaXj6cqBPx+QbMlKNgpdXho1Yd8aqIqubWAb7jhBq8Y8z/agg3lX jIcwqOeOP8gV8wkhWc7Jh4YfvBjQWPqCrN22FqQx82IyGEMqp278j8Aqpq8h+EBdh5Mz ivNnYbLqMlhmuxvtYan3vZJuu/0PoNJdgdZzyT2NlkGMy/YdjnBCyq56OJBpB5qbMFcF Ip3g4K6hLY3xJQELBOfXtBXfWxLO4tXb1Q1L4yvA4D0UfctSRP/lqUA3C7R2ZqeRysnV dosLDn/PQi1ihTVxot6HZcv8nEjIbHjmEFD5ejciK2lwBY+7a5PV4lukHQy7ShZbh1Mn zOyw== X-Forwarded-Encrypted: i=1; AJvYcCWxA8yr86LBe5cAXsOCZvSbcL/97Vqyi+YeN2CL4t2Ef7ypIZulcENtbAh9A2/urcpmVZvRKYwPXNL/aao=@vger.kernel.org X-Gm-Message-State: AOJu0YxCKRjmYfAXuzQAMo0wVHU4/RVeL9MxsWzuuJI9dRn4VYiVewMI I7T4kUwqp2eScf6uYKVlsqsDKuNPctXF/jWJTElTe2oz2SX2AkIClb9A X-Gm-Gg: ATEYQzxgagRGYoWyS6smLjmpBoH7vooQ+V1avSTeyUgCBU5iuGUl9ruEgipJZThNZBG dnCjYnGAggol7Qe5sywxj1qQdfK8UzxCjDsyCCo4clM6N4yyUTruP+tIAyzctfru/IHL4sapPWr 6507RK8ejfVn3y1ocR/SZe/YnatpetV/G2PGMUvaSss93EsBHfJHNvwKLQOFSu+ng+0tIbhB5x4 bAC/UgIIyFEeSnc2TSQkb8CmP1oV4AoqmMoUuv52Jq/g3DTs/MbrL7/HQ65lxNHEV/VmhtzEydc 1NBmdXc/ONG1e0X621U1dwMYDUspb9kbWTCyeuhVZHYlBtHTpnDlf1JpJTnCqecZaAtcCNBlocF mLp9WbaRdPT9AHiKQsXushm9dJJfgu40o52NNjeBxbvOSuySnj4VwVLAjB//+Nu/4lXmF+VP47x Z3+gqG8K6JFGGgssnK4F1MHwdEJrX80M59ak3ZIsc334E2+L8AqG+CWczJniwiNtTr X-Received: by 2002:a05:6000:4012:b0:43b:44e1:f661 with SMTP id ffacd0b85a97d-43b44e1f791mr5650973f8f.36.1773669870494; Mon, 16 Mar 2026 07:04:30 -0700 (PDT) Received: from ipedrosa-thinkpadx1carbongen12.rmtes.csb ([67.218.234.31]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b3a09e453sm20698725f8f.0.2026.03.16.07.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2026 07:04:29 -0700 (PDT) From: Iker Pedrosa Date: Mon, 16 Mar 2026 15:03:31 +0100 Subject: [PATCH v3 3/7] mmc: sdhci-of-k1: add comprehensive SDR tuning support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-orangepi-sd-card-uhs-v3-3-aefd3b7832df@gmail.com> References: <20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com> In-Reply-To: <20260316-orangepi-sd-card-uhs-v3-0-aefd3b7832df@gmail.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Yixun Lan Cc: Michael Opdenacker , Javier Martinez Canillas , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Iker Pedrosa , Anand Moon X-Mailer: b4 0.14.2 Implement software tuning algorithm to enable UHS-I SDR modes for SD card operation and HS200 mode for eMMC. This adds both TX and RX delay line tuning based on the SpacemiT K1 controller capabilities. Algorithm features: - Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) - Conditional tuning: only for high-speed modes (=E2=89=A5100MHz) - TX tuning: configure transmit delay line with optimal values (dline_reg=3D0, delaycode=3D127) to ensure optimal signal output timing - RX tuning: single-pass window detection algorithm testing full delay range (0-255) to find optimal receive timing window - Retry mechanism: multiple fallback delays within optimal window for improved reliability Tested-by: Anand Moon Signed-off-by: Iker Pedrosa Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 172 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c index 01afdadcf70796704b272ee5a31543afd5e01188..83d7f9fad5c1fba2f07624ee657= cd979a1c7e25d 100644 --- a/drivers/mmc/host/sdhci-of-k1.c +++ b/drivers/mmc/host/sdhci-of-k1.c @@ -69,6 +69,28 @@ #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) #define SDHC_RX_BIAS_CTRL BIT(5) =20 +#define SPACEMIT_SDHC_RX_CFG_REG 0x118 +#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) +#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) +#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK= , 1) + +#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 +#define SDHC_DLINE_PU BIT(0) +#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) +#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) + +#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 +#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) +#define SDHC_RX_DLINE_GAIN BIT(8) +#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) + +#define SPACEMIT_RX_DLINE_REG 9 +#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 +#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF + +#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 +#define SPACEMIT_TX_TUNING_DELAYCODE 127 + struct spacemit_sdhci_host { struct clk *clk_core; struct clk *clk_io; @@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdh= ci_host *host, u32 clr, u sdhci_writel(host, val, reg); } =20 +static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) +{ + spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, + FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), + SPACEMIT_SDHC_DLINE_CTRL_REG); +} + +static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) +{ + spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, + FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), + SPACEMIT_SDHC_DLINE_CTRL_REG); +} + +static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dl= ine_reg) +{ + spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, + FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), + SPACEMIT_SDHC_DLINE_CFG_REG); +} + +static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) +{ + spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); + spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); + udelay(5); +} + +static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) +{ + spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, + FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), + SPACEMIT_SDHC_DLINE_CFG_REG); + + spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); + udelay(5); + + spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SE= L1, + SPACEMIT_SDHC_RX_CFG_REG); + + if (host->mmc->ios.timing =3D=3D MMC_TIMING_MMC_HS200) + spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUN= C_REG); +} + static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) { sdhci_reset(host, mask); @@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(= struct sdhci_host *host) return clk_get_rate(pltfm_host->clk); } =20 +static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opco= de) +{ + int current_len =3D 0, current_start =3D 0; + int max_pass_len =3D 0, max_pass_start =3D 0; + struct mmc_host *mmc =3D host->mmc; + struct mmc_ios ios =3D mmc->ios; + u8 final_delay; + int ret =3D 0; + int i; + + /* + * Tuning is required for SDR50/SDR104, HS200/HS400 cards and + * if clock frequency is greater than 100MHz in these modes. + */ + if (host->clock < 100 * 1000 * 1000 || + !(ios.timing =3D=3D MMC_TIMING_MMC_HS200 || + ios.timing =3D=3D MMC_TIMING_UHS_SDR50 || + ios.timing =3D=3D MMC_TIMING_UHS_SDR104)) + return 0; + + if (mmc->caps2 & MMC_CAP2_NO_MMC) { + spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); + spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); + spacemit_sdhci_tx_tuning_prepare(host); + + dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=3D%d, delaycode=3D%d\n= ", + SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); + } + + spacemit_sdhci_prepare_tuning(host); + + for (i =3D SPACEMIT_RX_TUNE_DELAY_MIN; i <=3D SPACEMIT_RX_TUNE_DELAY_MAX;= i++) { + spacemit_sdhci_set_rx_delay(host, i); + ret =3D mmc_send_tuning(host->mmc, opcode, NULL); + + dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", + i, ret =3D=3D 0 ? "pass" : "fail"); + + if (ret =3D=3D 0) { + /* Test passed - extend current window */ + if (current_len =3D=3D 0) + current_start =3D i; + current_len++; + } else { + /* Test failed - check if current window is best so far */ + if (current_len > max_pass_len) { + max_pass_len =3D current_len; + max_pass_start =3D current_start; + } + current_len =3D 0; + } + } + + if (current_len > max_pass_len) { + max_pass_len =3D current_len; + max_pass_start =3D current_start; + } + + if (max_pass_len < 3) { + dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); + return -EIO; + } + + final_delay =3D max_pass_start + max_pass_len / 2; + spacemit_sdhci_set_rx_delay(host, final_delay); + ret =3D mmc_send_tuning(host->mmc, opcode, NULL); + if (ret) { + u8 retry_delays[] =3D { + max_pass_start + max_pass_len / 4, + max_pass_start + (3 * max_pass_len) / 4, + max_pass_start, + max_pass_start + max_pass_len - 1 + }; + int retry_count =3D ARRAY_SIZE(retry_delays); + + dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", + final_delay); + + for (i =3D 0; i < retry_count; i++) { + if (retry_delays[i] >=3D SPACEMIT_RX_TUNE_DELAY_MIN && + retry_delays[i] <=3D SPACEMIT_RX_TUNE_DELAY_MAX) { + spacemit_sdhci_set_rx_delay(host, retry_delays[i]); + ret =3D mmc_send_tuning(host->mmc, opcode, NULL); + if (!ret) { + final_delay =3D retry_delays[i]; + dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", + final_delay); + break; + } + } + } + + if (ret) { + dev_err(mmc_dev(mmc), "All retry attempts failed\n"); + return -EIO; + } + } + + dev_dbg(mmc_dev(host->mmc), + "Tuning successful: window %d-%d, using delay %d\n", + max_pass_start, max_pass_start + max_pass_len - 1, final_delay); + + return 0; +} + static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) { struct sdhci_host *host =3D mmc_priv(mmc); @@ -314,6 +485,7 @@ static const struct sdhci_ops spacemit_sdhci_ops =3D { .set_clock =3D spacemit_sdhci_set_clock, .set_uhs_signaling =3D spacemit_sdhci_set_uhs_signaling, .voltage_switch =3D spacemit_sdhci_voltage_switch, + .platform_execute_tuning =3D spacemit_sdhci_execute_tuning, }; =20 static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata =3D { --=20 2.53.0