From nobody Tue Apr 7 04:26:51 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4533E3A4F3F; Mon, 16 Mar 2026 15:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674765; cv=none; b=G0OyccA2QHP4Vcg9ahZZ6BeZEWguyotcBofbgBP63xcp+x8UdD+4YhLw82Mxyl+5kXYj4IfJU3Klc+smqssaO9j2Yj1b1ij1T5iy16jUyhAUiywy4Psq02jin3hHMg83j8iugyxdGdVHCyV3KNVv1GmoWHIVfoAMLmjkc6r9874= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674765; c=relaxed/simple; bh=9zkekABcAlg8YMMkj/L/dt3L6sYyji1eB7+IH2fyS2s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NexwXhkzy/1MCPunldL/0n2ZV+g/hCbvC1i2O8lRHa3nXhJtKE6kbdvWz7XskXxqxQp88Y5b+i9d8FTFYgUbX9lgmhnyA24vPfU17WgO4DXqkyv6X5lVpD5yHCy97A4RMYM7aw5qiqHtfi9PMqtL5xueZW1ibeuDdmi2knynrr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=2KYlx3jI; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="2KYlx3jI" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id CA62C4E40B37; Mon, 16 Mar 2026 15:26:02 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 9E77E5FC4A; Mon, 16 Mar 2026 15:26:02 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 59063103721F2; Mon, 16 Mar 2026 16:26:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674761; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=bMU1zdQY7oxfR3rDnGue/fO4nWAsw/nZQUBlMCuYV9E=; b=2KYlx3jIvnftdlBWCpB3QD8jZsD67BTlQl9myQzFomuSnz68bff+1166NlG9T8NlJdliVN 5DiW2RY41WjyL0KzAfZYJL+QOxQ9Wk2B7enQUCRq3O6OsDQA6FO94N+r25kfFFvhZiV4v6 X10m3XqLamqLNq/OGlqFgyAKAh/KSgYNFAA+1AyruLa3I1hcrp+DJG/tK/pdUTMQ9fML/D LHyUKjoKzSm5x65ba17A8La4/mC3OfOA4psfRCAp9xXAfn+9awRRHhLiW/4uCwd6P/HnVx hIRSlJQ6uKp6yJrzg9eUMXNvavW3hDZYUWU+gWgW/C8OouRxhvWXiHg1MuFtJA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:44 +0100 Subject: [PATCH v4 07/13] clk: eyeq: Skip post-divisor when computing PLL frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-7-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The output of the PLL is routed before the post-divisor so it should be ignored when computing the frequency of the PLL, functional change is implemented to reflect how the clock signal is wired internally. For the PLL of the EyeQ5, EyeQ6L, and EyeQ6H, this change has no impact as the post-divisor is either reported as disabled or set to 1. The PLL frequency is the same before and after the post-divisor. For the PLL in EyeQ6Lplus, however, the post-divisor is not 1, so it must be ignored to compute the correct frequency. Signed-off-by: Beno=C3=AEt Monin Acked-by: Stephen Boyd --- drivers/clk/clk-eyeq.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index b17f47fda1da..904d7d77d415 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -178,8 +178,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsi= gned long *mult, =20 *mult =3D FIELD_GET(PCSR0_INTIN, r0); *div =3D FIELD_GET(PCSR0_REF_DIV, r0); - if (r0 & PCSR0_FOUTPOSTDIV_EN) - *div *=3D FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0= ); =20 /* Fractional mode, in 2^20 (0x100000) parts. */ if (r0 & PCSR0_DSM_EN) { --=20 2.53.0