From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A29C39FCA9; Mon, 16 Mar 2026 15:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674754; cv=none; b=qUiimuTIRVyMpNuB255Eq+cP19wXiS+rLUcBQ07v0z1ksweq3G+zhlI/nCLpl2tR6xiEcow0puqwzjPR6yCWpe4IGgUcSrITL0W5zS+qAgqLemxzP50c9IpG6zGs7Aj9Xikn+Z4IFGYprhxrRir8f/iPl0cvU/uXx9DzbItwsec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674754; c=relaxed/simple; bh=0lSJAvm4Hn1Ils6DHNjWeGoR73lEO8Dc8PMjR4+fBqc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jWa1hm0B71P3YtpCmVe7yltDNqj37GVjKV9UGBayFsig1jbk4JztfRGbhq8evdPzphg2jvABO61j+RXOkZ/tFJgWkNj/Cerh674fpzW666wkiH8hipkmhWMyRY9HzjXmTg2ZQiDGoUfNSl+zFeJZWlMkTEgmjtLTbby7W1s1jU0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=f2TQfXi6; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="f2TQfXi6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 5A74C1A2E5B; Mon, 16 Mar 2026 15:25:52 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 235635FC4A; Mon, 16 Mar 2026 15:25:52 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CE3E2103721EB; Mon, 16 Mar 2026 16:25:49 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674751; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=YdDsgApApAV3cK0W79hVYmB4UC7l0NfHNOm1EgR/sOU=; b=f2TQfXi67nM66+ddhpigqhueijFX/zBaiSp1yLDY3jgJ6cyVoN9IgTUoWytDGJ2eDy2Tov ZeZd4ODA9vrkqB3iD8p8EBVY+2S5Fx4O2gYDvdSXt4bvWhcT2Wv3HIfcbswv/R2QJkd5N8 O9sEZAurdl5v/S1kJj1fGU2NGPQSjLZ82oWORtwQSg0b4TrwcGSFWrNJctM2OoBzXtXwMg Zs8gmmmbNnbQ3tngviIDItcvKQaoD+sgRTbupK8VfT7NPdbF1PTlsnour3etUtptWpopFL 47pRZRFqyRK/ntlMuulFqNbtdBdvUDqTiLP/Y5HxdKaNP1pym65V2yarW+q8JA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:38 +0100 Subject: [PATCH v4 01/13] dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-1-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add an entry to the mobileye bindings for the EyeQ6Lplus which is part of the EyeQ family of system-on-chip. Reviewed-by: Rob Herring (Arm) Signed-off-by: Beno=C3=AEt Monin --- Documentation/devicetree/bindings/mips/mobileye.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documen= tation/devicetree/bindings/mips/mobileye.yaml index d60744550e46..83abe268e96b 100644 --- a/Documentation/devicetree/bindings/mips/mobileye.yaml +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml @@ -31,6 +31,11 @@ properties: - enum: - mobileye,eyeq6h-epm6 - const: mobileye,eyeq6h + - description: Boards with Mobileye EyeQ6Lplus SoC + items: + - enum: + - mobileye,eyeq6lplus-epm6 + - const: mobileye,eyeq6lplus =20 additionalProperties: true =20 --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBEE63A1A28; Mon, 16 Mar 2026 15:25:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674757; cv=none; b=ON09xYjEqzHEz3deDszqpq7Xe1t5xuScrCWI11zsjzU2wJmMyqZFAjngs/MXLCYNdw0iCCA/motKMJKoMWHH7iIyPp4jVI7mVgD/UBkPNRG/oMmz4t788utw9DCcv+8VvB38wch0Mmn74h7+m07X+UO9EYh482S0DYMK7+VXFLY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674757; c=relaxed/simple; bh=oBOR980TwjJ2dJBFw8+3I1q6s5oxOQVha3EWu0SuaCA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kYLHwNzVEnlY1JgESnot0QtRWby1Rk3hL0ow7POxCmfp/nTTKeF5SmiRSMokyFYv+XqyoALKFUQJzzQYLeJuEa4lig2dfhKtueDHKhoxErPL42G89DmMDOXHjIqoGSUFZp9U92lZA5diHTdk9UnFKD7NfWiseNWfDZlBK1pM3c4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=SGscBu9M; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="SGscBu9M" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 38EAFC55052; Mon, 16 Mar 2026 15:26:18 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 969575FC4A; Mon, 16 Mar 2026 15:25:54 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 5D7CC103721CF; Mon, 16 Mar 2026 16:25:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674753; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=xbFb0N0mWFaPr9wcm17PmP2ipXvyfHX9OmBmbZQsT74=; b=SGscBu9MMZUwkNU0iPZ2bCoHdZ+KzW2fEilU+Rrm30mO8Slk5XKfxmfihCb+pq8wvyQ1CQ OpPK5D2Sy2NjIyy9z8CZRm36CKiXHTNuTOnlMDtfYoBNTE+V5SFt2+YFhYYdU/fDNhWVkJ /8KAv8Ol+AdevSaC+S3ox4PhZHRWjv9yJVSvttm8NP6V1w8cNKdWqWC66Rl5uGYO1g2KsL tWiwvnP5zSVW86mLh5h17ycGauNyX/s5XuIVKHXRlF9epXPCM/gsVPTIUVAZphTa9l0cNS aIUmyiWdf3XoEVen2dzqLLDXY5iiVMdCW4r47sFkTuUcqVNQ7ERcRn+3UMt4Zg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:39 +0100 Subject: [PATCH v4 02/13] dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-2-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides various functions for the controllers present in the SoC. The OLB produces 22 clocks derived from its input, which is connected to the main oscillator of the SoC. It provides reset signals via two reset domains. It also controls 32 pins to be either a GPIO or an alternate function. Reviewed-by: Rob Herring (Arm) Signed-off-by: Beno=C3=AEt Monin Acked-by: Stephen Boyd Reviewed-by: Linus Walleij --- .../soc/mobileye/mobileye,eyeq6lplus-olb.yaml | 208 +++++++++++++++++= ++++ .../dt-bindings/clock/mobileye,eyeq6lplus-clk.h | 37 ++++ 2 files changed, 245 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6l= plus-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eye= q6lplus-olb.yaml new file mode 100644 index 000000000000..8334876cf4e6 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-ol= b.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq6lplus-olb.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ6Lplus SoC system controller + +maintainers: + - Beno=C3=AEt Monin + - Gr=C3=A9gory Clement + - Th=C3=A9o Lebrun + - Vladimir Kondratiev + +description: + OLB ("Other Logic Block") is a hardware block grouping smaller blocks. + Clocks, resets, pinctrl are being handled from here. EyeQ6Lplus hosts + a single instance providing 22 clocks, two reset domains and one bank + of 32 pins. + +properties: + compatible: + items: + - const: mobileye,eyeq6lplus-olb + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + First cell is reset domain index. + Second cell is reset index inside that domain. + const: 2 + + '#clock-cells': + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + const: ref + +patternProperties: + '-pins?$': + type: object + description: Pin muxing configuration. + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + properties: + pins: true + function: + enum: [gpio, timer0, timer1, uart_ssi, spi0, uart0, timer2, timer3, + timer_ext0, spi1, timer_ext1, ext_ref_clk, mipi_ref_clk] + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + required: + - pins + - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + pins: + items: # PA0 - PA31 + pattern: '^(PA[1,2]?[0-9]|PA3[0,1])$' + - if: + properties: + function: + const: timer0 + then: + properties: + pins: + items: + enum: [PA0, PA1] + - if: + properties: + function: + const: timer1 + then: + properties: + pins: + items: + enum: [PA2, PA3] + - if: + properties: + function: + const: uart_ssi + then: + properties: + pins: + items: + enum: [PA4, PA5] + - if: + properties: + function: + const: spi0 + then: + properties: + pins: + items: + enum: [PA6, PA7, PA8, PA9, PA10] + - if: + properties: + function: + const: uart0 + then: + properties: + pins: + items: + enum: [PA11, PA12] + - if: + properties: + function: + const: timer2 + then: + properties: + pins: + items: + enum: [PA13, PA14] + - if: + properties: + function: + const: timer3 + then: + properties: + pins: + items: + enum: [PA15, PA16] + - if: + properties: + function: + const: timer_ext0 + then: + properties: + pins: + items: + enum: [PA17, PA18, PA19, PA20] + - if: + properties: + function: + const: spi1 + then: + properties: + pins: + items: + enum: [PA21, PA22, PA23, PA24, PA25] + - if: + properties: + function: + const: timer_ext1 + then: + properties: + pins: + items: + enum: [PA26, PA27, PA28, PA29] + - if: + properties: + function: + const: ext_ref_clk + then: + properties: + pins: + items: + enum: [PA30] + - if: + properties: + function: + const: mipi_ref_clk + then: + properties: + pins: + items: + enum: [PA31] + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + - '#reset-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + system-controller@e8400000 { + compatible =3D "mobileye,eyeq6lplus-olb", "syscon"; + reg =3D <0 0xe8400000 0x0 0x80000>; + #reset-cells =3D <2>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + }; diff --git a/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h b/include/= dt-bindings/clock/mobileye,eyeq6lplus-clk.h new file mode 100644 index 000000000000..20d84ee24ad5 --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H + +#define EQ6LPC_PLL_CPU 0 +#define EQ6LPC_PLL_DDR 1 +#define EQ6LPC_PLL_PER 2 +#define EQ6LPC_PLL_VDI 3 +#define EQ6LPC_PLL_ACC 4 + +#define EQ6LPC_CPU_OCC 5 + +#define EQ6LPC_ACC_VDI 6 +#define EQ6LPC_ACC_OCC 7 +#define EQ6LPC_ACC_FCMU 8 + +#define EQ6LPC_DDR_OCC 9 + +#define EQ6LPC_PER_OCC 10 +#define EQ6LPC_PER_I2C_SER 11 +#define EQ6LPC_PER_PCLK 12 +#define EQ6LPC_PER_TSU 13 +#define EQ6LPC_PER_OSPI 14 +#define EQ6LPC_PER_GPIO 15 +#define EQ6LPC_PER_TIMER 16 +#define EQ6LPC_PER_I2C 17 +#define EQ6LPC_PER_UART 18 +#define EQ6LPC_PER_SPI 19 +#define EQ6LPC_PER_PERIPH 20 + +#define EQ6LPC_VDI_OCC 21 + +#endif --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DF103A1E6A; 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bh=sZVsM7cOjX5aDJbulYzzyMObqmeiRrsk50vVV83iK4c=; b=FE8z8+832N7U5ZkENIVRSq42j/XkI9fAi+pZd0z39G/dFCmrV3f5HutJqmsDA2e5JN4vCT ewj6Xjn/pyO7hwKyHBoh8F5cfv1aoJoDvBIGSEsB5IHi1hM+bpnaLXyTHiWy70RK0F+VXQ uTICy4HoaBRwZ0h9r01a2HRZFa8JX+e9JYoIREZVX+Rh3+4S3EcRUTkKcSY62Ydi7QaTNp 88soEfw7W7VDidk5I+2KBP7jfROh+Dv3WTtB6PA0QmBS7MO5lr9NoMeyMtwwLsa4Y/PZgw icEj8+l0AZAniesyKthd0r+uzeBpeQVF96DnKgsJwBk028aTDrbwlbtqElD7Sg== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:40 +0100 Subject: [PATCH v4 03/13] MIPS: Add Mobileye EyeQ6Lplus support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-3-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the EyeQ6Lplus to the group of choices for Mobileye SoC and set the kernel load address specific to this SoC. Signed-off-by: Beno=C3=AEt Monin --- arch/mips/mobileye/Kconfig | 3 +++ arch/mips/mobileye/Platform | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/mips/mobileye/Kconfig b/arch/mips/mobileye/Kconfig index f9abb2d6e178..8a4868d2e28f 100644 --- a/arch/mips/mobileye/Kconfig +++ b/arch/mips/mobileye/Kconfig @@ -12,6 +12,9 @@ choice =20 config MACH_EYEQ6H bool "Mobileye EyeQ6H SoC" + + config MACH_EYEQ6LPLUS + bool "Mobileye EyeQ6Lplus SoC" endchoice =20 config FIT_IMAGE_FDT_EPM5 diff --git a/arch/mips/mobileye/Platform b/arch/mips/mobileye/Platform index 69f775bbbb1e..93b533492b58 100644 --- a/arch/mips/mobileye/Platform +++ b/arch/mips/mobileye/Platform @@ -10,6 +10,7 @@ =20 load-$(CONFIG_MACH_EYEQ5) =3D 0xa800000808000000 load-$(CONFIG_MACH_EYEQ6H) =3D 0xa800000100800000 +load-$(CONFIG_MACH_EYEQ6LPLUS) =3D 0xa800000108800000 all-$(CONFIG_MACH_EYEQ5) +=3D vmlinux.gz.itb =20 its-y :=3D vmlinux.its.S --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 652383A0B29; Mon, 16 Mar 2026 15:25:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674761; cv=none; b=a7hopQwGwpWKvXmqwmkx0nFsMRPJfUiuWaBQku+5Lam9pW12HNCg1gZPb4qOzRX40aqR3Vs5Mu1xdcPxo0dsDGxV5aQDKWuDhAzT2m59gCGUj1G0gwy+Vdl4JMrxLHkrj42C2DGEnGjexF/4Gs+RlGwI6Rp636hU6JhOTrxHTFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674761; c=relaxed/simple; bh=d7xzJ/Zdl4XUqWXeHp3gMAa9bQJQznI63W9v0R6XiC8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bfUZ24Nvc1kUIZRe8MbYwAX9Lx7FEirdnpX0OqSb5FZqC1w99N3nr+O1z02ePGk3s+ZMiMJ7RqNAHVaO+kF7gXjxaU95DtRPyALCzlJ7jA1gwNXzU4RT9E0MBklwEc4/8Y6NPbil9BjndrXYLOdbe1w2r9pYfx56IEUadhxuOIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=QIfFkmA1; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="QIfFkmA1" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id E10EB1A2E5B; Mon, 16 Mar 2026 15:25:57 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B7D4C5FC4A; Mon, 16 Mar 2026 15:25:57 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id ED6B8103721EB; Mon, 16 Mar 2026 16:25:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674756; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=qhsMzWBsOebiFYIKgHn4CikkhxD3WYEUDe0coVF4nXQ=; b=QIfFkmA1KhSYmzttxzn9uMG2jDmhnXu6X3tvtNN7UZhRkyy2WQmxfHcesvsO116AOsmBRP 7s/UrZTUvdCaQpGhSlasXvDZNWpB9Ew6z/w25VkFqSt9ONsGsAC9URgIIWWbS620Hdlc6L DJeJ4f/gGwaMbl2ddKKRycR/sDP/afjgWs1h8Kbg7N4n6pkuvb2VBYKVZupHlhGBTKnXdC EdGmM1Zs+tAuC4cyQrJbxcpMTP16uSxjkjO5BqOOWqyn+z6v281EVp2VOExequTP36ekeW D13NDxwQD14YzeYTyaehaWXcR0vqXP/lP1t8lQtputB8RSO+Gmc6i2u40XGFFA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:41 +0100 Subject: [PATCH v4 04/13] reset: eyeq: Add Mobileye EyeQ6Lplus OLB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-4-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Declare the two reset domains found in the EyeQ6Lplus OLB and add them to the data matched by 'mobileye,eyeq6lplus-olb' compatible. Those reset domains are identical to those present in the EyeQ5 OLB, so no changes are needed to support them. Also select reset-eyeq for all EYEQ SoCs instead of listing each one individually, as it is needed by all Mobileye EyeQ SoC. Reviewed-by: Philipp Zabel Signed-off-by: Beno=C3=AEt Monin --- drivers/reset/Kconfig | 4 ++-- drivers/reset/reset-eyeq.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 7ce151f6a7e4..67057248c810 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -85,9 +85,9 @@ config RESET_EIC7700 =20 config RESET_EYEQ bool "Mobileye EyeQ reset controller" - depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST + depends on EYEQ || COMPILE_TEST select AUXILIARY_BUS - default MACH_EYEQ5 || MACH_EYEQ6H + default EYEQ help This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L and EyeQ6H SoCs. diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c index 8018fa895427..1a3857983897 100644 --- a/drivers/reset/reset-eyeq.c +++ b/drivers/reset/reset-eyeq.c @@ -49,6 +49,18 @@ * 8. MPC0 9. MPC1 10. MPC2 11. MPC3 * 12. MPC4 * + * Known resets in EyeQ6Lplus domain 0 (type EQR_EYEQ5_PCIE): + * 0. SPI0 1. SPI1 2. UART0 3. I2C0 + * 4. I2C1 5. TIMER0 6. TIMER1 7. TIMER2 + * 8. TIMER3 9. WD0 10. WD1 11. EXT0 + * 12. EXT1 13. GPIO + * + * Known resets in EyeQ6Lplus domain 1 (type EQR_EYEQ5_ACRP): + * 0. VMP0 1. VMP1 2. VMP2 3. VMP3 + * 4. PMA0 5. PMA1 6. PMAC0 7. PMAC1 + * 8. MPC0 9. MPC1 10. MPC2 11. MPC3 + * 12. MPC4 + * * Known resets in EyeQ6H west/east (type EQR_EYEQ6H_SARCR): * 0. CAN 1. SPI0 2. SPI1 3. UART0 * 4. UART1 5. I2C0 6. I2C1 7. -hole- @@ -501,6 +513,24 @@ static const struct eqr_match_data eqr_eyeq6l_data =3D= { .domains =3D eqr_eyeq6l_domains, }; =20 +static const struct eqr_domain_descriptor eqr_eyeq6lplus_domains[] =3D { + { + .type =3D EQR_EYEQ5_PCIE, + .valid_mask =3D 0x3FFF, + .offset =3D 0x004, + }, + { + .type =3D EQR_EYEQ5_ACRP, + .valid_mask =3D 0x00FF, + .offset =3D 0x200, + }, +}; + +static const struct eqr_match_data eqr_eyeq6lplus_data =3D { + .domain_count =3D ARRAY_SIZE(eqr_eyeq6lplus_domains), + .domains =3D eqr_eyeq6lplus_domains, +}; + /* West and east OLBs each have an instance. */ static const struct eqr_domain_descriptor eqr_eyeq6h_we_domains[] =3D { { @@ -535,6 +565,7 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = =3D { static const struct of_device_id eqr_match_table[] =3D { { .compatible =3D "mobileye,eyeq5-olb", .data =3D &eqr_eyeq5_data }, { .compatible =3D "mobileye,eyeq6l-olb", .data =3D &eqr_eyeq6l_data }, + { .compatible =3D "mobileye,eyeq6lplus-olb", .data =3D &eqr_eyeq6lplus_da= ta }, { .compatible =3D "mobileye,eyeq6h-west-olb", .data =3D &eqr_eyeq6h_we_da= ta }, { .compatible =3D "mobileye,eyeq6h-east-olb", .data =3D &eqr_eyeq6h_we_da= ta }, { .compatible =3D "mobileye,eyeq6h-acc-olb", .data =3D &eqr_eyeq6h_acc_da= ta }, --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF96F3A4535; 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bh=KM7ClKbciDhEYUX4cUUl8kgfH4hJG6/U+Nkx/q2cQqs=; b=Q0ssCtQhDJ58NfXVH2DvJyxiYmcRenqDWPD3VJsJ3FB9I+i8M63v/bprU8yKaxqh3k5gqS 87gBVwTfi3dVcFIzJ+BZFDW3Ujiu7Vot7jSE3OsQE+b3uLrmNzKPm6SabUd6f+bqX+hgV0 xEgog/rxJr+eRDBtgAvgcN3GbSIvvqhMuN6bDDA0RLB5FROBCdC9PUX15h0AqCuhcZX0kb snXvlr2IIm6vkzSbX+M7OS/fcwgoW/iI2hJo/+1QyjvizzMciUlgVdMFAxBxpEyu3IAfk7 z+oe8V96jQ+DUsWjaHfPF1WHVdco9+OpX79jeA1ZI5cBjys+js+EAIl8ug3mOQ== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:42 +0100 Subject: [PATCH v4 05/13] pinctrl: eyeq5: Use match data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-5-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Instead of using the pin descriptions, pin functions and register offsets of the EyeQ5 directly, access those via a pointer to a newly introduced struct eq5p_match_data. This structure contains, in addition to the pin descriptions and pin functions, an array of pin banks. Each bank holds the number of pins and the register offsets. All functions accessing a pin now use a pointer to a bank structure and an offset inside that bank. The conversion from a pin number to a bank and an offset is done in the new function eq5p_pin_to_bank_offset(), which replace eq5p_pin_to_bank() and eq5p_pin_to_offset(). All the data related to the EyeQ5 is declared with the eq5p_eyeq5_ prefix to distinguish it from the common code. During the probe, we use the parent OF node to get the match data. We cannot directly use an OF node since pinctrl-eyeq5 is an auxiliary device of clk-eyeq. Signed-off-by: Beno=C3=AEt Monin Reviewed-by: Linus Walleij --- drivers/pinctrl/pinctrl-eyeq5.c | 342 +++++++++++++++++++++++++-----------= ---- 1 file changed, 213 insertions(+), 129 deletions(-) diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq= 5.c index 5f6af934a516..c780af09cde9 100644 --- a/drivers/pinctrl/pinctrl-eyeq5.c +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -38,18 +39,6 @@ #include "core.h" #include "pinctrl-utils.h" =20 -struct eq5p_pinctrl { - struct pinctrl_desc desc; - void __iomem *base; -}; - -enum eq5p_bank { - EQ5P_BANK_A, - EQ5P_BANK_B, - - EQ5P_BANK_COUNT, -}; - enum eq5p_regs { EQ5P_PD, EQ5P_PU, @@ -60,9 +49,24 @@ enum eq5p_regs { EQ5P_REG_COUNT, }; =20 -static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] =3D { - [EQ5P_BANK_A] =3D {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0}, - [EQ5P_BANK_B] =3D {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4}, +struct eq5p_bank { + const unsigned int npins; + const unsigned int regs[EQ5P_REG_COUNT]; +}; + +struct eq5p_match_data { + const unsigned int npins; + const unsigned int nfunctions; + const unsigned int nbanks; + const struct pinctrl_pin_desc *pins; + const struct pinfunction *functions; + const struct eq5p_bank *banks; +}; + +struct eq5p_pinctrl { + struct pinctrl_desc desc; + void __iomem *base; + const struct eq5p_match_data *data; }; =20 /* @@ -70,10 +74,18 @@ static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ= 5P_REG_COUNT] =3D { */ #define EQ5P_DS_MASK GENMASK(1, 0) =20 +/* + * The GPIO function is always the first function + */ +#define EQ5P_GPIO_FUNC_SELECTOR 0 + +/* Helper to declare pinfunction */ +#define EQ5P_PINFUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, A= RRAY_SIZE(groups)) + /* * Comments to the right of each pin are the "signal name" in the datashee= t. */ -static const struct pinctrl_pin_desc eq5p_pins[] =3D { +static const struct pinctrl_pin_desc eq5p_eyeq5_pins[] =3D { /* Bank A */ PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */ PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */ @@ -105,35 +117,35 @@ static const struct pinctrl_pin_desc eq5p_pins[] =3D { PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */ PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */ =20 -#define EQ5P_PIN_OFFSET_BANK_B 29 +#define EQ5P_EYEQ5_PIN_OFFSET_BANK_B 29 =20 /* Bank B */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1= */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2= */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP= 1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP= 2 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */ - PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC = */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC = */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_= INCAP1 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_= INCAP2 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_= OUTCMP1 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_= OUTCMP2 */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 = */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 = */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 = */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 = */ + PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */ }; =20 -static const char * const gpio_groups[] =3D { +static const char * const eq5p_eyeq5_gpio_groups[] =3D { /* Bank A */ "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", @@ -147,70 +159,90 @@ static const char * const gpio_groups[] =3D { }; =20 /* Groups of functions on bank A */ -static const char * const timer0_groups[] =3D { "PA0", "PA1" }; -static const char * const timer1_groups[] =3D { "PA2", "PA3" }; -static const char * const timer2_groups[] =3D { "PA4", "PA5" }; -static const char * const timer5_groups[] =3D { "PA6", "PA7", "PA8", "PA9"= }; -static const char * const uart0_groups[] =3D { "PA10", "PA11" }; -static const char * const uart1_groups[] =3D { "PA12", "PA13" }; -static const char * const can0_groups[] =3D { "PA14", "PA15" }; -static const char * const can1_groups[] =3D { "PA16", "PA17" }; -static const char * const spi0_groups[] =3D { "PA18", "PA19", "PA20", "PA2= 1", "PA22" }; -static const char * const spi1_groups[] =3D { "PA23", "PA24", "PA25", "PA2= 6", "PA27" }; -static const char * const refclk0_groups[] =3D { "PA28" }; +static const char * const eq5p_eyeq5_timer0_groups[] =3D { "PA0", "PA1" }; +static const char * const eq5p_eyeq5_timer1_groups[] =3D { "PA2", "PA3" }; +static const char * const eq5p_eyeq5_timer2_groups[] =3D { "PA4", "PA5" }; +static const char * const eq5p_eyeq5_timer5_groups[] =3D { "PA6", "PA7", "= PA8", "PA9" }; +static const char * const eq5p_eyeq5_uart0_groups[] =3D { "PA10", "PA11" }; +static const char * const eq5p_eyeq5_uart1_groups[] =3D { "PA12", "PA13" }; +static const char * const eq5p_eyeq5_can0_groups[] =3D { "PA14", "PA15" }; +static const char * const eq5p_eyeq5_can1_groups[] =3D { "PA16", "PA17" }; +static const char * const eq5p_eyeq5_spi0_groups[] =3D { "PA18", "PA19", "= PA20", "PA21", "PA22" }; +static const char * const eq5p_eyeq5_spi1_groups[] =3D { "PA23", "PA24", "= PA25", "PA26", "PA27" }; +static const char * const eq5p_eyeq5_refclk0_groups[] =3D { "PA28" }; =20 /* Groups of functions on bank B */ -static const char * const timer3_groups[] =3D { "PB0", "PB1" }; -static const char * const timer4_groups[] =3D { "PB2", "PB3" }; -static const char * const timer6_groups[] =3D { "PB4", "PB5", "PB6", "PB7"= }; -static const char * const uart2_groups[] =3D { "PB8", "PB9" }; -static const char * const can2_groups[] =3D { "PB10", "PB11" }; -static const char * const spi2_groups[] =3D { "PB12", "PB13", "PB14", "PB1= 5", "PB16" }; -static const char * const spi3_groups[] =3D { "PB17", "PB18", "PB19", "PB2= 0", "PB21" }; -static const char * const mclk0_groups[] =3D { "PB22" }; +static const char * const eq5p_eyeq5_timer3_groups[] =3D { "PB0", "PB1" }; +static const char * const eq5p_eyeq5_timer4_groups[] =3D { "PB2", "PB3" }; +static const char * const eq5p_eyeq5_timer6_groups[] =3D { "PB4", "PB5", "= PB6", "PB7" }; +static const char * const eq5p_eyeq5_uart2_groups[] =3D { "PB8", "PB9" }; +static const char * const eq5p_eyeq5_can2_groups[] =3D { "PB10", "PB11" }; +static const char * const eq5p_eyeq5_spi2_groups[] =3D { "PB12", "PB13", "= PB14", "PB15", "PB16" }; +static const char * const eq5p_eyeq5_spi3_groups[] =3D { "PB17", "PB18", "= PB19", "PB20", "PB21" }; +static const char * const eq5p_eyeq5_mclk0_groups[] =3D { "PB22" }; =20 -static const struct pinfunction eq5p_functions[] =3D { - /* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */ - PINCTRL_PINFUNCTION("gpio", gpio_groups, ARRAY_SIZE(gpio_groups)), -#define GPIO_FUNC_SELECTOR 0 +static const struct pinfunction eq5p_eyeq5_functions[] =3D { + /* GPIO having a fixed index is depended upon, see EQ5P_GPIO_FUNC_SELECTO= R. */ + EQ5P_PINFUNCTION("gpio", eq5p_eyeq5_gpio_groups), =20 /* Bank A functions */ - PINCTRL_PINFUNCTION("timer0", timer0_groups, ARRAY_SIZE(timer0_groups)), - PINCTRL_PINFUNCTION("timer1", timer1_groups, ARRAY_SIZE(timer1_groups)), - PINCTRL_PINFUNCTION("timer2", timer2_groups, ARRAY_SIZE(timer2_groups)), - PINCTRL_PINFUNCTION("timer5", timer5_groups, ARRAY_SIZE(timer5_groups)), - PINCTRL_PINFUNCTION("uart0", uart0_groups, ARRAY_SIZE(uart0_groups)), - PINCTRL_PINFUNCTION("uart1", uart1_groups, ARRAY_SIZE(uart1_groups)), - PINCTRL_PINFUNCTION("can0", can0_groups, ARRAY_SIZE(can0_groups)), - PINCTRL_PINFUNCTION("can1", can1_groups, ARRAY_SIZE(can1_groups)), - PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)), - PINCTRL_PINFUNCTION("spi1", spi1_groups, ARRAY_SIZE(spi1_groups)), - PINCTRL_PINFUNCTION("refclk0", refclk0_groups, ARRAY_SIZE(refclk0_groups)= ), + EQ5P_PINFUNCTION("timer0", eq5p_eyeq5_timer0_groups), + EQ5P_PINFUNCTION("timer1", eq5p_eyeq5_timer1_groups), + EQ5P_PINFUNCTION("timer2", eq5p_eyeq5_timer2_groups), + EQ5P_PINFUNCTION("timer5", eq5p_eyeq5_timer5_groups), + EQ5P_PINFUNCTION("uart0", eq5p_eyeq5_uart0_groups), + EQ5P_PINFUNCTION("uart1", eq5p_eyeq5_uart1_groups), + EQ5P_PINFUNCTION("can0", eq5p_eyeq5_can0_groups), + EQ5P_PINFUNCTION("can1", eq5p_eyeq5_can1_groups), + EQ5P_PINFUNCTION("spi0", eq5p_eyeq5_spi0_groups), + EQ5P_PINFUNCTION("spi1", eq5p_eyeq5_spi1_groups), + EQ5P_PINFUNCTION("refclk0", eq5p_eyeq5_refclk0_groups), =20 /* Bank B functions */ - PINCTRL_PINFUNCTION("timer3", timer3_groups, ARRAY_SIZE(timer3_groups)), - PINCTRL_PINFUNCTION("timer4", timer4_groups, ARRAY_SIZE(timer4_groups)), - PINCTRL_PINFUNCTION("timer6", timer6_groups, ARRAY_SIZE(timer6_groups)), - PINCTRL_PINFUNCTION("uart2", uart2_groups, ARRAY_SIZE(uart2_groups)), - PINCTRL_PINFUNCTION("can2", can2_groups, ARRAY_SIZE(can2_groups)), - PINCTRL_PINFUNCTION("spi2", spi2_groups, ARRAY_SIZE(spi2_groups)), - PINCTRL_PINFUNCTION("spi3", spi3_groups, ARRAY_SIZE(spi3_groups)), - PINCTRL_PINFUNCTION("mclk0", mclk0_groups, ARRAY_SIZE(mclk0_groups)), + EQ5P_PINFUNCTION("timer3", eq5p_eyeq5_timer3_groups), + EQ5P_PINFUNCTION("timer4", eq5p_eyeq5_timer4_groups), + EQ5P_PINFUNCTION("timer6", eq5p_eyeq5_timer6_groups), + EQ5P_PINFUNCTION("uart2", eq5p_eyeq5_uart2_groups), + EQ5P_PINFUNCTION("can2", eq5p_eyeq5_can2_groups), + EQ5P_PINFUNCTION("spi2", eq5p_eyeq5_spi2_groups), + EQ5P_PINFUNCTION("spi3", eq5p_eyeq5_spi3_groups), + EQ5P_PINFUNCTION("mclk0", eq5p_eyeq5_mclk0_groups), +}; + +static const struct eq5p_bank eq5p_eyeq5_banks[] =3D { + { + .npins =3D EQ5P_EYEQ5_PIN_OFFSET_BANK_B, + .regs =3D {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0}, + }, + { + .npins =3D ARRAY_SIZE(eq5p_eyeq5_pins) - EQ5P_EYEQ5_PIN_OFFSET_BANK_B, + .regs =3D {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4}, + }, +}; + +static const struct eq5p_match_data eq5p_eyeq5_data =3D { + .npins =3D ARRAY_SIZE(eq5p_eyeq5_pins), + .nfunctions =3D ARRAY_SIZE(eq5p_eyeq5_functions), + .nbanks =3D ARRAY_SIZE(eq5p_eyeq5_banks), + .pins =3D eq5p_eyeq5_pins, + .functions =3D eq5p_eyeq5_functions, + .banks =3D eq5p_eyeq5_banks, }; =20 static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl, - enum eq5p_bank bank, enum eq5p_regs reg, - u32 mask, u32 val) + const struct eq5p_bank *bank, + enum eq5p_regs reg, u32 mask, u32 val) { - void __iomem *ptr =3D pctrl->base + eq5p_regs[bank][reg]; + void __iomem *ptr =3D pctrl->base + bank->regs[reg]; =20 writel((readl(ptr) & ~mask) | (val & mask), ptr); } =20 static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl, - enum eq5p_bank bank, enum eq5p_regs reg, int offset) + const struct eq5p_bank *bank, + enum eq5p_regs reg, int offset) { - u32 val =3D readl(pctrl->base + eq5p_regs[bank][reg]); + u32 val =3D readl(pctrl->base + bank->regs[reg]); =20 if (WARN_ON(offset > 31)) return false; @@ -218,25 +250,29 @@ static bool eq5p_test_bit(const struct eq5p_pinctrl *= pctrl, return (val & BIT(offset)) !=3D 0; } =20 -static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin) +static int eq5p_pin_to_bank_offset(const struct eq5p_pinctrl *pctrl, unsig= ned int pin, + const struct eq5p_bank **bank, unsigned int *offset) { - if (pin < EQ5P_PIN_OFFSET_BANK_B) - return EQ5P_BANK_A; - else - return EQ5P_BANK_B; -} + for (unsigned int i =3D 0; i < pctrl->data->nbanks; i++) { + const struct eq5p_bank *_bank =3D &pctrl->data->banks[i]; + unsigned int npins =3D _bank->npins; =20 -static unsigned int eq5p_pin_to_offset(unsigned int pin) -{ - if (pin < EQ5P_PIN_OFFSET_BANK_B) - return pin; - else - return pin - EQ5P_PIN_OFFSET_BANK_B; + if (pin < npins) { + *bank =3D _bank; + *offset =3D pin; + return 0; + } + pin -=3D npins; + } + + return -EINVAL; } =20 static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) { - return ARRAY_SIZE(eq5p_pins); + struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->npins; } =20 static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev, @@ -260,10 +296,15 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctld= ev, unsigned int pin, { enum pin_config_param param =3D pinconf_to_config_param(*config); struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); - unsigned int offset =3D eq5p_pin_to_offset(pin); - enum eq5p_bank bank =3D eq5p_pin_to_bank(pin); + const struct eq5p_bank *bank; + unsigned int offset; u32 val_ds, arg; bool pd, pu; + int ret; + + ret =3D eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; =20 pd =3D eq5p_test_bit(pctrl, bank, EQ5P_PD, offset); pu =3D eq5p_test_bit(pctrl, bank, EQ5P_PU, offset); @@ -281,10 +322,10 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctld= ev, unsigned int pin, case PIN_CONFIG_DRIVE_STRENGTH: offset *=3D 2; /* two bits per pin */ if (offset >=3D 32) { - val_ds =3D readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]); + val_ds =3D readl(pctrl->base + bank->regs[EQ5P_DS_HIGH]); offset -=3D 32; } else { - val_ds =3D readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]); + val_ds =3D readl(pctrl->base + bank->regs[EQ5P_DS_LOW]); } arg =3D (val_ds >> offset) & EQ5P_DS_MASK; break; @@ -302,30 +343,35 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_= dev *pctldev, { struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const char *pin_name =3D pctrl->desc.pins[pin].name; - unsigned int offset =3D eq5p_pin_to_offset(pin); - enum eq5p_bank bank =3D eq5p_pin_to_bank(pin); + const struct eq5p_bank *bank; const char *func_name, *bias; unsigned long ds_config; + unsigned int offset; u32 drive_strength; bool pd, pu; int i, j; =20 + if (eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset)) { + seq_puts(s, "unknown pin"); + return; + } + /* * First, let's get the function name. All pins have only two functions: * GPIO (IOCR =3D=3D 0) and something else (IOCR =3D=3D 1). */ if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) { func_name =3D NULL; - for (i =3D 0; i < ARRAY_SIZE(eq5p_functions); i++) { - if (i =3D=3D GPIO_FUNC_SELECTOR) + for (i =3D 0; i < pctrl->data->nfunctions; i++) { + if (i =3D=3D EQ5P_GPIO_FUNC_SELECTOR) continue; =20 - for (j =3D 0; j < eq5p_functions[i].ngroups; j++) { + for (j =3D 0; j < pctrl->data->functions[i].ngroups; j++) { /* Groups and pins are the same thing for us. */ - const char *x =3D eq5p_functions[i].groups[j]; + const char *x =3D pctrl->data->functions[i].groups[j]; =20 if (strcmp(x, pin_name) =3D=3D 0) { - func_name =3D eq5p_functions[i].name; + func_name =3D pctrl->data->functions[i].name; break; } } @@ -341,7 +387,7 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_de= v *pctldev, if (!func_name) func_name =3D "unknown"; } else { - func_name =3D eq5p_functions[GPIO_FUNC_SELECTOR].name; + func_name =3D pctrl->data->functions[EQ5P_GPIO_FUNC_SELECTOR].name; } =20 /* Second, we retrieve the bias. */ @@ -376,13 +422,17 @@ static const struct pinctrl_ops eq5p_pinctrl_ops =3D { =20 static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev) { - return ARRAY_SIZE(eq5p_functions); + struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->nfunctions; } =20 static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctld= ev, unsigned int selector) { - return eq5p_functions[selector].name; + struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->functions[selector].name; } =20 static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev, @@ -390,8 +440,10 @@ static int eq5p_pinmux_get_function_groups(struct pinc= trl_dev *pctldev, const char * const **groups, unsigned int *num_groups) { - *groups =3D eq5p_functions[selector].groups; - *num_groups =3D eq5p_functions[selector].ngroups; + struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + *groups =3D pctrl->data->functions[selector].groups; + *num_groups =3D pctrl->data->functions[selector].ngroups; return 0; } =20 @@ -399,12 +451,17 @@ static int eq5p_pinmux_set_mux(struct pinctrl_dev *pc= tldev, unsigned int func_selector, unsigned int pin) { struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); - const char *func_name =3D eq5p_functions[func_selector].name; + const char *func_name =3D pctrl->data->functions[func_selector].name; const char *group_name =3D pctldev->desc->pins[pin].name; - bool is_gpio =3D func_selector =3D=3D GPIO_FUNC_SELECTOR; - unsigned int offset =3D eq5p_pin_to_offset(pin); - enum eq5p_bank bank =3D eq5p_pin_to_bank(pin); + bool is_gpio =3D func_selector =3D=3D EQ5P_GPIO_FUNC_SELECTOR; + const struct eq5p_bank *bank; + unsigned int offset; u32 mask, val; + int ret; + + ret =3D eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; =20 dev_dbg(pctldev->dev, "func=3D%s group=3D%s\n", func_name, group_name); =20 @@ -419,7 +476,7 @@ static int eq5p_pinmux_gpio_request_enable(struct pinct= rl_dev *pctldev, unsigned int pin) { /* Pin numbers and group selectors are the same thing in our case. */ - return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin); + return eq5p_pinmux_set_mux(pctldev, EQ5P_GPIO_FUNC_SELECTOR, pin); } =20 static const struct pinmux_ops eq5p_pinmux_ops =3D { @@ -435,10 +492,15 @@ static int eq5p_pinconf_set_drive_strength(struct pin= ctrl_dev *pctldev, unsigned int pin, u32 arg) { struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); - unsigned int offset =3D eq5p_pin_to_offset(pin); - enum eq5p_bank bank =3D eq5p_pin_to_bank(pin); + const struct eq5p_bank *bank; + unsigned int offset; unsigned int reg; u32 mask, val; + int ret; + + ret =3D eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; =20 if (arg & ~EQ5P_DS_MASK) { dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg); @@ -465,12 +527,18 @@ static int eq5p_pinconf_set(struct pinctrl_dev *pctld= ev, unsigned int pin, { struct eq5p_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); const char *pin_name =3D pctldev->desc->pins[pin].name; - unsigned int offset =3D eq5p_pin_to_offset(pin); - enum eq5p_bank bank =3D eq5p_pin_to_bank(pin); struct device *dev =3D pctldev->dev; - u32 val =3D BIT(offset); + const struct eq5p_bank *bank; + unsigned int offset; unsigned int i; + u32 val; + int ret; =20 + ret =3D eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset); + if (ret) + return ret; + + val =3D BIT(offset); for (i =3D 0; i < num_configs; i++) { enum pin_config_param param =3D pinconf_to_config_param(configs[i]); u32 arg =3D pinconf_to_config_argument(configs[i]); @@ -533,19 +601,26 @@ static const struct pinconf_ops eq5p_pinconf_ops =3D { static int eq5p_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) { + const struct of_device_id *match; struct device *dev =3D &adev->dev; struct pinctrl_dev *pctldev; struct eq5p_pinctrl *pctrl; int ret; =20 + /* Get match data based on parent OF node set in clk-eyeq */ + match =3D of_match_node(dev->driver->of_match_table, dev->of_node); + if (!match || !match->data) + return -ENODEV; + pctrl =3D devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; =20 pctrl->base =3D (void __iomem *)dev_get_platdata(dev); + pctrl->data =3D match->data; pctrl->desc.name =3D dev_name(dev); - pctrl->desc.pins =3D eq5p_pins; - pctrl->desc.npins =3D ARRAY_SIZE(eq5p_pins); + pctrl->desc.pins =3D pctrl->data->pins; + pctrl->desc.npins =3D pctrl->data->npins; pctrl->desc.pctlops =3D &eq5p_pinctrl_ops; pctrl->desc.pmxops =3D &eq5p_pinmux_ops; pctrl->desc.confops =3D &eq5p_pinconf_ops; @@ -562,6 +637,12 @@ static int eq5p_probe(struct auxiliary_device *adev, return 0; } =20 +static const struct of_device_id eq5p_match_table[] =3D { + { .compatible =3D "mobileye,eyeq5-olb", .data =3D &eq5p_eyeq5_data }, + {} +}; +MODULE_DEVICE_TABLE(of, eq5p_match_table); + static const struct auxiliary_device_id eq5p_id_table[] =3D { { .name =3D "clk_eyeq.pinctrl" }, {} @@ -571,5 +652,8 @@ MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table); static struct auxiliary_driver eq5p_driver =3D { .probe =3D eq5p_probe, .id_table =3D eq5p_id_table, + .driver =3D { + .of_match_table =3D eq5p_match_table, + } }; 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Mon, 16 Mar 2026 16:25:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674760; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=8irxtQmFAKyzzxyCAyZaG+kfIE9cyeuAz9+GABROzAU=; b=hZ6Lp3xcB8UvHKIQGIilmVCGxY1o5HZ++5toLx9+5QTGlCelXSvjWBRlaZV5yETR1LEU+n pcoBMo7lx/KKmsNEzskPJY3XyB86DsgnB/QSVcyiu7102f9DiFUgqBO0yBein1ia7ObvBz MKMZIUmPJhzISyca7DTdtTWAkJsTHXV40/6DeeFrolzwr7XzcMtJStFCY/fH5SMRz7pT5I EGT+gXzYwT5tkc8TD5Z5NCzEuvIF3mGBIjKzg6qz9HI3lSOHhkHgB4kD96WnqCMfjeRdfa mU3BwVICNHdZc78EwEPLo26aXRwwY+843wKEyCcj8U1HxQnVi/bsG0HkDnON/Q== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:43 +0100 Subject: [PATCH v4 06/13] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-6-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the match data for the pinctrl found in the EyeQ6Lplus OLB. The pin control is identical in function to the one present in the EyeQ5 but has a single bank of 32 pins. Signed-off-by: Beno=C3=AEt Monin Reviewed-by: Linus Walleij --- drivers/pinctrl/Kconfig | 4 +- drivers/pinctrl/pinctrl-eyeq5.c | 95 +++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index afecd9407f53..72c7f21d81e4 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -254,11 +254,11 @@ config PINCTRL_EQUILIBRIUM config PINCTRL_EYEQ5 bool "Mobileye EyeQ5 pinctrl driver" depends on OF - depends on MACH_EYEQ5 || COMPILE_TEST + depends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST select PINMUX select GENERIC_PINCONF select AUXILIARY_BUS - default MACH_EYEQ5 + default MACH_EYEQ5 || MACH_EYEQ6LPLUS help Pin controller driver for the Mobileye EyeQ5 platform. It does both pin config & pin muxing. It does not handle GPIO. diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq= 5.c index c780af09cde9..dcdf80f07a90 100644 --- a/drivers/pinctrl/pinctrl-eyeq5.c +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -229,6 +229,100 @@ static const struct eq5p_match_data eq5p_eyeq5_data = =3D { .banks =3D eq5p_eyeq5_banks, }; =20 +static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] =3D { + PINCTRL_PIN(0, "PA0"), /* GPIO_A0_TIMER0_CK0 */ + PINCTRL_PIN(1, "PA1"), /* GPIO_A1_TIMER0_EOC */ + PINCTRL_PIN(2, "PA2"), /* GPIO_A2_TIMER1_CK */ + PINCTRL_PIN(3, "PA3"), /* GPIO_A3_TIMER1_EOC1 */ + PINCTRL_PIN(4, "PA4"), /* GPIO_A4_SSI_UART_RX */ + PINCTRL_PIN(5, "PA5"), /* GPIO_A5_SSI_UART_TX */ + PINCTRL_PIN(6, "PA6"), /* GPIO_A6_SPI_0_CS */ + PINCTRL_PIN(7, "PA7"), /* GPIO_A7_SPI_0_DI */ + PINCTRL_PIN(8, "PA8"), /* GPIO_A8_SPI_0_CK */ + PINCTRL_PIN(9, "PA9"), /* GPIO_A9_SPI_0_DO */ + PINCTRL_PIN(10, "PA10"), /* GPIO_A10_SPI_0_CS1 */ + PINCTRL_PIN(11, "PA11"), /* GPIO_A11_UART_0_RX */ + PINCTRL_PIN(12, "PA12"), /* GPIO_A12_UART_0_TX */ + PINCTRL_PIN(13, "PA13"), /* GPIO_A13_TIMER2_CK */ + PINCTRL_PIN(14, "PA14"), /* GPIO_A14_TIMER2_EOC */ + PINCTRL_PIN(15, "PA15"), /* GPIO_A15_TIMER3_CK */ + PINCTRL_PIN(16, "PA16"), /* GPIO_A16_TIMER_EOC */ + PINCTRL_PIN(17, "PA17"), /* GPIO_A17_TIMER_EXT0_INCA P1 */ + PINCTRL_PIN(18, "PA18"), /* GPIO_A18_TIMER_EXT0_INCA P2 */ + PINCTRL_PIN(19, "PA19"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */ + PINCTRL_PIN(20, "PA20"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */ + PINCTRL_PIN(21, "PA21"), /* GPIO_A21_SPI_1_CS0 */ + PINCTRL_PIN(22, "PA22"), /* GPIO_A22_SPI_1_DI */ + PINCTRL_PIN(23, "PA23"), /* GPIO_A23_SPI_1_CK */ + PINCTRL_PIN(24, "PA24"), /* GPIO_A24_SPI_1_DO */ + PINCTRL_PIN(25, "PA25"), /* GPIO_A25_SPI_1_CS1 */ + PINCTRL_PIN(26, "PA26"), /* GPIO_A26_TIMER_EXT1_INCA P1 */ + PINCTRL_PIN(27, "PA27"), /* GPIO_A27_TIMER_EXT1_INCA P2 */ + PINCTRL_PIN(28, "PA28"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */ + PINCTRL_PIN(29, "PA29"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */ + PINCTRL_PIN(30, "PA30"), /* GPIO_A30_EXT_CLK */ + PINCTRL_PIN(31, "PA31"), /* GPIO_A31_VDI_MCLK */ +}; + +static const char * const eq5p_eyeq6lplus_gpio_groups[] =3D { + /* Bank A */ + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27", "PA28", "PA29", "PA30", "PA31", +}; + +/* Groups of functions on bank A */ +static const char * const eq5p_eyeq6lplus_timer0_groups[] =3D { "PA0", "PA= 1" }; +static const char * const eq5p_eyeq6lplus_timer1_groups[] =3D { "PA2", "PA= 3" }; +static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] =3D { "PA4", "= PA5" }; +static const char * const eq5p_eyeq6lplus_spi0_groups[] =3D { "PA6", "PA7"= , "PA8", "PA9", "PA10" }; +static const char * const eq5p_eyeq6lplus_uart0_groups[] =3D { "PA11", "PA= 12" }; +static const char * const eq5p_eyeq6lplus_timer2_groups[] =3D { "PA13", "P= A14" }; +static const char * const eq5p_eyeq6lplus_timer3_groups[] =3D { "PA15", "P= A16" }; +static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] =3D { "PA17"= , "PA18", "PA19", "PA20" }; +static const char * const eq5p_eyeq6lplus_spi1_groups[] =3D { + "PA21", "PA22", "PA23", "PA24", "PA25" +}; +static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] =3D { "PA26"= , "PA27", "PA28", "PA29" }; +static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] =3D { "PA30= " }; +static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] =3D { "PA3= 1" }; + +static const struct pinfunction eq5p_eyeq6lplus_functions[] =3D { + /* gpios function */ + EQ5P_PINFUNCTION("gpio", eq5p_eyeq6lplus_gpio_groups), + + /* Bank A alternate functions */ + EQ5P_PINFUNCTION("timer0", eq5p_eyeq6lplus_timer0_groups), + EQ5P_PINFUNCTION("timer1", eq5p_eyeq6lplus_timer1_groups), + EQ5P_PINFUNCTION("uart_ssi", eq5p_eyeq6lplus_uart_ssi_groups), + EQ5P_PINFUNCTION("spi0", eq5p_eyeq6lplus_spi0_groups), + EQ5P_PINFUNCTION("uart0", eq5p_eyeq6lplus_uart0_groups), + EQ5P_PINFUNCTION("timer2", eq5p_eyeq6lplus_timer2_groups), + EQ5P_PINFUNCTION("timer3", eq5p_eyeq6lplus_timer3_groups), + EQ5P_PINFUNCTION("timer_ext0", eq5p_eyeq6lplus_timer_ext0_groups), + EQ5P_PINFUNCTION("spi1", eq5p_eyeq6lplus_spi1_groups), + EQ5P_PINFUNCTION("timer_ext1", eq5p_eyeq6lplus_timer_ext1_groups), + EQ5P_PINFUNCTION("ext_ref_clk", eq5p_eyeq6lplus_ext_ref_clk_groups), + EQ5P_PINFUNCTION("mipi_ref_clk", eq5p_eyeq6lplus_mipi_ref_clk_groups), +}; + +static const struct eq5p_bank eq5p_eyeq6lplus_banks[] =3D { + { + .npins =3D ARRAY_SIZE(eq5p_eyeq6lplus_pins), + .regs =3D {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0}, + }, +}; + +static const struct eq5p_match_data eq5p_eyeq6lplus_data =3D { + .npins =3D ARRAY_SIZE(eq5p_eyeq6lplus_pins), + .nfunctions =3D ARRAY_SIZE(eq5p_eyeq6lplus_functions), + .nbanks =3D ARRAY_SIZE(eq5p_eyeq6lplus_banks), + .pins =3D eq5p_eyeq6lplus_pins, + .functions =3D eq5p_eyeq6lplus_functions, + .banks =3D eq5p_eyeq6lplus_banks, +}; + static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl, const struct eq5p_bank *bank, enum eq5p_regs reg, u32 mask, u32 val) @@ -639,6 +733,7 @@ static int eq5p_probe(struct auxiliary_device *adev, =20 static const struct of_device_id eq5p_match_table[] =3D { { .compatible =3D "mobileye,eyeq5-olb", .data =3D &eq5p_eyeq5_data }, + { .compatible =3D "mobileye,eyeq6lplus-olb", .data =3D &eq5p_eyeq6lplus_d= ata }, {} }; MODULE_DEVICE_TABLE(of, eq5p_match_table); --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4533E3A4F3F; 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arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="2KYlx3jI" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id CA62C4E40B37; Mon, 16 Mar 2026 15:26:02 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 9E77E5FC4A; Mon, 16 Mar 2026 15:26:02 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 59063103721F2; Mon, 16 Mar 2026 16:26:00 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674761; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=bMU1zdQY7oxfR3rDnGue/fO4nWAsw/nZQUBlMCuYV9E=; b=2KYlx3jIvnftdlBWCpB3QD8jZsD67BTlQl9myQzFomuSnz68bff+1166NlG9T8NlJdliVN 5DiW2RY41WjyL0KzAfZYJL+QOxQ9Wk2B7enQUCRq3O6OsDQA6FO94N+r25kfFFvhZiV4v6 X10m3XqLamqLNq/OGlqFgyAKAh/KSgYNFAA+1AyruLa3I1hcrp+DJG/tK/pdUTMQ9fML/D LHyUKjoKzSm5x65ba17A8La4/mC3OfOA4psfRCAp9xXAfn+9awRRHhLiW/4uCwd6P/HnVx hIRSlJQ6uKp6yJrzg9eUMXNvavW3hDZYUWU+gWgW/C8OouRxhvWXiHg1MuFtJA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:44 +0100 Subject: [PATCH v4 07/13] clk: eyeq: Skip post-divisor when computing PLL frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-7-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The output of the PLL is routed before the post-divisor so it should be ignored when computing the frequency of the PLL, functional change is implemented to reflect how the clock signal is wired internally. For the PLL of the EyeQ5, EyeQ6L, and EyeQ6H, this change has no impact as the post-divisor is either reported as disabled or set to 1. The PLL frequency is the same before and after the post-divisor. For the PLL in EyeQ6Lplus, however, the post-divisor is not 1, so it must be ignored to compute the correct frequency. Signed-off-by: Beno=C3=AEt Monin Acked-by: Stephen Boyd --- drivers/clk/clk-eyeq.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index b17f47fda1da..904d7d77d415 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -178,8 +178,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsi= gned long *mult, =20 *mult =3D FIELD_GET(PCSR0_INTIN, r0); *div =3D FIELD_GET(PCSR0_REF_DIV, r0); - if (r0 & PCSR0_FOUTPOSTDIV_EN) - *div *=3D FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0= ); =20 /* Fractional mode, in 2^20 (0x100000) parts. */ if (r0 & PCSR0_DSM_EN) { --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F5643A63FB for ; Mon, 16 Mar 2026 15:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674767; cv=none; b=ubqXnbPE4yeANHyZgXS0NCHwM8pdl8dQxU8Ut0HRsExrn3jWJ4nqreBezJuXOb2gCVTYP1ehpYbQZY7OjSyvLXneCJ2iU2lr9tWv8hB+veKXNjoakMuXtfMLSVau7wkomNL0mols95LfkirLGZvXoCwnwg1oZri47iLYqRRPtp0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674767; c=relaxed/simple; bh=kz55thIenPw3bekdJ4aFbt2VUZoLFRkqCicN/30NKDE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vr7VGgy6/pcn+fAPAlcipBq15NF+7G8o5pG9HDmQ25whxAmPLr9UiqhEJ2KFVu3r2ZCWT4eB2jOPCHUCG+ENdX1kt/VQo51inMEgBVQuW6EgAB5STArBMQaMLzSxTH+8dlRjg/ayYLlDGQrwWR654gBag4PgdhqKDgccErJX+Jk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rlU0bcoB; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rlU0bcoB" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 26E174E426C0; Mon, 16 Mar 2026 15:26:05 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id F06C15FC4A; Mon, 16 Mar 2026 15:26:04 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 077EB103721F3; Mon, 16 Mar 2026 16:26:01 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674763; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fzigpU/p/PzFO6PSD51srQn9vza1EMhFgBBVZX2t/WQ=; b=rlU0bcoBsAEncaYDD+0VdD6lcTC9bnCiZpMYDYsdY6ojDX99uDmfKJD9T2A5Gk8dI0iDFt oL0oO6N5nzKT6QIS7Y+01P1EkoDE4SL0/X+QhNQafTX+rOOGBhDiffozrQA6Lo3pPW61eS AWKUP8nUY2+JuwsOeGme6AcSmezQeXFCKWRkI0UIu3wMCnzGFjnmQnbsYGVfOeamVHr8rP YC/y/2H2S/49v092H3iE0Qk680IOv94tf+U4U4J67EiVZjx+PS+vSzfJ1AGEusSaZHrp+F E2FJ8XCKiRcqh6ThxxPUE6frhW48dFE8zAfcozUCAHcrOd8gWWbFfVQjLFvWgw== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:45 +0100 Subject: [PATCH v4 08/13] clk: eyeq: Adjust PLL accuracy computation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-8-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The spread spectrum of the PLL found in eyeQ OLB is in 1/1024 parts of the frequency, not in 1/1000, so adjust the computation of the accuracy. Also correct the downspreading to match. Signed-off-by: Beno=C3=AEt Monin Acked-by: Stephen Boyd --- drivers/clk/clk-eyeq.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index 904d7d77d415..abffa46364f5 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -164,7 +164,7 @@ static void eqc_pll_downshift_factors(unsigned long *mu= lt, unsigned long *div) static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, unsigned long *div, unsigned long *acc) { - u32 spread; + unsigned long spread; =20 if (r0 & PCSR0_BYPASS) { *mult =3D 1; @@ -196,23 +196,23 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, un= signed long *mult, /* * Spread spectrum. * - * Spread is 1/1000 parts of frequency, accuracy is half of - * that. To get accuracy, convert to ppb (parts per billion). + * Spread is in 1/1024 parts of frequency. Clock accuracy + * is half the spread value expressed in parts per billion. * - * acc =3D spread * 1e6 / 2 - * with acc in parts per billion and, - * spread in parts per thousand. + * accuracy =3D (spread * 1e9) / (1024 * 2) + * + * Care is taken to avoid overflowing or losing precision. */ spread =3D FIELD_GET(PCSR1_SPREAD, r1); - *acc =3D spread * 500000; + *acc =3D DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2); =20 if (r1 & PCSR1_DOWN_SPREAD) { /* * Downspreading: the central frequency is half a * spread lower. */ - *mult *=3D 2000 - spread; - *div *=3D 2000; + *mult *=3D 2048 - spread; + *div *=3D 2048; =20 /* * Previous operation might overflow 32 bits. If it --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCE2C3A6EFE for ; Mon, 16 Mar 2026 15:26:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674769; cv=none; b=KYIHYIv1G86Nhj5iJEgE6psevNiuSafCoPeSwZljGLSSf4rIQrDElq6CSxzELJSyotHbVX4b2K8FLYnxKz10X2Rt7y8YfFn1e61Gfj7aNs/Pd1qGuDF3W9OlgHxfekQeUDNvSvtu/fYYfuHhiqkfG6vSLKHT/o7eRdCNP4lfDrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773674769; c=relaxed/simple; bh=POO5jZgBLxgudtTkfmz4w/k9zAm/3adMESWk60y0TP0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=epGISC3N+oNdNpAUziybVobWbBaRT30Ph3nFprYhiFONgKXw6rDtZv+IKadvvB2Shq1yh/HSxdCYv+wy75M0Xq7bMfUjWhr3Sb4kOU05x76cLzoCoiO0dqx3yc50KI/MHrLqIuSrQ5JtCpgASH3M+OfWcs2/KNO27OEvAjixLWc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=WhCakINY; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="WhCakINY" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 793501A2E6C; Mon, 16 Mar 2026 15:26:06 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 488A55FC4A; Mon, 16 Mar 2026 15:26:06 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EFD3B103721F5; Mon, 16 Mar 2026 16:26:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674765; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Sca1IFjitSHaa3J34xhk9u93ly8rAo7mslu4a9/oRQE=; b=WhCakINYfaXM4jW3tt9AnNsricGv9NHO2gRQIiMnysCM9hDLx+ixpusyfl0g8dXHfslqN9 WQJFkgr394SW8MuxqhVtwGiXKXw/GWs0jQdkndp7rjQAyXH1nShyiSX8FABE4YCQKy6B9T dleDOymNHrXC8asdMn3Cv97Tp72J7pGka5UfEnMpCmWLAHmXhTJ/+TgtjcInluVSzQ/nkz vKmaEghm4G2nZWB+1cgOVY42mPx7k/sVkEU4LmHV9qf9YK6aH+utYKn/aaXVzl4wm4tGXT K+qwAQdbuLQJDZH9q+WjX5bGKcSQuLqckHOtmFDyTLFv+FRu2O4NCIx+jOVZYw== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:46 +0100 Subject: [PATCH v4 09/13] clk: eyeq: Add Mobileye EyeQ6Lplus OLB Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-9-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Declare the PLLs and fixed factors found in the EyeQ6Lplus OLB as part of the match data for the "mobileye,eyeq6lplus-olb" compatible. The PLL and fixed factor of the CPU are registered in early init as they are required during the boot by the GIC timer. Also select clk-eyeq for all EYEQ SoCs instead of listing each one individually, as it is needed by all Mobileye EyeQ SoC. Signed-off-by: Beno=C3=AEt Monin Acked-by: Stephen Boyd --- drivers/clk/Kconfig | 4 +-- drivers/clk/clk-eyeq.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3d803b4cf5c1..240e9dbeff2b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -236,9 +236,9 @@ config COMMON_CLK_EP93XX =20 config COMMON_CLK_EYEQ bool "Clock driver for the Mobileye EyeQ platform" - depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST + depends on EYEQ || COMPILE_TEST select AUXILIARY_BUS - default MACH_EYEQ5 || MACH_EYEQ6H + default EYEQ help This driver provides clocks found on Mobileye EyeQ5, EyeQ6L and Eye6H SoCs. Controllers live in shared register regions called OLB. Driver diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index abffa46364f5..d9303c2c7aa5 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -45,6 +45,7 @@ #include =20 #include +#include =20 /* In frac mode, it enables fractional noise canceling DAC. Else, no funct= ion. */ #define PCSR0_DAC_EN BIT(0) @@ -541,6 +542,68 @@ static const struct eqc_match_data eqc_eyeq6l_match_da= ta =3D { .reset_auxdev_name =3D "reset", }; =20 +static const struct eqc_pll eqc_eyeq6lplus_early_plls[] =3D { + { .index =3D EQ6LPC_PLL_CPU, .name =3D "pll-cpu", .reg64 =3D 0x058 }, +}; + +static const struct eqc_pll eqc_eyeq6lplus_plls[] =3D { + { .index =3D EQ6LPC_PLL_DDR, .name =3D "pll-ddr", .reg64 =3D 0x02C }, + { .index =3D EQ6LPC_PLL_ACC, .name =3D "pll-acc", .reg64 =3D 0x034 }, + { .index =3D EQ6LPC_PLL_PER, .name =3D "pll-per", .reg64 =3D 0x03C }, + { .index =3D EQ6LPC_PLL_VDI, .name =3D "pll-vdi", .reg64 =3D 0x044 }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6lplus_early_fixed_factors[] = =3D { + { EQ6LPC_CPU_OCC, "occ-cpu", 1, 1, EQ6LPC_PLL_CPU }, +}; + +static const struct eqc_fixed_factor eqc_eyeq6lplus_fixed_factors[] =3D { + { EQ6LPC_DDR_OCC, "occ-ddr", 1, 1, EQ6LPC_PLL_DDR }, + + { EQ6LPC_ACC_VDI, "vdi-div", 1, 10, EQ6LPC_PLL_ACC }, + { EQ6LPC_ACC_OCC, "occ-acc", 1, 1, EQ6LPC_PLL_ACC }, + { EQ6LPC_ACC_FCMU, "fcmu-a-clk", 1, 10, EQ6LPC_ACC_OCC }, + + { EQ6LPC_PER_OCC, "occ-per", 1, 1, EQ6LPC_PLL_PER }, + { EQ6LPC_PER_I2C_SER, "i2c-ser-clk", 1, 10, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_PCLK, "pclk", 1, 4, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_TSU, "tsu-clk", 1, 8, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_OSPI, "ospi-ref-clk", 1, 10, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_GPIO, "gpio-clk", 1, 4, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_TIMER, "timer-clk", 1, 4, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_I2C, "i2c-clk", 1, 4, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_UART, "uart-clk", 1, 4, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_SPI, "spi-clk", 1, 4, EQ6LPC_PER_OCC }, + { EQ6LPC_PER_PERIPH, "periph-clk", 1, 1, EQ6LPC_PER_OCC }, + + { EQ6LPC_VDI_OCC, "occ-vdi", 1, 1, EQ6LPC_PLL_VDI }, +}; + +static const struct eqc_early_match_data eqc_eyeq6lplus_early_match_data _= _initconst =3D { + .early_pll_count =3D ARRAY_SIZE(eqc_eyeq6lplus_early_plls), + .early_plls =3D eqc_eyeq6lplus_early_plls, + + .early_fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq6lplus_early_fixed= _factors), + .early_fixed_factors =3D eqc_eyeq6lplus_early_fixed_factors, + + .late_clk_count =3D ARRAY_SIZE(eqc_eyeq6lplus_plls) + + ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors), +}; + +static const struct eqc_match_data eqc_eyeq6lplus_match_data =3D { + .pll_count =3D ARRAY_SIZE(eqc_eyeq6lplus_plls), + .plls =3D eqc_eyeq6lplus_plls, + + .fixed_factor_count =3D ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors), + .fixed_factors =3D eqc_eyeq6lplus_fixed_factors, + + .reset_auxdev_name =3D "reset", + .pinctrl_auxdev_name =3D "pinctrl", + + .early_clk_count =3D ARRAY_SIZE(eqc_eyeq6lplus_early_plls) + + ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors), +}; + static const struct eqc_match_data eqc_eyeq6h_west_match_data =3D { .reset_auxdev_name =3D "reset_west", }; @@ -642,6 +705,7 @@ static const struct eqc_match_data eqc_eyeq6h_acc_match= _data =3D { static const struct of_device_id eqc_match_table[] =3D { { .compatible =3D "mobileye,eyeq5-olb", .data =3D &eqc_eyeq5_match_data }, { .compatible =3D "mobileye,eyeq6l-olb", .data =3D &eqc_eyeq6l_match_data= }, + { .compatible =3D "mobileye,eyeq6lplus-olb", .data =3D &eqc_eyeq6lplus_ma= tch_data }, { .compatible =3D "mobileye,eyeq6h-west-olb", .data =3D &eqc_eyeq6h_west_= match_data }, { .compatible =3D "mobileye,eyeq6h-east-olb", .data =3D &eqc_eyeq6h_east_= match_data }, { .compatible =3D "mobileye,eyeq6h-south-olb", .data =3D &eqc_eyeq6h_sout= h_match_data }, @@ -825,3 +889,9 @@ static void __init eqc_eyeq6h_west_early_init(struct de= vice_node *np) } CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb", eqc_eyeq6h_west_early_init); + +static void __init eqc_eyeq6lplus_early_init(struct device_node *np) +{ + eqc_early_init(np, &eqc_eyeq6lplus_early_match_data); +} +CLK_OF_DECLARE_DRIVER(eqc_eyeq6lplus, "mobileye,eyeq6lplus-olb", eqc_eyeq6= lplus_early_init); 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Mon, 16 Mar 2026 16:26:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674767; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dfiuaLc8bx94tgxUemYFMGzOoB2nYnzT6eWglqGNczQ=; b=F3haMy3mO7ISotohV+KnVd/oue7uNXDL8C/FVzwobS6p3hc87OjEsr3rU7CRHbRJWg/4Qm v65mbxWxK7mkEEekEX+YdIVZ1JrWCf9J2ucOEyyO/bJ8j3tr3eJF9WRzPmBU3U5hZkxbVq EF+WKfmyQTs3usYRUGtVaIR9WU0v3No0qQ38ClCmF+y4LlL4oPs4rVoGz+xUEOpwvKKgZ+ o8cnNHZ0tAOWt5X4fB+xGMsgelxnBQKv5bVuiu9BprgtKtE+V0ctz2WJD8jqkfosDnaguQ 7qj07Hzaoem3E1dvVPtRb8zvraxrE0tdkgq9L3iFACFzVBkR5wVDmr04c8ND+A== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:47 +0100 Subject: [PATCH v4 10/13] MIPS: Add Mobileye EyeQ6Lplus SoC dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-10-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the device tree include files for the EyeQ6Lplus system on chip from Mobileye. Those files provide the initial support of the SoC: * The I6500 CPU and GIC interrupt controller. * The OLB ("Other Logic Block") providing clocks, resets and pin controls. * One UART. * One GPIO controller. * Two SPI controllers, one in host mode and one in target mode. * One octoSPI flash controller. * Two I2C controllers. Signed-off-by: Beno=C3=AEt Monin --- arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi | 84 +++++++++++ arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi | 170 +++++++++++++++++++= ++++ 2 files changed, 254 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi b/arch/mips/b= oot/dts/mobileye/eyeq6lplus-pins.dtsi new file mode 100644 index 000000000000..5cb0660f46c6 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +&olb { + timer0_pins: timer0-pins { + function =3D "timer0"; + pins =3D "PA0", "PA1"; + }; + timer1_pins: timer1-pins { + function =3D "timer1"; + pins =3D "PA2", "PA3"; + }; + uart_ssi_pins: uart-ssi-pins { + function =3D "uart_ssi"; + pins =3D "PA4", "PA5"; + }; + spi0_pins: spi0-pins { + function =3D "spi0"; + pins =3D "PA6", "PA7", "PA8", "PA9"; + }; + uart0_pins: uart0-pins { + function =3D "uart0"; + pins =3D "PA11", "PA12"; + }; + timer2_pins: timer2-pins { + function =3D "timer2"; + pins =3D "PA13", "PA14"; + }; + timer3_pins: timer3-pins { + function =3D "timer3"; + pins =3D "PA15", "PA16"; + }; + timer_ext0_pins: timer-ext0-pins { + function =3D "timer_ext0"; + pins =3D "PA17", "PA18", "PA19", "PA20"; + }; + timer_ext0_input_a_pins: timer-ext0-input-a-pins { + function =3D "timer_ext0"; + pins =3D "PA17"; + }; + pps0_pins: pps0-pins { + function =3D "timer_ext0"; + pins =3D "PA17"; + }; + timer_ext0_input_b_pins: timer-ext0-input-b-pins { + function =3D "timer_ext0"; + pins =3D "PA18"; + }; + timer_ext0_output_pins: timer-ext0-output-pins { + function =3D "timer_ext0"; + pins =3D "PA19", "PA20"; + }; + spi1_pins: spi1-pins { + function =3D "spi1"; + pins =3D "PA21", "PA22", "PA23", "PA24"; + }; + spi1_reduced_pins: spi1-reduced-pins { + function =3D "spi1"; + pins =3D "PA21", "PA22", "PA23"; + }; + timer_ext1_pins: timer-ext1-pins { + function =3D "timer_ext1"; + pins =3D "PA26", "PA27", "PA28", "PA29"; + }; + timer_ext1_input_a_pins: timer-ext1-input-a-pins { + function =3D "timer_ext1"; + pins =3D "PA26"; + }; + timer_ext1_input_b_pins: timer-ext1-input-b-pins { + function =3D "timer_ext1"; + pins =3D "PA27"; + }; + timer_ext1_output_pins: timer-ext1-output-pins { + function =3D "timer_ext1"; + pins =3D "PA28", "PA29"; + }; + ext_ref_clk_pins: ext-ref-clk-pins { + function =3D "ext_ref_clk"; + pins =3D "PA30"; + }; + mipi_ref_clk_pins: mipi-ref-clk-pins { + function =3D "mipi_ref_clk"; + pins =3D "PA31"; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi b/arch/mips/boot/d= ts/mobileye/eyeq6lplus.dtsi new file mode 100644 index 000000000000..4c72da917a95 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright 2025 Mobileye Vision Technologies Ltd. + */ + +#include + +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu@0 { + device_type =3D "cpu"; + compatible =3D "img,i6500"; + reg =3D <0>; + clocks =3D <&olb EQ6LPC_CPU_OCC>; + }; + }; + + cpu_intc: interrupt-controller { + compatible =3D "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + coherency-manager { + compatible =3D "mobileye,eyeq6-cm"; + }; + + xtal: clock-30000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <30000000>; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + olb: system-controller@e8400000 { + compatible =3D "mobileye,eyeq6lplus-olb", "syscon"; + reg =3D <0 0xe8400000 0x0 0x80000>; + #reset-cells =3D <2>; + #clock-cells =3D <1>; + clocks =3D <&xtal>; + clock-names =3D "ref"; + }; + + ospi: spi@e8800000 { + compatible =3D "mobileye,eyeq5-ospi", "cdns,qspi-nor"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0xe8800000 0x0 0x100000>, + <0 0xb0000000 0x0 0x30000000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + cdns,fifo-depth =3D <128>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x00000000>; + clocks =3D <&olb EQ6LPC_PER_OSPI>; + status =3D "disabled"; + }; + + spi0: spi@eac0d000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0 0xeac0d000 0x0 0x1000>; + clocks =3D <&olb EQ6LPC_PER_SPI>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <&olb 0 0>; + reset-names =3D "spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@eac0e000 { + compatible =3D "snps,dw-apb-ssi"; + reg =3D <0 0xeac0e000 0x0 0x1000>; + spi-slave; + clocks =3D <&olb EQ6LPC_PER_SPI>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <&olb 0 1>; + reset-names =3D "spi"; + #address-cells =3D <0>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@eac10000 { + compatible =3D "snps,dw-apb-uart"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&olb EQ6LPC_PER_UART>; + clock-frequency =3D <15625000>; + reg =3D <0 0xeac10000 0x0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + resets =3D <&olb 0 2>; + status =3D "disabled"; + }; + + i2c0: i2c@eac11000 { + compatible =3D "mobileye,eyeq6lplus-i2c", "snps,designware-i2c"; + reg =3D <0 0xeac11000 0x0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&olb EQ6LPC_PER_I2C_SER>; + resets =3D <&olb 0 3>; + i2c-sda-hold-time-ns =3D <50>; + status =3D "disabled"; + }; + + i2c1: i2c@eac12000 { + compatible =3D "mobileye,eyeq6lplus-i2c", "snps,designware-i2c"; + reg =3D <0 0xeac12000 0x0 0x1000>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + clock-frequency =3D <400000>; + clocks =3D <&olb EQ6LPC_PER_I2C_SER>; + resets =3D <&olb 0 4>; + i2c-sda-hold-time-ns =3D <50>; + status =3D "disabled"; + }; + + gpio: gpio@eac14000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0x0 0xeac14000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + resets =3D <&olb 0 13>; + porta: gpio-port@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + snps,nr-gpios =3D <32>; + gpio-ranges =3D <&olb 0 0 32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + gic: interrupt-controller@f0920000 { + compatible =3D "mti,gic"; + reg =3D <0x0 0xf0920000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&cpu_intc>; + timer { + compatible =3D "mti,gic-timer"; + interrupts =3D ; + clocks =3D <&olb EQ6LPC_CPU_OCC>; + }; + }; + }; +}; + +#include "eyeq6lplus-pins.dtsi" --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F51C3A7823; Mon, 16 Mar 2026 15:26:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="lbph7C6D" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 7A5234E40B37; Mon, 16 Mar 2026 15:26:10 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 505A35FC4A; Mon, 16 Mar 2026 15:26:10 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B35A6103721F7; Mon, 16 Mar 2026 16:26:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773674769; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=RynMD57QmlInHCRSqrRnZ8BdOyZAlob/tJmmv4olNGM=; b=lbph7C6DybpVHHQcsArG93jXN21QS2ayHM1QzSs2yRKgDRkYKZLEQ8EXGYayUZbb/TbsJn h7C4XkE/VQ7EQMkynAidDV0Am6TKrGLJY8eUULDvvh6D2mBdyZqDWEkeZZ13RPbL3cHsfU 4KNnXFe+AzJoH0QNo4ett/L6XLJgmU5jio1Q12hxJBONK86qo/239msPUpsskvE1BNtkHT fArlgR5T4pTbJvifAuiwcJLU8X9uCKu4zK+CfD9+Gz/mI7InW5WCGyJ+w4sZh+EC5sMAfh kmHwRIdYHe1in0c0qyi1MMOPwKKaJH1rtxb/y0UQ9QihXXfY3Sg0IdruvIlK1A== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:48 +0100 Subject: [PATCH v4 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-11-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add the device tree of the evaluation board of the EyeQ6Lplus SoC. The board comes with 2GB of RAM and an SPI NAND connected to the octoSPI controller The UART of the SoC is used as the serial console. Signed-off-by: Beno=C3=AEt Monin --- arch/mips/boot/dts/mobileye/Makefile | 1 + arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts | 103 ++++++++++++++++++++= ++++ 2 files changed, 104 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobi= leye/Makefile index 7cc89968aaac..9305dd01f4c8 100644 --- a/arch/mips/boot/dts/mobileye/Makefile +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -3,3 +3,4 @@ =20 dtb-$(CONFIG_MACH_EYEQ5) +=3D eyeq5-epm5.dtb dtb-$(CONFIG_MACH_EYEQ6H) +=3D eyeq6h-epm6.dtb +dtb-$(CONFIG_MACH_EYEQ6LPLUS) +=3D eyeq6lplus-epm6.dtb diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts b/arch/mips/bo= ot/dts/mobileye/eyeq6lplus-epm6.dts new file mode 100644 index 000000000000..404d0ff09f5a --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2025 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq6lplus.dtsi" + +/ { + compatible =3D "mobileye,eyeq6lplus-epm6", "mobileye,eyeq6lplus"; + model =3D "Mobileye EyeQ6Lplus Evaluation board"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x1 0x00000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + mhm_reserved_0: the-mhm-reserved-0 { + reg =3D <0x1 0x00000000 0x0 0x0000800>; + }; + bm_logs_reserved: bm-logs-reserved { + reg =3D <0x1 0x0000800 0x0 0x000f800>; + }; + shmem0_reserved: shmem@804000000 { + reg =3D <0x1 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg =3D <0x1 0x05000000 0x0 0x1000000>; + }; + mini_coredump0_reserved: mini-coredump0@806200000 { + reg =3D <0x1 0x06200000 0x0 0x100000>; + }; + mailbox_reserved: mailbox-reserved { + reg =3D <0x1 0x06300000 0x0 0x000300>; + }; + sys_logs_reserved: sys-logs-reserved { + reg =3D <0x1 0x10000000 0x0 0x800000>; + }; + csl_policy_logs_reserved: csl-policy-logs-reserved { + reg =3D <0x1 0x10800000 0x0 0x10000>; + }; + }; +}; + +&ospi { + status =3D "okay"; + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + spi-max-frequency =3D <40000000>; + cdns,read-delay =3D <0>; + cdns,tshsl-ns =3D <400>; + cdns,tsd2d-ns =3D <120>; + cdns,tchsh-ns =3D <40>; + cdns,tslch-ns =3D <20>; + spi-tx-bus-width =3D <1>; + spi-rx-bus-width =3D <8>; + }; +}; + +&spi0 { + pinctrl-0 =3D <&spi0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&spi1 { + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C68DE3A8726; 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bh=DMNcbL6zBp+PTc5h/KNHwWosR3kMnkkAB0mP2EbbEFc=; b=2d2r/9+axM3NevtzGhWnfrAYCzuRwqMHvpasKDNDMHqnDga1eSWq5PJqeRuQJUjXQVyRak L3QvHA12SmSYSB2wD1WpDaklC1l3Ne+4NHEx0cCjRBVFMl11uhMgmzXTX0UiBMBWlaTo5g ss62wpzZMw9Jr5u0wdqZUaZS5t/y/KLV4ldIoE7xlJPcSb8MLS8P+LrP6GjrJ/+GbEezle mliK6Vsh77b9Y7+8uhP4tNYVR3YqgHZFDhxq4uqL5wqhfBxJIBWr9+thu1CBiZrGihgJFT lOEZbZ52jFRklVQDzhLXWqyI4fOOdHJMiqT+GJo/V8P5uZCSCjSQjcxSuYCk3Q== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:49 +0100 Subject: [PATCH v4 12/13] MIPS: config: add eyeq6lplus_defconfig Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-12-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a default configuration for Mobileye EyeQ6Lplus evaluation board. Signed-off-by: Beno=C3=AEt Monin --- arch/mips/configs/eyeq6lplus_defconfig | 117 +++++++++++++++++++++++++++++= ++++ 1 file changed, 117 insertions(+) diff --git a/arch/mips/configs/eyeq6lplus_defconfig b/arch/mips/configs/eye= q6lplus_defconfig new file mode 100644 index 000000000000..39430ebf8e60 --- /dev/null +++ b/arch/mips/configs/eyeq6lplus_defconfig @@ -0,0 +1,117 @@ +CONFIG_SYSVIPC=3Dy +CONFIG_NO_HZ_IDLE=3Dy +CONFIG_HIGH_RES_TIMERS=3Dy +CONFIG_BPF_SYSCALL=3Dy +CONFIG_TASKSTATS=3Dy +CONFIG_IKCONFIG=3Dy +CONFIG_IKCONFIG_PROC=3Dy +CONFIG_MEMCG=3Dy +CONFIG_BLK_CGROUP=3Dy +CONFIG_CFS_BANDWIDTH=3Dy +CONFIG_RT_GROUP_SCHED=3Dy +CONFIG_CGROUP_PIDS=3Dy +CONFIG_CGROUP_FREEZER=3Dy +CONFIG_CPUSETS=3Dy +CONFIG_CGROUP_DEVICE=3Dy +CONFIG_CGROUP_CPUACCT=3Dy +CONFIG_NAMESPACES=3Dy +CONFIG_USER_NS=3Dy +CONFIG_SCHED_AUTOGROUP=3Dy +CONFIG_BLK_DEV_INITRD=3Dy +CONFIG_EXPERT=3Dy +CONFIG_EYEQ=3Dy +CONFIG_MACH_EYEQ6LPLUS=3Dy +CONFIG_MIPS_CPS=3Dy +CONFIG_CPU_HAS_MSA=3Dy +CONFIG_NR_CPUS=3D16 +CONFIG_MIPS_RAW_APPENDED_DTB=3Dy +CONFIG_JUMP_LABEL=3Dy +CONFIG_PAGE_SIZE_16KB=3Dy +CONFIG_COMPAT_32BIT_TIME=3Dy +CONFIG_MODULES=3Dy +CONFIG_MODULE_UNLOAD=3Dy +CONFIG_TRIM_UNUSED_KSYMS=3Dy +# CONFIG_COMPAT_BRK is not set +CONFIG_USERFAULTFD=3Dy +CONFIG_NET=3Dy +CONFIG_PACKET=3Dy +CONFIG_UNIX=3Dy +CONFIG_INET=3Dy +CONFIG_IP_PNP=3Dy +CONFIG_IP_PNP_DHCP=3Dy +CONFIG_NETFILTER=3Dy +CONFIG_CAN=3Dy +CONFIG_PCI=3Dy +CONFIG_PCI_MSI=3Dy +CONFIG_PCI_DEBUG=3Dy +CONFIG_PCI_ENDPOINT=3Dy +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +CONFIG_CONNECTOR=3Dy +CONFIG_MTD=3Dy +CONFIG_MTD_SPI_NAND=3Dy +CONFIG_MTD_UBI=3Dy +CONFIG_MTD_UBI_BLOCK=3Dy +CONFIG_SCSI=3Dy +CONFIG_NETDEVICES=3Dy +CONFIG_MACVLAN=3Dy +CONFIG_IPVLAN=3Dy +CONFIG_MACB=3Dy +CONFIG_MARVELL_PHY=3Dy +CONFIG_MICREL_PHY=3Dy +CONFIG_CAN_M_CAN=3Dy +CONFIG_SERIAL_8250=3Dy +CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_8250_DW=3Dy +CONFIG_HW_RANDOM=3Dy +CONFIG_I2C=3Dy +CONFIG_I2C_CHARDEV=3Dy +CONFIG_I2C_DESIGNWARE_CORE=3Dy +CONFIG_SPI=3Dy +CONFIG_SPI_CADENCE_QUADSPI=3Dy +CONFIG_SPI_DESIGNWARE=3Dy +CONFIG_SPI_DW_MMIO=3Dy +CONFIG_SPI_SPIDEV=3Dy +CONFIG_SPI_SLAVE=3Dy +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=3Dy +CONFIG_GPIOLIB=3Dy +CONFIG_GPIO_DWAPB=3Dy +CONFIG_MFD_SYSCON=3Dy +CONFIG_HID_A4TECH=3Dy +CONFIG_HID_BELKIN=3Dy +CONFIG_HID_CHERRY=3Dy +CONFIG_HID_CYPRESS=3Dy +CONFIG_HID_EZKEY=3Dy +CONFIG_HID_ITE=3Dy +CONFIG_HID_KENSINGTON=3Dy +CONFIG_HID_REDRAGON=3Dy +CONFIG_HID_MICROSOFT=3Dy +CONFIG_HID_MONTEREY=3Dy +CONFIG_MMC=3Dy +CONFIG_MMC_SDHCI=3Dy +CONFIG_MMC_SDHCI_PLTFM=3Dy +CONFIG_MMC_SDHCI_CADENCE=3Dy +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=3Dy +# CONFIG_NVMEM is not set +CONFIG_EXT4_FS=3Dy +CONFIG_EXT4_FS_POSIX_ACL=3Dy +CONFIG_EXT4_FS_SECURITY=3Dy +CONFIG_FS_ENCRYPTION=3Dy +CONFIG_FUSE_FS=3Dy +CONFIG_CUSE=3Dy +CONFIG_MSDOS_FS=3Dy +CONFIG_VFAT_FS=3Dy +CONFIG_TMPFS=3Dy +CONFIG_TMPFS_POSIX_ACL=3Dy +CONFIG_UBIFS_FS=3Dy +CONFIG_NFS_FS=3Dy +CONFIG_NFS_V3_ACL=3Dy +CONFIG_NFS_V4=3Dy +CONFIG_NFS_V4_2=3Dy +CONFIG_ROOT_NFS=3Dy +CONFIG_FRAME_WARN=3D1024 +CONFIG_DEBUG_FS=3Dy +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set --=20 2.53.0 From nobody Tue Apr 7 02:54:17 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E8DE3A2541; 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bh=t13fTL38ybBnjcJkpfx+K3cUGVZwn08bqofOvp3rY/E=; b=g7wEu8wMxX14MPtuGpZ3ujPtebXwaYKya4BVSMUMXY6d2jmNLwfi4RsmVX1UH28Smz24ax 7TqPs8xLfeEfQZMrZ1ORToYJgtJttR+2wfDycflPSIrX7m94pPIH4ADkroO5TC5PaxIAQR iTvbfvRa+zOxQaKSHvc3GnfBr3qNDB+MrLuqLLdAxjEDmuWmC6rOwHuFQkN1QTsj/hT7nD E3Ixl5ChZDd553sn+onzq581qTC0yunPSUfOn/kuia+eQ3RCavKnT0ibkNBJfon5A2xjmb DbvmB816++87ULv9YHpBPNzn/cb4hhtMAHXPgIe3y9r+8YYlLNjtfF8Ld5mxkA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Mon, 16 Mar 2026 16:25:50 +0100 Subject: [PATCH v4 13/13] MAINTAINERS: Mobileye: Add EyeQ6Lplus files Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260316-eyeq6lplus-v4-13-bf44dfc7a261@bootlin.com> References: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> In-Reply-To: <20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij Cc: Thomas Petazzoni , Tawfik Bayouk , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Beno=C3=AEt_Monin?= X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Use wildcard to match all EyeQ defconfigs under arch/mips. This covers the newly added defconfig, and the EyeQ5 and EyeQ6H ones. Add an entry for the dt-bindings header of the EyeQ6Lplus clocks. While at it, add myself to the maintainers of Mobileye MIPS SoCs. Signed-off-by: Beno=C3=AEt Monin --- MAINTAINERS | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 55af015174a5..63048d5ede7d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17802,6 +17802,7 @@ F: drivers/media/dvb-frontends/mn88473* =20 MOBILEYE MIPS SOCS M: Vladimir Kondratiev +M: Beno=C3=AEt Monin M: Gregory CLEMENT M: Th=C3=A9o Lebrun L: linux-mips@vger.kernel.org @@ -17809,12 +17810,13 @@ S: Maintained F: Documentation/devicetree/bindings/mips/mobileye.yaml F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ -F: arch/mips/configs/eyeq5_defconfig +F: arch/mips/configs/eyeq*_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq.c F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h +F: include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h =20 MODULE SUPPORT M: Luis Chamberlain --=20 2.53.0