From nobody Tue Apr 7 06:14:32 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E8F34C6D; Mon, 16 Mar 2026 03:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630061; cv=none; b=F7ILT+ggQJyedMiyIzGciD2FvJkwIYAdQ1pxu3jxmHHtKCCk4g2AF+8mBar9bs7ihOJqsOq2OcWD1yBzvRwR2Q9QoXjhsFgRElx5KMMrgYYsF4b/c5MpXfg6A4VHZGdjdSIpr34/R2KgLK20jLLH6TYek+LQnhPVAK+dtkkWxSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630061; c=relaxed/simple; bh=rESyvr9FI4k+pXWuBtBd2BjqM1Hm5GV8Bt0NdXlFyLU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jP4XQe1BnpjFuUMU40bcEwHUkfAQ0/l7+iRub82yQnm8iglTHHGavClkjXca+QA6JvL7T1WH9MqrJcsXDfr8Jeb941lRoJq79CvC674UU8xylojpyHoH5RhieUkAjnXkeocDwltAdRzHl6rr1n/pHBEWPejH2Ym6YBUlxW8/af4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 16 Mar 2026 11:00:47 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 16 Mar 2026 11:00:47 +0800 From: Billy Tsai Date: Mon, 16 Mar 2026 11:00:47 +0800 Subject: [PATCH v2 2/3] iio: adc: Enable multiple consecutive channels based on model data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260316-adc-v2-2-21475a217b09@aspeedtech.com> References: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> In-Reply-To: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773630047; l=2441; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=rESyvr9FI4k+pXWuBtBd2BjqM1Hm5GV8Bt0NdXlFyLU=; b=wCLeoY6AJwRWGyZ1g6zFZX4s/XiFltkM0W8fkuHXuM4R27q8k+whENeJ0ChcMS3z7I/N2jwWp DVR6/UOGxzzBOujREyHpD2AHRU8pjL7ulY08ZsbltKXMEKLLN+gHfFl X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add helpers to generate channel masks and enable multiple ADC channels according to the device model's channel count. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index af9a95d31d81..81a2dd752541 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -72,6 +72,29 @@ #define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHAN= NEL, BIT(ch)) + +/* + * Enable multiple consecutive channels starting from channel 0. + * This creates a bitmask for channels 0 to (num_channels - 1). + * For example: num_channels=3D3 creates mask 0x0007 (channels 0,1,2) + */ +static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) +{ + if (num_channels =3D=3D 0) + return 0; + if (num_channels >=3D 16) + return GENMASK(15, 0); + return GENMASK(num_channels - 1, 0); +} + +/* + * Helper function to enable multiple channels in the control register + */ +static inline u32 aspeed_adc_enable_channels(unsigned int num_channels) +{ + return FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, aspeed_adc_channels_mask(num_c= hannels)); +} + /* Battery sensing is typically on the last channel */ #define ASPEED_ADC_BATTERY_CHANNEL 7 =20 @@ -123,6 +146,11 @@ struct aspeed_adc_data { struct adc_gain battery_mode_gain; }; =20 +static inline unsigned int aspeed_adc_get_active_channels(const struct asp= eed_adc_data *data) +{ + return data->model_data->num_channels; +} + #define ASPEED_CHAN(_idx, _data_reg_addr) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -610,9 +638,10 @@ static int aspeed_adc_probe(struct platform_device *pd= ev) =20 aspeed_adc_compensation(indio_dev); /* Start all channels in normal mode. */ - adc_engine_control_reg_val =3D - readl(data->base + ASPEED_REG_ENGINE_CONTROL); - adc_engine_control_reg_val |=3D ASPEED_ADC_CTRL_CHANNEL; + adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTR= OL); + adc_engine_control_reg_val |=3D + aspeed_adc_enable_channels(aspeed_adc_get_active_channels(data)); + writel(adc_engine_control_reg_val, data->base + ASPEED_REG_ENGINE_CONTROL); =20 --=20 2.34.1