From nobody Tue Apr 7 04:45:25 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 958B831F995; Mon, 16 Mar 2026 03:00:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630059; cv=none; b=h+3Xeur7ObvM8pdDgLA34FXsaDIl2gX29o6qwUdasqNbQaJ4LvwgPFmqVGj3do+2D/4RCRVCpsRckEYlxmwlUBbVb8OkTqQChLgh3dTVXtBZ/7P/RXy+rD7K3/1YjVHMEFVsfRgckPovjoqsiS3JLpGVBr1dqDSNmnwzAw8H2zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630059; c=relaxed/simple; bh=GZwwwE7oVnurHeVr7/W1QtASLg5VwPGmo5eS0xkT1dQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=A+b1xFtW17Co4KJ9+dERPHkV0RxEICUjimeL4v/dY5b9MXQMuGCQTT9eD7LYiXz/1rQDxgRmiZ97I1lVPefprZWINXd4EGlEMJu2pmT1yxSsYT8rdhgfTwa6P8NKmJKRta13L/jT+0B2ml8iKTLoqletb4Js25snPCwghTqCOqk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 16 Mar 2026 11:00:47 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 16 Mar 2026 11:00:47 +0800 From: Billy Tsai Date: Mon, 16 Mar 2026 11:00:46 +0800 Subject: [PATCH v2 1/3] iio: adc: Add battery channel definition for ADC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260316-adc-v2-1-21475a217b09@aspeedtech.com> References: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> In-Reply-To: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773630047; l=1666; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=GZwwwE7oVnurHeVr7/W1QtASLg5VwPGmo5eS0xkT1dQ=; b=IFn+eYF7YKhXYpsxr6TRY6l5rykGbuUz1/dNHl4P+K3JQJSNkaqETwX9Yq5iHieye0peTM/Ul 5SxvX+48YPxBmSR+VLIzfEl3p4ZAH2bivMJAPZPshz6se9Z9JfuGhjy X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Defines a constant for the battery sensing channel, typically the last channel of the ADC. Clarifies channel usage and improves code readability. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 4be44c524b4d..af9a95d31d81 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -72,6 +72,8 @@ #define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHAN= NEL, BIT(ch)) +/* Battery sensing is typically on the last channel */ +#define ASPEED_ADC_BATTERY_CHANNEL 7 =20 #define ASPEED_ADC_INIT_POLLING_TIME 500 #define ASPEED_ADC_INIT_TIMEOUT 500000 @@ -285,7 +287,7 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_de= v, =20 switch (mask) { case IIO_CHAN_INFO_RAW: - if (data->battery_sensing && chan->channel =3D=3D 7) { + if (data->battery_sensing && chan->channel =3D=3D ASPEED_ADC_BATTERY_CHA= NNEL) { adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTROL); writel(adc_engine_control_reg_val | @@ -309,7 +311,7 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_de= v, return IIO_VAL_INT; =20 case IIO_CHAN_INFO_OFFSET: - if (data->battery_sensing && chan->channel =3D=3D 7) + if (data->battery_sensing && chan->channel =3D=3D ASPEED_ADC_BATTERY_CHA= NNEL) *val =3D (data->cv * data->battery_mode_gain.mult) / data->battery_mode_gain.div; else --=20 2.34.1 From nobody Tue Apr 7 04:45:25 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E8F34C6D; Mon, 16 Mar 2026 03:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630061; cv=none; b=F7ILT+ggQJyedMiyIzGciD2FvJkwIYAdQ1pxu3jxmHHtKCCk4g2AF+8mBar9bs7ihOJqsOq2OcWD1yBzvRwR2Q9QoXjhsFgRElx5KMMrgYYsF4b/c5MpXfg6A4VHZGdjdSIpr34/R2KgLK20jLLH6TYek+LQnhPVAK+dtkkWxSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630061; c=relaxed/simple; bh=rESyvr9FI4k+pXWuBtBd2BjqM1Hm5GV8Bt0NdXlFyLU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jP4XQe1BnpjFuUMU40bcEwHUkfAQ0/l7+iRub82yQnm8iglTHHGavClkjXca+QA6JvL7T1WH9MqrJcsXDfr8Jeb941lRoJq79CvC674UU8xylojpyHoH5RhieUkAjnXkeocDwltAdRzHl6rr1n/pHBEWPejH2Ym6YBUlxW8/af4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 16 Mar 2026 11:00:47 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 16 Mar 2026 11:00:47 +0800 From: Billy Tsai Date: Mon, 16 Mar 2026 11:00:47 +0800 Subject: [PATCH v2 2/3] iio: adc: Enable multiple consecutive channels based on model data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260316-adc-v2-2-21475a217b09@aspeedtech.com> References: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> In-Reply-To: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773630047; l=2441; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=rESyvr9FI4k+pXWuBtBd2BjqM1Hm5GV8Bt0NdXlFyLU=; b=wCLeoY6AJwRWGyZ1g6zFZX4s/XiFltkM0W8fkuHXuM4R27q8k+whENeJ0ChcMS3z7I/N2jwWp DVR6/UOGxzzBOujREyHpD2AHRU8pjL7ulY08ZsbltKXMEKLLN+gHfFl X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add helpers to generate channel masks and enable multiple ADC channels according to the device model's channel count. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index af9a95d31d81..81a2dd752541 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -72,6 +72,29 @@ #define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHAN= NEL, BIT(ch)) + +/* + * Enable multiple consecutive channels starting from channel 0. + * This creates a bitmask for channels 0 to (num_channels - 1). + * For example: num_channels=3D3 creates mask 0x0007 (channels 0,1,2) + */ +static inline u32 aspeed_adc_channels_mask(unsigned int num_channels) +{ + if (num_channels =3D=3D 0) + return 0; + if (num_channels >=3D 16) + return GENMASK(15, 0); + return GENMASK(num_channels - 1, 0); +} + +/* + * Helper function to enable multiple channels in the control register + */ +static inline u32 aspeed_adc_enable_channels(unsigned int num_channels) +{ + return FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, aspeed_adc_channels_mask(num_c= hannels)); +} + /* Battery sensing is typically on the last channel */ #define ASPEED_ADC_BATTERY_CHANNEL 7 =20 @@ -123,6 +146,11 @@ struct aspeed_adc_data { struct adc_gain battery_mode_gain; }; =20 +static inline unsigned int aspeed_adc_get_active_channels(const struct asp= eed_adc_data *data) +{ + return data->model_data->num_channels; +} + #define ASPEED_CHAN(_idx, _data_reg_addr) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -610,9 +638,10 @@ static int aspeed_adc_probe(struct platform_device *pd= ev) =20 aspeed_adc_compensation(indio_dev); /* Start all channels in normal mode. */ - adc_engine_control_reg_val =3D - readl(data->base + ASPEED_REG_ENGINE_CONTROL); - adc_engine_control_reg_val |=3D ASPEED_ADC_CTRL_CHANNEL; + adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONTR= OL); + adc_engine_control_reg_val |=3D + aspeed_adc_enable_channels(aspeed_adc_get_active_channels(data)); + writel(adc_engine_control_reg_val, data->base + ASPEED_REG_ENGINE_CONTROL); =20 --=20 2.34.1 From nobody Tue Apr 7 04:45:25 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10C5131F9B5; Mon, 16 Mar 2026 03:01:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630063; cv=none; b=LL/9Hc5QAPtMeldYtsauUxJZAIM2h3fLPkinw9Y56sZxSvrCej/hhhJGUocJOW7DAMAaxBi3fQ93aQkQMASHCMbgZl+hpLYEIG0qmK4QGh4znVJ3v52fgcRRH6JK1H4J8nBkXLopgPbN4o+/TLtbCwdBa+Xc6q5hqf/8S8Q0mi8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773630063; c=relaxed/simple; bh=NDFWhGINrDRsy3G0bfBO0q4ZxiMyFTtoWTFlKzGT8bg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Kh1McPR++DruoOf8k6gLAsrUDL46OLKGFl1cmzs55To87/nzoOGH+vNPwWxkA50oCy6uVK6ZBpGxaweehYXaCpwRS0BwNpdGg0uA+ieHzHHTQ5RGCN9vnWLu/eBnMH9j/ktEzMUdAC1YjlVFU2sTAtiUtbXqfFogvfJJDEcDcCE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 16 Mar 2026 11:00:48 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 16 Mar 2026 11:00:48 +0800 From: Billy Tsai Date: Mon, 16 Mar 2026 11:00:48 +0800 Subject: [PATCH v2 3/3] iio: adc: aspeed: Reserve battery sensing channel for on-demand use Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260316-adc-v2-3-21475a217b09@aspeedtech.com> References: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> In-Reply-To: <20260316-adc-v2-0-21475a217b09@aspeedtech.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Joel Stanley , Andrew Jeffery CC: , , , , , Billy Tsai X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773630047; l=3044; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=NDFWhGINrDRsy3G0bfBO0q4ZxiMyFTtoWTFlKzGT8bg=; b=8+JasgxeNNHI5TmBibZAQ6o3VSNdAtCoMXPHE46zCX4x1ALdv0eCR3VXkTeVQYfJuIc07K160 P2qmexYd5iSCsN5gia0/OnQHF3m7pxjNAjBii10chq1nZ31mI2AqNnB X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= For controllers with battery sensing capability (AST2600/AST2700), the last channel uses a different circuit design optimized for battery voltage measurement. This channel should not be enabled by default along with other channels to avoid potential interference and power efficiency issues. This ensures optimal power efficiency for normal ADC operations while maintaining full functionality when battery sensing is needed. Signed-off-by: Billy Tsai --- drivers/iio/adc/aspeed_adc.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 81a2dd752541..ab173d8542c6 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -148,6 +148,13 @@ struct aspeed_adc_data { =20 static inline unsigned int aspeed_adc_get_active_channels(const struct asp= eed_adc_data *data) { + /* + * For controllers with battery sensing capability, the last channel + * is reserved for battery sensing and should not be included in + * normal channel operations. + */ + if (data->model_data->bat_sense_sup) + return data->model_data->num_channels - 1; return data->model_data->num_channels; } =20 @@ -315,9 +322,26 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_d= ev, =20 switch (mask) { case IIO_CHAN_INFO_RAW: + adc_engine_control_reg_val =3D readl(data->base + ASPEED_REG_ENGINE_CONT= ROL); + /* + * For battery sensing capable controllers, we need to enable + * the specific channel before reading. This is required because + * the battery channel may not be enabled by default. + */ + if (data->model_data->bat_sense_sup && + chan->channel =3D=3D ASPEED_ADC_BATTERY_CHANNEL) { + u32 ctrl_reg =3D adc_engine_control_reg_val & ~ASPEED_ADC_CTRL_CHANNEL; + + ctrl_reg |=3D ASPEED_ADC_CTRL_CHANNEL_ENABLE(chan->channel); + writel(ctrl_reg, data->base + ASPEED_REG_ENGINE_CONTROL); + /* + * After enable a new channel need to wait some time for adc stable + * Experiment result is 1ms. + */ + mdelay(1); + } + if (data->battery_sensing && chan->channel =3D=3D ASPEED_ADC_BATTERY_CHA= NNEL) { - adc_engine_control_reg_val =3D - readl(data->base + ASPEED_REG_ENGINE_CONTROL); writel(adc_engine_control_reg_val | FIELD_PREP(ASPEED_ADC_CH7_MODE, ASPEED_ADC_CH7_BAT) | @@ -331,11 +355,11 @@ static int aspeed_adc_read_raw(struct iio_dev *indio_= dev, *val =3D readw(data->base + chan->address); *val =3D (*val * data->battery_mode_gain.mult) / data->battery_mode_gain.div; - /* Restore control register value */ - writel(adc_engine_control_reg_val, - data->base + ASPEED_REG_ENGINE_CONTROL); } else *val =3D readw(data->base + chan->address); + /* Restore control register value */ + writel(adc_engine_control_reg_val, + data->base + ASPEED_REG_ENGINE_CONTROL); return IIO_VAL_INT; =20 case IIO_CHAN_INFO_OFFSET: --=20 2.34.1