From nobody Tue Apr 7 09:49:08 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1FC32D5935; Sat, 14 Mar 2026 16:28:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773505738; cv=none; b=PB6Zomz7HzHRL4Sq5xHEowOWnyN6qaPCUD+hKBiPGHVeQXuxU/t0//dUoyoyJN5e8reikL3dMhLWSJs9B77UnuJYlBRa6qFN21bcHT41it3q5kMmMugU38afMLPZzzliypkcCcv53dSJtbdLO7SjDOFBSE7WoGUb51nOoj0eOSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773505738; c=relaxed/simple; bh=uWWHmZ0HKKnTQHe3f3HvLp8HveAdTyIbri3LH+YWsmU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mIcVZ/sda9nYwq7yIvByOtAVTo0B4fqT//57U220yuHh0gfAoFAm0fTo2TXO35rgboF0SwckHdsj2aS13d0w5AWgen6eFHeoCEbaDr/4XnI4BuFbp1eZ8jc17X10GCjHqqSZfvLt2WpyRm8ZLhv8c51aF9Js2sxwNkwklQumr4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.100.43]) by APP-03 (Coremail) with SMTP id rQCowAB3ktmwjLVpHpqpCg--.41252S4; Sun, 15 Mar 2026 00:28:44 +0800 (CST) From: Icenowy Zheng To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Huacai Chen , WANG Xuerui , Thomas Bogendoerfer , Jiaxun Yang Cc: Icenowy Zheng , Yao Zi , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, Icenowy Zheng Subject: [PATCH v3 2/8] LoongArch: Override arch_dynirq_lower_bound to reserve LPC IRQs Date: Sun, 15 Mar 2026 00:28:22 +0800 Message-ID: <20260314162828.1055188-3-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260314162828.1055188-1-zhengxingda@iscas.ac.cn> References: <20260314162828.1055188-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAB3ktmwjLVpHpqpCg--.41252S4 X-Coremail-Antispam: 1UD129KBjvJXoW7WryrCFW7Jr17CFy7KrWrGrg_yoW8Xw48pa 9ruF4DXrs5GryDZF15Aw1F9ry5ZaykWw17WF9Iqa4xZr1aqrn0gwnYqrZ3XFy0qw4v9F4j 9F15XrZ8WFs8AaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0x vEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVj vjDU0xZFpf9x0JUQXo7UUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Loongson 7A PCH chips all contain a LPC controller, which is used in some devices to connect legacy ISA devices (e.g. 8259 PS/2 controller). The LPC IRQ driver will register LPC IRQs at the fixed range 0~15, and the PCH PIC IRQ driver uses dynamic allocation. However the LPC IRQs are currently not exempted from dynamic allocation. The currently setup work by accident because the LPC IRQ controller is the first consumer of PIC IRQ controller, and the PIC IRQ number is allocated after LPC IRQs are registered. Such setup is fragile and will stop to work when the LPC IRQ driver is reworked. Override arch_dynirq_lower_bound() to reserve LPC IRQs from dynamic allocation, to prevent IRQ number collision and allow rework of the LPC IRQ driver. Signed-off-by: Icenowy Zheng --- arch/loongarch/kernel/irq.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c index 80946cafaec1b..7bf68a7a5f4b3 100644 --- a/arch/loongarch/kernel/irq.c +++ b/arch/loongarch/kernel/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -99,6 +100,11 @@ int __init arch_probe_nr_irqs(void) return NR_IRQS_LEGACY; } =20 +unsigned int arch_dynirq_lower_bound(unsigned int from) +{ + return MAX(from, NR_IRQS_LEGACY); +} + void __init init_IRQ(void) { int i; --=20 2.52.0