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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:28 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 3/6] phy: qcom-qmp-usbc: Use register definitions in qserdes-txrx-v3 Date: Sat, 14 Mar 2026 13:13:22 +0800 Message-ID: <20260314051325.198137-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfX/AqReoEs0S4w fEspPqLy6kqC82CJN8gN/t5Yy2SWGI9LH6SsofqCiv/f4h51u0PD18fqAisd072uaFSXC3XTJ5L RAAjQT/ppSb4U5yMSGyzzJb2EBDfqapJVjb7RXI5TC8OUJ8mnfLyqw6/IVcsKbiEp7D+aSRZJhF jNE9N3+VDDgYtZ8DAXnPOuS7qNSLlIl2xYM4/7xhBF3pxrRUFSeq5wtI0SSmqFcMFgxjEcqrt9m 4yJheDpRbGgeszmO9kcLAvJfYcETUocTZerQUjEpgJnMClXrinivyu3fvSBh0CYpP/fwhnQHWzf fZ2XOtws6rNfipOiZGzpu6anTtfUDSc/DO3eE2SES/7tHHmiNXAAGAXSUFP2b7/xnmjSt+UNdBH bUThPgpJbBwJU0BWYNGlXGNpIr4uhcVCH/p9nR13vJzo2dobMXSR6UTjrSUAZGocaTtHdw9gY0Q Hp9cZDOr2KUTqiiSHWQ== X-Authority-Analysis: v=2.4 cv=YLOSCBGx c=1 sm=1 tr=0 ts=69b4eeb6 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=f3I94rbs0dppKun-wmkA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: ECpsvHyoVY2nzDoap2dHSs4kN32JAdpL X-Proofpoint-GUID: ECpsvHyoVY2nzDoap2dHSs4kN32JAdpL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" The register definitions in header qserdes-txrx-v2 and qserdes-txrx-v3 are actually identical. Considering that QSERDES TX/RX v2 is already defined by header qserdes-txrx, qserdes-txrx-v2 is really just a duplication of qserdes-txrx-v3 for QSERDES TX/RX v3. Switch qcom-qmp-usbc driver to use v3 registers. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 64 ++++++++++++------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 1b841e805536..3f8c4280b933 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -351,20 +351,20 @@ static const struct qmp_phy_init_tbl qmp_v2_dp_serdes= _tbl_hbr2[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRANSCEIVER_BIAS_EN, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_VMODE_CTRL1, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_INTERFACE_SELECT, 0x3d), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_CLKBUF_ENABLE, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_RESET_TSYNC_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRAN_DRVR_EMP_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_EMP_POST1_LVL, 0x2b), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_DRV_LVL, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_BAND, 0x4), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_TX, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_RX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), }; =20 struct qmp_usbc_offsets { @@ -809,10 +809,10 @@ static int qmp_v2_configure_dp_swing(struct qmp_usbc = *qmp) if (voltage_swing_cfg =3D=3D 0xff && pre_emphasis_cfg =3D=3D 0xff) return -EINVAL; =20 - writel(voltage_swing_cfg, tx + QSERDES_V2_TX_TX_DRV_LVL); - writel(pre_emphasis_cfg, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL); - writel(voltage_swing_cfg, tx2 + QSERDES_V2_TX_TX_DRV_LVL); - writel(pre_emphasis_cfg, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); =20 return 0; } @@ -871,17 +871,17 @@ static void qmp_v2_configure_dp_tx(struct qmp_usbc *q= mp) void __iomem *tx2 =3D qmp->dp_tx2; =20 /* program default setting first */ - writel(0x2a, tx + QSERDES_V2_TX_TX_DRV_LVL); - writel(0x20, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL); - writel(0x2a, tx2 + QSERDES_V2_TX_TX_DRV_LVL); - writel(0x20, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); =20 if (dp_opts->link_rate >=3D 2700) { - writel(0xc4, tx + QSERDES_V2_TX_LANE_MODE_1); - writel(0xc4, tx2 + QSERDES_V2_TX_LANE_MODE_1); + writel(0xc4, tx + QSERDES_V3_TX_LANE_MODE_1); + writel(0xc4, tx2 + QSERDES_V3_TX_LANE_MODE_1); } else { - writel(0xc6, tx + QSERDES_V2_TX_LANE_MODE_1); - writel(0xc6, tx2 + QSERDES_V2_TX_LANE_MODE_1); + writel(0xc6, tx + QSERDES_V3_TX_LANE_MODE_1); + writel(0xc6, tx2 + QSERDES_V3_TX_LANE_MODE_1); } =20 qmp_v2_configure_dp_swing(qmp); @@ -955,12 +955,12 @@ static int qmp_v2_configure_dp_phy(struct qmp_usbc *q= mp) return -ETIMEDOUT; } =20 - writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); - writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); - writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); - writel(0x3f, qmp->dp_tx2 + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); - writel(0x10, qmp->dp_tx2 + QSERDES_V2_TX_HIGHZ_DRVR_EN); - writel(0x0a, qmp->dp_tx2 + QSERDES_V2_TX_TX_POL_INV); + writel(0x3f, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, qmp->dp_tx + QSERDES_V3_TX_TX_POL_INV); + writel(0x3f, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, qmp->dp_tx2 + QSERDES_V3_TX_TX_POL_INV); =20 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); --=20 2.43.0