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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:20 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 1/6] phy: qcom-qmp: Add missing QSERDES COM v2 registers Date: Sat, 14 Mar 2026 13:13:20 +0800 Message-ID: <20260314051325.198137-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: CUGm6h9iBE2U3Qcc3tbuyFKFIaSRFgdA X-Authority-Analysis: v=2.4 cv=QOxlhwLL c=1 sm=1 tr=0 ts=69b4eeae cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=PaEeUX0na0p9oEYLet8A:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: CUGm6h9iBE2U3Qcc3tbuyFKFIaSRFgdA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfXxw3cepAqO+gs B1KtDjh/0i9hLdW7YYz0QbmjUxfWvP+D9ERqWxZIGVZCnBdV19dUqHmTMnak54oJ/dYRTHbGFPm cDC/yl0Wq08VIvxd6+VFkXKLtlTvbPkX+MvciRNRZjlVyDxVBDIhDIfroEzsZkcHF14r2C/UYxx JC0Jp41JQ/mtJZGdRM98YTsKHzBEEbnzP6vQsbViYG2Kf/xNybf7N14MCeOjhILirvxUavwV1BX v1UH/tqGNr9tZe4viZJqp3xgVjz5XEF7MjK1Ojim5ZG9BRcfC3Vv8gvbgudDDg86U51FnaPjWYD TeCXYAt46OWls9DhJpSHm5TyTzfAb0QNpXhcfCI5kpXCUrU0YX/C/vKXWv1DOA+U2ji9v4RnYNy IbiEtCTzMTZGSJZB7yYM9vIQKSlGVo9jd8DrNeBtvp0usT3O53jpZMG87vyv67tpYji4UX+69O/ /WqZwCsm+BE8gos2LQg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" A few registers that could be used by phy-qcom-qmp drivers are missing from qserdes-com-v2 header. Add them. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v2.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v2.h b/drivers/p= hy/qualcomm/phy-qcom-qmp-qserdes-com-v2.h index 3ea1884f35dd..cb599c113189 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v2.h @@ -34,6 +34,7 @@ #define QSERDES_V2_COM_LOCK_CMP3_MODE1 0x060 #define QSERDES_V2_COM_EP_CLOCK_DETECT_CTR 0x068 #define QSERDES_V2_COM_SYSCLK_DET_COMP_STATUS 0x06c +#define QSERDES_V2_COM_BG_TRIM 0x070 #define QSERDES_V2_COM_CLK_EP_DIV 0x074 #define QSERDES_V2_COM_CP_CTRL_MODE0 0x078 #define QSERDES_V2_COM_CP_CTRL_MODE1 0x07c @@ -47,6 +48,7 @@ #define QSERDES_V2_COM_CML_SYSCLK_SEL 0x0b0 #define QSERDES_V2_COM_RESETSM_CNTRL 0x0b4 #define QSERDES_V2_COM_RESETSM_CNTRL2 0x0b8 +#define QSERDES_V2_COM_RESCODE_DIV_NUM 0x0c4 #define QSERDES_V2_COM_LOCK_CMP_EN 0x0c8 #define QSERDES_V2_COM_LOCK_CMP_CFG 0x0cc #define QSERDES_V2_COM_DEC_START_MODE0 0x0d0 @@ -83,6 +85,7 @@ #define QSERDES_V2_COM_RESTRIM_CODE_STATUS 0x164 #define QSERDES_V2_COM_PLLCAL_CODE1_STATUS 0x168 #define QSERDES_V2_COM_PLLCAL_CODE2_STATUS 0x16c +#define QSERDES_V2_COM_BG_CTRL 0x170 #define QSERDES_V2_COM_CLK_SELECT 0x174 #define QSERDES_V2_COM_HSCLK_SEL 0x178 #define QSERDES_V2_COM_INTEGLOOP_BINCODE_STATUS 0x17c --=20 2.43.0 From nobody Tue Apr 7 09:21:03 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D43C2156CA for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:24 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 2/6] phy: qcom-qmp: Use explicit QSERDES COM v2 register definitions Date: Sat, 14 Mar 2026 13:13:21 +0800 Message-ID: <20260314051325.198137-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: CvtiucuIZULy_CH8yxU4tiUvQVChbaK6 X-Proofpoint-ORIG-GUID: CvtiucuIZULy_CH8yxU4tiUvQVChbaK6 X-Authority-Analysis: v=2.4 cv=D9xK6/Rj c=1 sm=1 tr=0 ts=69b4eeb2 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=DJ2Tc-a1hsMvy5d54m8A:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfX7xcZbCNll9/Q d3UtrW5JZAU4Efa1kmwfnDl652yaZ+KbG0f08z/ajYFKB0F3OmVJmj8CkKfDfDZJMMnZy0FfIeD 3+IllisOgAz0lxWTkrG6vhyhDr9Z4BL81ftQ7+h5BmDK5dx/VRINx/OOjEppPyyZ6NeGtLjyxCk BT2SZz3UC2t1w8M38RqM6LfyJVGmj6ZNp+IaMQdPafc+IY11abSzH/bcfFlODiF3v2ZhPdsvheg oSpdqz6LFl44f57aF+gHdgeccx3PgcBCsHgKb1nE+MB3hc7BcHeulTVXcY88VzhFxxwH+riDB8V 6DpH3Uj6FY94/EAVeKke9iXt5H2sXh5p+Oh9DUQ1mt9Ba4QNKVN5Lo64qiCPC8hQ4cEIS/Wwmki TgPpNH/soWEx2RMBdGo1IIhUqRGnYHPjAWbhWI+uQh+IzZWO4ec3d1bTotEZ/Wbymo2IZo1BxeV +2e0PzqSzRtFTFluojg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" As the code comments in the headers say, both qserdes-com and qserdes-com-v2 define QSERDES COM registers for QMP V2 PHY. Switch phy-qcom-qmp drivers to use register definitions in qserdes-com-v2 to make the QSERDES COM version explicit. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 86 ++++---- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 162 +++++++-------- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 194 +++++++++--------- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 188 ++++++++--------- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 180 ++++++++-------- 5 files changed, 405 insertions(+), 405 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy= /qualcomm/phy-qcom-qmp-pcie-msm8996.c index a7c65cfe31df..24b5d66e9ecf 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -59,49 +59,49 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYO= UT_SIZE] =3D { }; =20 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESCODE_DIV_NUM, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESCODE_DIV_NUM, 0x40), }; =20 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fed2fc9bb311..aa2f8da93a02 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -309,46 +309,46 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs= _misc_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0xf), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x6), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0xf), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0xa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x3), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0xD), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xD04), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x33), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0xb), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19), }; =20 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] =3D { @@ -752,47 +752,47 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_p= cie_pcs_misc_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0xf), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x6), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0xf), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0xa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x9), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x3), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0xd), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x35), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0xa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_EP_DIV, 0x19), }; =20 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index df138a5442eb..cb799015c494 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -147,52 +147,52 @@ static const struct qmp_phy_init_tbl milos_ufsphy_pcs= [] =3D { }; =20 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0xd7), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE1, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE1, 0x00), }; =20 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] =3D { @@ -320,60 +320,60 @@ static const struct qmp_phy_init_tbl sc7280_ufsphy_hs= _g4_rx[] =3D { }; =20 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE1, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE1, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE1, 0xd6), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE1, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_INITVAL1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_INITVAL2, 0x00), }; =20 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x44), }; =20 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm= /phy-qcom-qmp-usb.c index b0ecd5ba2464..f43650f9a45c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -244,40 +244,40 @@ static const struct qmp_phy_init_tbl glymur_usb3_unip= hy_pcs_usb_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), /* PLL and Loop filter settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x29), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), /* SSC settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x05), }; =20 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] =3D { @@ -326,40 +326,40 @@ static const struct qmp_phy_init_tbl ipq9574_usb3_pcs= _tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), /* PLL and Loop filter settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), /* SSC settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x07), }; =20 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] =3D { @@ -401,40 +401,40 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs= _tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x04), /* PLL and Loop filter settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), /* SSC settings */ - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x07), }; =20 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 14feb77789b3..1b841e805536 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -177,44 +177,44 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs= _tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), - QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_ADJ_PER2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE1, 0xde), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SSC_STEP_SIZE2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_INITVAL, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CTRL_BY_PSM, 0x01), }; =20 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] =3D { @@ -291,63 +291,63 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs= _tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06), - QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40), - QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08), - QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_CTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x02), }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_rbr[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x21), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr2[] =3D { - QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20), - QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70), - QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_tx_tbl[] =3D { @@ -906,9 +906,9 @@ static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp) writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); =20 - writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL); + writel(0x20, qmp->dp_serdes + QSERDES_V2_COM_RESETSM_CNTRL); =20 - if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_C_READY_STATUS, + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V2_COM_C_READY_STATUS, status, ((status & BIT(0)) > 0), 500, @@ -917,7 +917,7 @@ static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp) return -ETIMEDOUT; } =20 - if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V2_COM_CMN_STATUS, status, ((status & BIT(0)) > 0), 500, @@ -926,7 +926,7 @@ static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp) return -ETIMEDOUT; } =20 - if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V2_COM_CMN_STATUS, status, ((status & BIT(1)) > 0), 500, --=20 2.43.0 From nobody Tue Apr 7 09:21:03 2026 Received: from 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:28 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 3/6] phy: qcom-qmp-usbc: Use register definitions in qserdes-txrx-v3 Date: Sat, 14 Mar 2026 13:13:22 +0800 Message-ID: <20260314051325.198137-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfX/AqReoEs0S4w fEspPqLy6kqC82CJN8gN/t5Yy2SWGI9LH6SsofqCiv/f4h51u0PD18fqAisd072uaFSXC3XTJ5L RAAjQT/ppSb4U5yMSGyzzJb2EBDfqapJVjb7RXI5TC8OUJ8mnfLyqw6/IVcsKbiEp7D+aSRZJhF jNE9N3+VDDgYtZ8DAXnPOuS7qNSLlIl2xYM4/7xhBF3pxrRUFSeq5wtI0SSmqFcMFgxjEcqrt9m 4yJheDpRbGgeszmO9kcLAvJfYcETUocTZerQUjEpgJnMClXrinivyu3fvSBh0CYpP/fwhnQHWzf fZ2XOtws6rNfipOiZGzpu6anTtfUDSc/DO3eE2SES/7tHHmiNXAAGAXSUFP2b7/xnmjSt+UNdBH bUThPgpJbBwJU0BWYNGlXGNpIr4uhcVCH/p9nR13vJzo2dobMXSR6UTjrSUAZGocaTtHdw9gY0Q Hp9cZDOr2KUTqiiSHWQ== X-Authority-Analysis: v=2.4 cv=YLOSCBGx c=1 sm=1 tr=0 ts=69b4eeb6 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=f3I94rbs0dppKun-wmkA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: ECpsvHyoVY2nzDoap2dHSs4kN32JAdpL X-Proofpoint-GUID: ECpsvHyoVY2nzDoap2dHSs4kN32JAdpL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" The register definitions in header qserdes-txrx-v2 and qserdes-txrx-v3 are actually identical. Considering that QSERDES TX/RX v2 is already defined by header qserdes-txrx, qserdes-txrx-v2 is really just a duplication of qserdes-txrx-v3 for QSERDES TX/RX v3. Switch qcom-qmp-usbc driver to use v3 registers. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 64 ++++++++++++------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 1b841e805536..3f8c4280b933 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -351,20 +351,20 @@ static const struct qmp_phy_init_tbl qmp_v2_dp_serdes= _tbl_hbr2[] =3D { }; =20 static const struct qmp_phy_init_tbl qmp_v2_dp_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRANSCEIVER_BIAS_EN, 0x1a), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_VMODE_CTRL1, 0x40), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN, 0x30), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_INTERFACE_SELECT, 0x3d), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_CLKBUF_ENABLE, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_RESET_TSYNC_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TRAN_DRVR_EMP_EN, 0x03), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_EMP_POST1_LVL, 0x2b), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_DRV_LVL, 0x2f), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_BAND, 0x4), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_TX, 0x12), - QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET_RX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), }; =20 struct qmp_usbc_offsets { @@ -809,10 +809,10 @@ static int qmp_v2_configure_dp_swing(struct qmp_usbc = *qmp) if (voltage_swing_cfg =3D=3D 0xff && pre_emphasis_cfg =3D=3D 0xff) return -EINVAL; =20 - writel(voltage_swing_cfg, tx + QSERDES_V2_TX_TX_DRV_LVL); - writel(pre_emphasis_cfg, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL); - writel(voltage_swing_cfg, tx2 + QSERDES_V2_TX_TX_DRV_LVL); - writel(pre_emphasis_cfg, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); =20 return 0; } @@ -871,17 +871,17 @@ static void qmp_v2_configure_dp_tx(struct qmp_usbc *q= mp) void __iomem *tx2 =3D qmp->dp_tx2; =20 /* program default setting first */ - writel(0x2a, tx + QSERDES_V2_TX_TX_DRV_LVL); - writel(0x20, tx + QSERDES_V2_TX_TX_EMP_POST1_LVL); - writel(0x2a, tx2 + QSERDES_V2_TX_TX_DRV_LVL); - writel(0x20, tx2 + QSERDES_V2_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); =20 if (dp_opts->link_rate >=3D 2700) { - writel(0xc4, tx + QSERDES_V2_TX_LANE_MODE_1); - writel(0xc4, tx2 + QSERDES_V2_TX_LANE_MODE_1); + writel(0xc4, tx + QSERDES_V3_TX_LANE_MODE_1); + writel(0xc4, tx2 + QSERDES_V3_TX_LANE_MODE_1); } else { - writel(0xc6, tx + QSERDES_V2_TX_LANE_MODE_1); - writel(0xc6, tx2 + QSERDES_V2_TX_LANE_MODE_1); + writel(0xc6, tx + QSERDES_V3_TX_LANE_MODE_1); + writel(0xc6, tx2 + QSERDES_V3_TX_LANE_MODE_1); } =20 qmp_v2_configure_dp_swing(qmp); @@ -955,12 +955,12 @@ static int qmp_v2_configure_dp_phy(struct qmp_usbc *q= mp) return -ETIMEDOUT; } =20 - writel(0x3f, qmp->dp_tx + QSERDES_V2_TX_TRANSCEIVER_BIAS_EN); - writel(0x10, qmp->dp_tx + QSERDES_V2_TX_HIGHZ_DRVR_EN); - writel(0x0a, qmp->dp_tx + QSERDES_V2_TX_TX_POL_INV); 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:32 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 4/6] phy: qcom-qmp-usbc: Rename QCS615 DP PHY variables and functions Date: Sat, 14 Mar 2026 13:13:23 +0800 Message-ID: <20260314051325.198137-5-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfX0HNklhJ7hlU7 AV+oiegXVA8rfeX5raQBOa4N4aqSCQ4qAw6/0iaEkL8Rs5fnKL0VKcy3ICSqoXJzYC7Pjmqgjsd ZmE4Cris9Ylm2jbPYBnuQOQVC2TnY8XybGEncKuWrM9f6awwLwNi2dHr8P5a7Od28RQ2uFEjHRZ MObkVrHTjQ/6QrDWlViob1Nh0g6hRWaN8H/MHrRCWg7N4/LdnhwA0Dy5LyiY7DFvuPbfUwtQlxA q48HktIueaaHpRP+Lj03oGpvzutQarYZRaB46XJiJWNPmoPuck9w9UvmkWcYWlrHV3Ojqs90bv1 4KAnkZauOGdBva+pM0lPOnt7kSzfiOlJ/FtGQRbQOBUbNo9n0IJtopbqcyuRQBqG9uZ8UNqJnkn C8/39n8oJEM4cWPDQNrtxeJIIcEu2CetPylzBWIaFGifMHbWH8CMhSG7AvCu0F72LdlFSBEev0v HB7cCNQ+slO0kz7uybw== X-Proofpoint-GUID: _pwbYRsF-VQ1_hM_H7zKaOz1pYjl1sR0 X-Authority-Analysis: v=2.4 cv=fLs0HJae c=1 sm=1 tr=0 ts=69b4eeba cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=BQofoxfB7IYdQntn66wA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: _pwbYRsF-VQ1_hM_H7zKaOz1pYjl1sR0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" Commit 81791c45c8e0 ("phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support") chose to name QCS615 DP PHY variables/functions with qmp_v2 prefix, by assuming that QMP PHY registers are versioned as a whole. However, the reality is that the registers are versioned in sub-modules like QSERDES COM and QSERDES TXRX respectively, e.g. QCS615 DP PHY has registers of QSERDES COM v2 and QSERDES TXRX v3. Thus it may cause confusion that qmp_v2_xxx table and functions access QSERDES TXRX v3 registers. Rename QCS615 DP PHY variables and functions to be prefixed by qcs615 instead of qmp_v2. This better aligns with how the driver names USB3 PHY variables for QCM2290 etc. Signed-off-by: Shawn Guo --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 66 ++++++++++++------------ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 3f8c4280b933..edfc1ae68f49 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -290,7 +290,7 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_t= bl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 -static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x37), QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x00), @@ -317,7 +317,7 @@ static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x02), }; =20 -static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_rbr[] =3D { +static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x2c), QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x69), QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -328,7 +328,7 @@ static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_t= bl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), }; =20 -static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr[] =3D { +static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x69), QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -339,7 +339,7 @@ static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_t= bl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), }; =20 -static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_tbl_hbr2[] =3D { +static const struct qmp_phy_init_tbl qcs615_dp_serdes_tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x20), QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x8c), QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00), @@ -350,7 +350,7 @@ static const struct qmp_phy_init_tbl qmp_v2_dp_serdes_t= bl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00), }; =20 -static const struct qmp_phy_init_tbl qmp_v2_dp_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl qcs615_dp_tx_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), @@ -555,14 +555,14 @@ static const struct qmp_usbc_offsets qmp_usbc_usb3dp_= offsets_qcs615 =3D { .dp_dp_phy =3D 0x1000, }; =20 -static const u8 qmp_v2_dp_pre_emphasis_hbr2_rbr[4][4] =3D { +static const u8 qcs615_dp_pre_emphasis_hbr2_rbr[4][4] =3D { {0x00, 0x0b, 0x12, 0xff}, {0x00, 0x0a, 0x12, 0xff}, {0x00, 0x0c, 0xff, 0xff}, {0xff, 0xff, 0xff, 0xff} }; =20 -static const u8 qmp_v2_dp_voltage_swing_hbr2_rbr[4][4] =3D { +static const u8 qcs615_dp_voltage_swing_hbr2_rbr[4][4] =3D { {0x07, 0x0f, 0x14, 0xff}, {0x11, 0x1d, 0x1f, 0xff}, {0x18, 0x1f, 0xff, 0xff}, @@ -641,10 +641,10 @@ static const struct qmp_phy_cfg qcs615_usb3phy_cfg = =3D { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 -static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp); -static void qmp_v2_configure_dp_tx(struct qmp_usbc *qmp); -static int qmp_v2_configure_dp_phy(struct qmp_usbc *qmp); -static int qmp_v2_calibrate_dp_phy(struct qmp_usbc *qmp); +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp); +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp); +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp); +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp); =20 static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg =3D { .offsets =3D &qmp_usbc_usb3dp_offsets_qcs615, @@ -660,25 +660,25 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg= =3D { =20 .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, =20 - .dp_serdes_tbl =3D qmp_v2_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v2_dp_serdes_tbl), - .dp_tx_tbl =3D qmp_v2_dp_tx_tbl, - .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v2_dp_tx_tbl), + .dp_serdes_tbl =3D qcs615_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qcs615_dp_serdes_tbl), + .dp_tx_tbl =3D qcs615_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qcs615_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v2_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v2_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v2_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v2_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v2_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v2_dp_serdes_tbl_hbr2), + .serdes_tbl_rbr =3D qcs615_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qcs615_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qcs615_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qcs615_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qcs615_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qcs615_dp_serdes_tbl_hbr2), =20 - .swing_tbl =3D &qmp_v2_dp_voltage_swing_hbr2_rbr, - .pre_emphasis_tbl =3D &qmp_v2_dp_pre_emphasis_hbr2_rbr, + .swing_tbl =3D &qcs615_dp_voltage_swing_hbr2_rbr, + .pre_emphasis_tbl =3D &qcs615_dp_pre_emphasis_hbr2_rbr, =20 - .dp_aux_init =3D qmp_v2_dp_aux_init, - .configure_dp_tx =3D qmp_v2_configure_dp_tx, - .configure_dp_phy =3D qmp_v2_configure_dp_phy, - .calibrate_dp_phy =3D qmp_v2_calibrate_dp_phy, + .dp_aux_init =3D qcs615_qmp_dp_aux_init, + .configure_dp_tx =3D qcs615_qmp_configure_dp_tx, + .configure_dp_phy =3D qcs615_qmp_configure_dp_phy, + .calibrate_dp_phy =3D qcs615_qmp_calibrate_dp_phy, =20 .reset_list =3D usb3dpphy_reset_l, .num_resets =3D ARRAY_SIZE(usb3dpphy_reset_l), @@ -744,7 +744,7 @@ static int qmp_usbc_com_exit(struct phy *phy) return 0; } =20 -static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp) +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp) { writel(DP_PHY_PD_CTL_AUX_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | @@ -774,7 +774,7 @@ static void qmp_v2_dp_aux_init(struct qmp_usbc *qmp) qmp->dp_dp_phy + QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK); } =20 -static int qmp_v2_configure_dp_swing(struct qmp_usbc *qmp) +static int qcs615_qmp_configure_dp_swing(struct qmp_usbc *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; @@ -864,7 +864,7 @@ static int qmp_usbc_configure_dp_clocks(struct qmp_usbc= *qmp) return 0; } =20 -static void qmp_v2_configure_dp_tx(struct qmp_usbc *qmp) +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp) { const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; void __iomem *tx =3D qmp->dp_tx; @@ -884,10 +884,10 @@ static void qmp_v2_configure_dp_tx(struct qmp_usbc *q= mp) writel(0xc6, tx2 + QSERDES_V3_TX_LANE_MODE_1); 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:36 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 5/6] phy: qcom-qmp: Drop unused register headers Date: Sat, 14 Mar 2026 13:13:24 +0800 Message-ID: <20260314051325.198137-6-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=IsATsb/g c=1 sm=1 tr=0 ts=69b4eebe cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=zYeDregsQ1GP4i_2LSEA:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfX4jT5QSiAGoEP svKzuaLD1h8Aqgx5wXwjjmw9g5qrkYc88x+XqZkt63URMlwGxa9hRO7slR2yHvSzkNuupuVPJME am/ZkJhEvVjn64fVcL8V5AAN465ek82MbmEqagDQThdx5ePepyqLUYYOnXhOZQ18rzTTj55g7sb cPvWu6AWgbtAOhv3Az7rMi6e5QwtNhGPb3iAKK1Tb0J6C8RTXnwrlmZFIXIi0jgy2aCTu7OQ0sE RMvpIbcO0G+BI8y6g4yyiwQNsPDwFwWLRPU6Se5NtTEnlu3v4qVg7zw+smLzx3o2Ar1hY/Un46+ 6rMEkzBhEWJp2QpQsIm8jhjsO9StTd4zoQEuVhA3l126eYMAyuNs8V+Akd7DNk0EJvTwbsx/U4D Q11lJ3VYOcAb6UGq4n7YXqmQNTx/1zrkLAuEEEBeLfK0lqrcij6/5Qcqy2yzxfEbhAPb4/cyRme pV2MpfqNpZZyxsl+nXQ== X-Proofpoint-GUID: iM1EXxm2PhAA9WgalsfzmB0j44Opkfgh X-Proofpoint-ORIG-GUID: iM1EXxm2PhAA9WgalsfzmB0j44Opkfgh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" None of qcom-qmp drivers uses header qserdes-com or qserdes-txrx-v2. Drop them. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 140 ------------------ .../qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h | 68 --------- drivers/phy/qualcomm/phy-qcom-qmp.h | 2 - 3 files changed, 210 deletions(-) delete mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h delete mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/= qualcomm/phy-qcom-qmp-qserdes-com.h deleted file mode 100644 index 7fa5363feeb9..000000000000 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - -#ifndef QCOM_PHY_QMP_QSERDES_COM_H_ -#define QCOM_PHY_QMP_QSERDES_COM_H_ - -/* Only for QMP V2 PHY - QSERDES COM registers */ -#define QSERDES_COM_ATB_SEL1 0x000 -#define QSERDES_COM_ATB_SEL2 0x004 -#define QSERDES_COM_FREQ_UPDATE 0x008 -#define QSERDES_COM_BG_TIMER 0x00c -#define QSERDES_COM_SSC_EN_CENTER 0x010 -#define QSERDES_COM_SSC_ADJ_PER1 0x014 -#define QSERDES_COM_SSC_ADJ_PER2 0x018 -#define QSERDES_COM_SSC_PER1 0x01c -#define QSERDES_COM_SSC_PER2 0x020 -#define QSERDES_COM_SSC_STEP_SIZE1 0x024 -#define QSERDES_COM_SSC_STEP_SIZE2 0x028 -#define QSERDES_COM_POST_DIV 0x02c -#define QSERDES_COM_POST_DIV_MUX 0x030 -#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 -#define QSERDES_COM_CLK_ENABLE1 0x038 -#define QSERDES_COM_SYS_CLK_CTRL 0x03c -#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 -#define QSERDES_COM_PLL_EN 0x044 -#define QSERDES_COM_PLL_IVCO 0x048 -#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c -#define QSERDES_COM_LOCK_CMP2_MODE0 0x050 -#define QSERDES_COM_LOCK_CMP3_MODE0 0x054 -#define QSERDES_COM_LOCK_CMP1_MODE1 0x058 -#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c -#define QSERDES_COM_LOCK_CMP3_MODE1 0x060 -#define QSERDES_COM_LOCK_CMP1_MODE2 0x064 -#define QSERDES_COM_CMN_RSVD0 0x064 -#define QSERDES_COM_LOCK_CMP2_MODE2 0x068 -#define QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x068 -#define QSERDES_COM_LOCK_CMP3_MODE2 0x06c -#define QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x06c -#define QSERDES_COM_BG_TRIM 0x070 -#define QSERDES_COM_CLK_EP_DIV 0x074 -#define QSERDES_COM_CP_CTRL_MODE0 0x078 -#define QSERDES_COM_CP_CTRL_MODE1 0x07c -#define QSERDES_COM_CP_CTRL_MODE2 0x080 -#define QSERDES_COM_CMN_RSVD1 0x080 -#define QSERDES_COM_PLL_RCTRL_MODE0 0x084 -#define QSERDES_COM_PLL_RCTRL_MODE1 0x088 -#define QSERDES_COM_PLL_RCTRL_MODE2 0x08c -#define QSERDES_COM_CMN_RSVD2 0x08c -#define QSERDES_COM_PLL_CCTRL_MODE0 0x090 -#define QSERDES_COM_PLL_CCTRL_MODE1 0x094 -#define QSERDES_COM_PLL_CCTRL_MODE2 0x098 -#define QSERDES_COM_CMN_RSVD3 0x098 -#define QSERDES_COM_PLL_CNTRL 0x09c -#define QSERDES_COM_PHASE_SEL_CTRL 0x0a0 -#define QSERDES_COM_PHASE_SEL_DC 0x0a4 -#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x0a8 -#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 -#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac -#define QSERDES_COM_CML_SYSCLK_SEL 0x0b0 -#define QSERDES_COM_RESETSM_CNTRL 0x0b4 -#define QSERDES_COM_RESETSM_CNTRL2 0x0b8 -#define QSERDES_COM_RESTRIM_CTRL 0x0bc -#define QSERDES_COM_RESTRIM_CTRL2 0x0c0 -#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 -#define QSERDES_COM_LOCK_CMP_EN 0x0c8 -#define QSERDES_COM_LOCK_CMP_CFG 0x0cc -#define QSERDES_COM_DEC_START_MODE0 0x0d0 -#define QSERDES_COM_DEC_START_MODE1 0x0d4 -#define QSERDES_COM_DEC_START_MODE2 0x0d8 -#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0d8 -#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc -#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 -#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 -#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 -#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec -#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 -#define QSERDES_COM_DIV_FRAC_START1_MODE2 0x0f4 -#define QSERDES_COM_VCO_TUNE_MINVAL1 0x0f4 -#define QSERDES_COM_DIV_FRAC_START2_MODE2 0x0f8 -#define QSERDES_COM_VCO_TUNE_MINVAL2 0x0f8 -#define QSERDES_COM_DIV_FRAC_START3_MODE2 0x0fc -#define QSERDES_COM_CMN_RSVD4 0x0fc -#define QSERDES_COM_INTEGLOOP_INITVAL 0x100 -#define QSERDES_COM_INTEGLOOP_EN 0x104 -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x118 -#define QSERDES_COM_VCO_TUNE_MAXVAL1 0x118 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x11c -#define QSERDES_COM_VCO_TUNE_MAXVAL2 0x11c -#define QSERDES_COM_RES_TRIM_CONTROL2 0x120 -#define QSERDES_COM_VCO_TUNE_CTRL 0x124 -#define QSERDES_COM_VCO_TUNE_MAP 0x128 -#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c -#define QSERDES_COM_VCO_TUNE2_MODE0 0x130 -#define QSERDES_COM_VCO_TUNE1_MODE1 0x134 -#define QSERDES_COM_VCO_TUNE2_MODE1 0x138 -#define QSERDES_COM_VCO_TUNE1_MODE2 0x13c -#define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c -#define QSERDES_COM_VCO_TUNE2_MODE2 0x140 -#define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 -#define QSERDES_COM_VCO_TUNE_TIMER1 0x144 -#define QSERDES_COM_VCO_TUNE_TIMER2 0x148 -#define QSERDES_COM_SAR 0x14c -#define QSERDES_COM_SAR_CLK 0x150 -#define QSERDES_COM_SAR_CODE_OUT_STATUS 0x154 -#define QSERDES_COM_SAR_CODE_READY_STATUS 0x158 -#define QSERDES_COM_CMN_STATUS 0x15c -#define QSERDES_COM_RESET_SM_STATUS 0x160 -#define QSERDES_COM_RESTRIM_CODE_STATUS 0x164 -#define QSERDES_COM_PLLCAL_CODE1_STATUS 0x168 -#define QSERDES_COM_PLLCAL_CODE2_STATUS 0x16c -#define QSERDES_COM_BG_CTRL 0x170 -#define QSERDES_COM_CLK_SELECT 0x174 -#define QSERDES_COM_HSCLK_SEL 0x178 -#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x17c -#define QSERDES_COM_PLL_ANALOG 0x180 -#define QSERDES_COM_CORECLK_DIV 0x184 -#define QSERDES_COM_SW_RESET 0x188 -#define QSERDES_COM_CORE_CLK_EN 0x18c -#define QSERDES_COM_C_READY_STATUS 0x190 -#define QSERDES_COM_CMN_CONFIG 0x194 -#define QSERDES_COM_CMN_RATE_OVERRIDE 0x198 -#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c -#define QSERDES_COM_DEBUG_BUS0 0x1a0 -#define QSERDES_COM_DEBUG_BUS1 0x1a4 -#define QSERDES_COM_DEBUG_BUS2 0x1a8 -#define QSERDES_COM_DEBUG_BUS3 0x1ac -#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 -#define QSERDES_COM_CMN_MISC1 0x1b4 -#define QSERDES_COM_CMN_MISC2 0x1b8 -#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc -#define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0 -#define QSERDES_COM_CMN_RSVD5 0x1c4 - -#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h b/drivers/= phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h deleted file mode 100644 index 34919720b7bc..000000000000 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - -#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V2_H_ -#define QCOM_PHY_QMP_QSERDES_TXRX_V2_H_ - -/* Only for QMP V2 PHY - TX registers */ -#define QSERDES_V2_TX_BIST_MODE_LANENO 0x000 -#define QSERDES_V2_TX_CLKBUF_ENABLE 0x008 -#define QSERDES_V2_TX_TX_EMP_POST1_LVL 0x00c -#define QSERDES_V2_TX_TX_DRV_LVL 0x01c -#define QSERDES_V2_TX_RESET_TSYNC_EN 0x024 -#define QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN 0x028 -#define QSERDES_V2_TX_TX_BAND 0x02c -#define QSERDES_V2_TX_SLEW_CNTL 0x030 -#define QSERDES_V2_TX_INTERFACE_SELECT 0x034 -#define QSERDES_V2_TX_RES_CODE_LANE_TX 0x03c -#define QSERDES_V2_TX_RES_CODE_LANE_RX 0x040 -#define QSERDES_V2_TX_RES_CODE_LANE_OFFSET_TX 0x044 -#define QSERDES_V2_TX_RES_CODE_LANE_OFFSET_RX 0x048 -#define QSERDES_V2_TX_DEBUG_BUS_SEL 0x058 -#define QSERDES_V2_TX_TRANSCEIVER_BIAS_EN 0x05c -#define QSERDES_V2_TX_HIGHZ_DRVR_EN 0x060 -#define QSERDES_V2_TX_TX_POL_INV 0x064 -#define QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 -#define QSERDES_V2_TX_LANE_MODE_1 0x08c -#define QSERDES_V2_TX_LANE_MODE_2 0x090 -#define QSERDES_V2_TX_LANE_MODE_3 0x094 -#define QSERDES_V2_TX_RCV_DETECT_LVL_2 0x0a4 -#define QSERDES_V2_TX_TRAN_DRVR_EMP_EN 0x0c0 -#define QSERDES_V2_TX_TX_INTERFACE_MODE 0x0c4 -#define QSERDES_V2_TX_VMODE_CTRL1 0x0f0 - -/* Only for QMP V2 PHY - RX registers */ -#define QSERDES_V2_RX_UCDR_FO_GAIN 0x008 -#define QSERDES_V2_RX_UCDR_SO_GAIN_HALF 0x00c -#define QSERDES_V2_RX_UCDR_SO_GAIN 0x014 -#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_HALF 0x024 -#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 -#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN 0x02c -#define QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN 0x030 -#define QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 -#define QSERDES_V2_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c -#define QSERDES_V2_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 -#define QSERDES_V2_RX_UCDR_PI_CONTROLS 0x044 -#define QSERDES_V2_RX_RX_TERM_BW 0x07c -#define QSERDES_V2_RX_VGA_CAL_CNTRL1 0x0bc -#define QSERDES_V2_RX_VGA_CAL_CNTRL2 0x0c0 -#define QSERDES_V2_RX_RX_EQ_GAIN2_LSB 0x0c8 -#define QSERDES_V2_RX_RX_EQ_GAIN2_MSB 0x0cc -#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d0 -#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 -#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 -#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc -#define QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 -#define QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc -#define QSERDES_V2_RX_SIGDET_ENABLES 0x100 -#define QSERDES_V2_RX_SIGDET_CNTRL 0x104 -#define QSERDES_V2_RX_SIGDET_LVL 0x108 -#define QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL 0x10c -#define QSERDES_V2_RX_RX_BAND 0x110 -#define QSERDES_V2_RX_RX_INTERFACE_MODE 0x11c -#define QSERDES_V2_RX_RX_MODE_00 0x164 -#define QSERDES_V2_RX_RX_MODE_01 0x168 - -#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index a873bdd7bffe..19e91f44e84e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -6,11 +6,9 @@ #ifndef QCOM_PHY_QMP_H_ #define QCOM_PHY_QMP_H_ =20 -#include "phy-qcom-qmp-qserdes-com.h" #include "phy-qcom-qmp-qserdes-txrx.h" =20 #include "phy-qcom-qmp-qserdes-com-v2.h" -#include "phy-qcom-qmp-qserdes-txrx-v2.h" =20 #include "phy-qcom-qmp-qserdes-com-v3.h" #include "phy-qcom-qmp-qserdes-txrx-v3.h" --=20 2.43.0 From nobody Tue Apr 7 09:21:03 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 084622FE078 for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2c098cbd4dasm1784045eec.0.2026.03.13.22.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 22:14:40 -0700 (PDT) From: Shawn Guo To: Vinod Koul Cc: Neil Armstrong , Dmitry Baryshkov , Abel Vesa , Konrad Dybcio , Xiangxu Yin , Manivannan Sadhasivam , Luca Weiss , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, Shawn Guo Subject: [PATCH 6/6] phy: qcom-qmp: Make QSERDES TXRX v2 registers explicit Date: Sat, 14 Mar 2026 13:13:25 +0800 Message-ID: <20260314051325.198137-7-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> References: <20260314051325.198137-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: WowyBY-dOF1ao57T7jOiltQ-dF_kxkF9 X-Proofpoint-ORIG-GUID: WowyBY-dOF1ao57T7jOiltQ-dF_kxkF9 X-Authority-Analysis: v=2.4 cv=D9xK6/Rj c=1 sm=1 tr=0 ts=69b4eec2 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=HmBPgOZM63ur2ZWdtjIA:9 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE0MDAzOCBTYWx0ZWRfX3bLiw0MkCMdL 41FIKvtSWYUJphCUOSMBFXs1RwiLvz7xIP5K9lEie3kg0+NLHYbtYo75cEZoGJ8cY0xB83fYjTA uq/K36xrnoVROuylkIp/asmCZIJAlSmnMZPWVWfinyU7o1ok2aLDrlL5oP6f0qN/ROayonm1dy/ Xs6/IaKn4qB7wxwDaaXI6a6CsBxBvNlGNYyFkmyhE0aog5QnTzKH7wmHB8K7uEtH5LARbgp4uOx 6FAnfU8eBRRbXZeioWiybBRoKezb+2wm9yTCMHYiKraSLUgWfMxrmMhkoLh6QOs1AwDMjJyT5F3 Q8Oiqn+b/GOoxUV2X6aTV1LuyJPAQLMdYMJY2qxspIuabagwrxr6mWpHSOFGQlwDWzGA6GC0Bcl 9ra9ESsMSNcWMY+UuF/wotL+GCxfvs30yA4KhY9hFK0mFRzjygqR47G+WnsiuDbptM8dGXxkp4l oBb0C2qwurTlOKv7XUg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-14_01,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603140038 Content-Type: text/plain; charset="utf-8" Rename QSERDES TXRX v2 registers and the header to make version explicit. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 24 +- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 50 ++--- .../qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h | 205 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h | 205 ------------------ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 60 ++--- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 74 +++---- drivers/phy/qualcomm/phy-qcom-qmp.h | 3 +- 7 files changed, 310 insertions(+), 311 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h delete mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy= /qualcomm/phy-qcom-qmp-pcie-msm8996.c index 24b5d66e9ecf..37e96493b722 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -105,21 +105,21 @@ static const struct qmp_phy_init_tbl msm8996_pcie_ser= des_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06), }; =20 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x19), }; =20 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index aa2f8da93a02..75afbd15aaf4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -352,22 +352,22 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_ser= des_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), - QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), - QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), - QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x6), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_TX_EMP_POST1_LVL, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_SLEW_CNTL, 0x0a), }; =20 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x4), }; =20 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] =3D { @@ -796,21 +796,21 @@ static const struct qmp_phy_init_tbl qcs615_pcie_serd= es_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN_HALF, 0x4), }; =20 static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), - QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), - QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x6), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_RES_CODE_LANE_OFFSET, 0x2), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), }; =20 static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h b/drivers/= phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h new file mode 100644 index 000000000000..9ae0cf95e317 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v2.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V2_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V2_H_ + +/* Only for QMP V2 PHY - TX registers */ +#define QSERDES_V2_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V2_TX_BIST_INVERT 0x004 +#define QSERDES_V2_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V2_TX_CMN_CONTROL_ONE 0x00c +#define QSERDES_V2_TX_CMN_CONTROL_TWO 0x010 +#define QSERDES_V2_TX_CMN_CONTROL_THREE 0x014 +#define QSERDES_V2_TX_TX_EMP_POST1_LVL 0x018 +#define QSERDES_V2_TX_TX_POST2_EMPH 0x01c +#define QSERDES_V2_TX_TX_BOOST_LVL_UP_DN 0x020 +#define QSERDES_V2_TX_HP_PD_ENABLES 0x024 +#define QSERDES_V2_TX_TX_IDLE_LVL_LARGE_AMP 0x028 +#define QSERDES_V2_TX_TX_DRV_LVL 0x02c +#define QSERDES_V2_TX_TX_DRV_LVL_OFFSET 0x030 +#define QSERDES_V2_TX_RESET_TSYNC_EN 0x034 +#define QSERDES_V2_TX_PRE_STALL_LDO_BOOST_EN 0x038 +#define QSERDES_V2_TX_TX_BAND 0x03c +#define QSERDES_V2_TX_SLEW_CNTL 0x040 +#define QSERDES_V2_TX_INTERFACE_SELECT 0x044 +#define QSERDES_V2_TX_LPB_EN 0x048 +#define QSERDES_V2_TX_RES_CODE_LANE_TX 0x04c +#define QSERDES_V2_TX_RES_CODE_LANE_RX 0x050 +#define QSERDES_V2_TX_RES_CODE_LANE_OFFSET 0x054 +#define QSERDES_V2_TX_PERL_LENGTH1 0x058 +#define QSERDES_V2_TX_PERL_LENGTH2 0x05c +#define QSERDES_V2_TX_SERDES_BYP_EN_OUT 0x060 +#define QSERDES_V2_TX_DEBUG_BUS_SEL 0x064 +#define QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 +#define QSERDES_V2_TX_TX_POL_INV 0x06c +#define QSERDES_V2_TX_PARRATE_REC_DETECT_IDLE_EN 0x070 +#define QSERDES_V2_TX_BIST_PATTERN1 0x074 +#define QSERDES_V2_TX_BIST_PATTERN2 0x078 +#define QSERDES_V2_TX_BIST_PATTERN3 0x07c +#define QSERDES_V2_TX_BIST_PATTERN4 0x080 +#define QSERDES_V2_TX_BIST_PATTERN5 0x084 +#define QSERDES_V2_TX_BIST_PATTERN6 0x088 +#define QSERDES_V2_TX_BIST_PATTERN7 0x08c +#define QSERDES_V2_TX_BIST_PATTERN8 0x090 +#define QSERDES_V2_TX_LANE_MODE 0x094 +#define QSERDES_V2_TX_IDAC_CAL_LANE_MODE 0x098 +#define QSERDES_V2_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c +#define QSERDES_V2_TX_ATB_SEL1 0x0a0 +#define QSERDES_V2_TX_ATB_SEL2 0x0a4 +#define QSERDES_V2_TX_RCV_DETECT_LVL 0x0a8 +#define QSERDES_V2_TX_RCV_DETECT_LVL_2 0x0ac +#define QSERDES_V2_TX_PRBS_SEED1 0x0b0 +#define QSERDES_V2_TX_PRBS_SEED2 0x0b4 +#define QSERDES_V2_TX_PRBS_SEED3 0x0b8 +#define QSERDES_V2_TX_PRBS_SEED4 0x0bc +#define QSERDES_V2_TX_RESET_GEN 0x0c0 +#define QSERDES_V2_TX_RESET_GEN_MUXES 0x0c4 +#define QSERDES_V2_TX_TRAN_DRVR_EMP_EN 0x0c8 +#define QSERDES_V2_TX_TX_INTERFACE_MODE 0x0cc +#define QSERDES_V2_TX_PWM_CTRL 0x0d0 +#define QSERDES_V2_TX_PWM_ENCODED_OR_DATA 0x0d4 +#define QSERDES_V2_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d8 +#define QSERDES_V2_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc +#define QSERDES_V2_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e0 +#define QSERDES_V2_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e4 +#define QSERDES_V2_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e8 +#define QSERDES_V2_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec +#define QSERDES_V2_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f0 +#define QSERDES_V2_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f4 +#define QSERDES_V2_TX_VMODE_CTRL1 0x0f8 +#define QSERDES_V2_TX_VMODE_CTRL2 0x0fc +#define QSERDES_V2_TX_TX_ALOG_INTF_OBSV_CNTL 0x100 +#define QSERDES_V2_TX_BIST_STATUS 0x104 +#define QSERDES_V2_TX_BIST_ERROR_COUNT1 0x108 +#define QSERDES_V2_TX_BIST_ERROR_COUNT2 0x10c +#define QSERDES_V2_TX_TX_ALOG_INTF_OBSV 0x110 + +/* Only for QMP V2 PHY - RX registers */ +#define QSERDES_V2_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_V2_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_V2_RX_UCDR_FO_GAIN_EIGHTH 0x008 +#define QSERDES_V2_RX_UCDR_FO_GAIN 0x00c +#define QSERDES_V2_RX_UCDR_SO_GAIN_HALF 0x010 +#define QSERDES_V2_RX_UCDR_SO_GAIN_QUARTER 0x014 +#define QSERDES_V2_RX_UCDR_SO_GAIN_EIGHTH 0x018 +#define QSERDES_V2_RX_UCDR_SO_GAIN 0x01c +#define QSERDES_V2_RX_UCDR_SVS_FO_GAIN_HALF 0x020 +#define QSERDES_V2_RX_UCDR_SVS_FO_GAIN_QUARTER 0x024 +#define QSERDES_V2_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x028 +#define QSERDES_V2_RX_UCDR_SVS_FO_GAIN 0x02c +#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_HALF 0x030 +#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 +#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 +#define QSERDES_V2_RX_UCDR_SVS_SO_GAIN 0x03c +#define QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN 0x040 +#define QSERDES_V2_RX_UCDR_FD_GAIN 0x044 +#define QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 +#define QSERDES_V2_RX_UCDR_FO_TO_SO_DELAY 0x04c +#define QSERDES_V2_RX_UCDR_FASTLOCK_COUNT_LOW 0x050 +#define QSERDES_V2_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054 +#define QSERDES_V2_RX_UCDR_MODULATE 0x058 +#define QSERDES_V2_RX_UCDR_PI_CONTROLS 0x05c +#define QSERDES_V2_RX_RBIST_CONTROL 0x060 +#define QSERDES_V2_RX_AUX_CONTROL 0x064 +#define QSERDES_V2_RX_AUX_DATA_TCOARSE 0x068 +#define QSERDES_V2_RX_AUX_DATA_TFINE_LSB 0x06c +#define QSERDES_V2_RX_AUX_DATA_TFINE_MSB 0x070 +#define QSERDES_V2_RX_RCLK_AUXDATA_SEL 0x074 +#define QSERDES_V2_RX_AC_JTAG_ENABLE 0x078 +#define QSERDES_V2_RX_AC_JTAG_INITP 0x07c +#define QSERDES_V2_RX_AC_JTAG_INITN 0x080 +#define QSERDES_V2_RX_AC_JTAG_LVL 0x084 +#define QSERDES_V2_RX_AC_JTAG_MODE 0x088 +#define QSERDES_V2_RX_AC_JTAG_RESET 0x08c +#define QSERDES_V2_RX_RX_TERM_BW 0x090 +#define QSERDES_V2_RX_RX_RCVR_IQ_EN 0x094 +#define QSERDES_V2_RX_RX_IDAC_I_DC_OFFSETS 0x098 +#define QSERDES_V2_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c +#define QSERDES_V2_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0 +#define QSERDES_V2_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4 +#define QSERDES_V2_RX_RX_IDAC_A_DC_OFFSETS 0x0a8 +#define QSERDES_V2_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac +#define QSERDES_V2_RX_RX_IDAC_EN 0x0b0 +#define QSERDES_V2_RX_RX_IDAC_ENABLES 0x0b4 +#define QSERDES_V2_RX_RX_IDAC_SIGN 0x0b8 +#define QSERDES_V2_RX_RX_HIGHZ_HIGHRATE 0x0bc +#define QSERDES_V2_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0 +#define QSERDES_V2_RX_RX_EQ_GAIN1_LSB 0x0c4 +#define QSERDES_V2_RX_RX_EQ_GAIN1_MSB 0x0c8 +#define QSERDES_V2_RX_RX_EQ_GAIN2_LSB 0x0cc +#define QSERDES_V2_RX_RX_EQ_GAIN2_MSB 0x0d0 +#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4 +#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 +#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc +#define QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 +#define QSERDES_V2_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4 +#define QSERDES_V2_RX_RX_IDAC_TSETTLE_LOW 0x0e8 +#define QSERDES_V2_RX_RX_IDAC_TSETTLE_HIGH 0x0ec +#define QSERDES_V2_RX_RX_IDAC_ENDSAMP_LOW 0x0f0 +#define QSERDES_V2_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4 +#define QSERDES_V2_RX_RX_IDAC_MIDPOINT_LOW 0x0f8 +#define QSERDES_V2_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc +#define QSERDES_V2_RX_RX_EQ_OFFSET_LSB 0x100 +#define QSERDES_V2_RX_RX_EQ_OFFSET_MSB 0x104 +#define QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 +#define QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c +#define QSERDES_V2_RX_SIGDET_ENABLES 0x110 +#define QSERDES_V2_RX_SIGDET_CNTRL 0x114 +#define QSERDES_V2_RX_SIGDET_LVL 0x118 +#define QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL 0x11c +#define QSERDES_V2_RX_RX_BAND 0x120 +#define QSERDES_V2_RX_CDR_FREEZE_UP_DN 0x124 +#define QSERDES_V2_RX_CDR_RESET_OVERRIDE 0x128 +#define QSERDES_V2_RX_RX_INTERFACE_MODE 0x12c +#define QSERDES_V2_RX_JITTER_GEN_MODE 0x130 +#define QSERDES_V2_RX_BUJ_AMP 0x134 +#define QSERDES_V2_RX_SJ_AMP1 0x138 +#define QSERDES_V2_RX_SJ_AMP2 0x13c +#define QSERDES_V2_RX_SJ_PER1 0x140 +#define QSERDES_V2_RX_SJ_PER2 0x144 +#define QSERDES_V2_RX_BUJ_STEP_FREQ1 0x148 +#define QSERDES_V2_RX_BUJ_STEP_FREQ2 0x14c +#define QSERDES_V2_RX_PPM_OFFSET1 0x150 +#define QSERDES_V2_RX_PPM_OFFSET2 0x154 +#define QSERDES_V2_RX_SIGN_PPM_PERIOD1 0x158 +#define QSERDES_V2_RX_SIGN_PPM_PERIOD2 0x15c +#define QSERDES_V2_RX_SSC_CTRL 0x160 +#define QSERDES_V2_RX_SSC_COUNT1 0x164 +#define QSERDES_V2_RX_SSC_COUNT2 0x168 +#define QSERDES_V2_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c +#define QSERDES_V2_RX_RX_PWM_ENABLE_AND_DATA 0x170 +#define QSERDES_V2_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174 +#define QSERDES_V2_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178 +#define QSERDES_V2_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c +#define QSERDES_V2_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180 +#define QSERDES_V2_RX_PI_CTRL1 0x184 +#define QSERDES_V2_RX_PI_CTRL2 0x188 +#define QSERDES_V2_RX_PI_QUAD 0x18c +#define QSERDES_V2_RX_IDATA1 0x190 +#define QSERDES_V2_RX_IDATA2 0x194 +#define QSERDES_V2_RX_AUX_DATA1 0x198 +#define QSERDES_V2_RX_AUX_DATA2 0x19c +#define QSERDES_V2_RX_AC_JTAG_OUTP 0x1a0 +#define QSERDES_V2_RX_AC_JTAG_OUTN 0x1a4 +#define QSERDES_V2_RX_RX_SIGDET 0x1a8 +#define QSERDES_V2_RX_RX_VDCOFF 0x1ac +#define QSERDES_V2_RX_IDAC_CAL_ON 0x1b0 +#define QSERDES_V2_RX_IDAC_STATUS_I 0x1b4 +#define QSERDES_V2_RX_IDAC_STATUS_IBAR 0x1b8 +#define QSERDES_V2_RX_IDAC_STATUS_Q 0x1bc +#define QSERDES_V2_RX_IDAC_STATUS_QBAR 0x1c0 +#define QSERDES_V2_RX_IDAC_STATUS_A 0x1c4 +#define QSERDES_V2_RX_IDAC_STATUS_ABAR 0x1c8 +#define QSERDES_V2_RX_CALST_STATUS_I 0x1cc +#define QSERDES_V2_RX_CALST_STATUS_Q 0x1d0 +#define QSERDES_V2_RX_CALST_STATUS_A 0x1d4 +#define QSERDES_V2_RX_RX_ALOG_INTF_OBSV 0x1d8 +#define QSERDES_V2_RX_READ_EQCODE 0x1dc +#define QSERDES_V2_RX_READ_OFFSETCODE 0x1e0 +#define QSERDES_V2_RX_IA_ERROR_COUNTER_LOW 0x1e4 +#define QSERDES_V2_RX_IA_ERROR_COUNTER_HIGH 0x1e8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy= /qualcomm/phy-qcom-qmp-qserdes-txrx.h deleted file mode 100644 index d20694513eb4..000000000000 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. - */ - -#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_ -#define QCOM_PHY_QMP_QSERDES_TXRX_H_ - -/* Only for QMP V2 PHY - TX registers */ -#define QSERDES_TX_BIST_MODE_LANENO 0x000 -#define QSERDES_TX_BIST_INVERT 0x004 -#define QSERDES_TX_CLKBUF_ENABLE 0x008 -#define QSERDES_TX_CMN_CONTROL_ONE 0x00c -#define QSERDES_TX_CMN_CONTROL_TWO 0x010 -#define QSERDES_TX_CMN_CONTROL_THREE 0x014 -#define QSERDES_TX_TX_EMP_POST1_LVL 0x018 -#define QSERDES_TX_TX_POST2_EMPH 0x01c -#define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020 -#define QSERDES_TX_HP_PD_ENABLES 0x024 -#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x028 -#define QSERDES_TX_TX_DRV_LVL 0x02c -#define QSERDES_TX_TX_DRV_LVL_OFFSET 0x030 -#define QSERDES_TX_RESET_TSYNC_EN 0x034 -#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x038 -#define QSERDES_TX_TX_BAND 0x03c -#define QSERDES_TX_SLEW_CNTL 0x040 -#define QSERDES_TX_INTERFACE_SELECT 0x044 -#define QSERDES_TX_LPB_EN 0x048 -#define QSERDES_TX_RES_CODE_LANE_TX 0x04c -#define QSERDES_TX_RES_CODE_LANE_RX 0x050 -#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 -#define QSERDES_TX_PERL_LENGTH1 0x058 -#define QSERDES_TX_PERL_LENGTH2 0x05c -#define QSERDES_TX_SERDES_BYP_EN_OUT 0x060 -#define QSERDES_TX_DEBUG_BUS_SEL 0x064 -#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 -#define QSERDES_TX_TX_POL_INV 0x06c -#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x070 -#define QSERDES_TX_BIST_PATTERN1 0x074 -#define QSERDES_TX_BIST_PATTERN2 0x078 -#define QSERDES_TX_BIST_PATTERN3 0x07c -#define QSERDES_TX_BIST_PATTERN4 0x080 -#define QSERDES_TX_BIST_PATTERN5 0x084 -#define QSERDES_TX_BIST_PATTERN6 0x088 -#define QSERDES_TX_BIST_PATTERN7 0x08c -#define QSERDES_TX_BIST_PATTERN8 0x090 -#define QSERDES_TX_LANE_MODE 0x094 -#define QSERDES_TX_IDAC_CAL_LANE_MODE 0x098 -#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x09c -#define QSERDES_TX_ATB_SEL1 0x0a0 -#define QSERDES_TX_ATB_SEL2 0x0a4 -#define QSERDES_TX_RCV_DETECT_LVL 0x0a8 -#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac -#define QSERDES_TX_PRBS_SEED1 0x0b0 -#define QSERDES_TX_PRBS_SEED2 0x0b4 -#define QSERDES_TX_PRBS_SEED3 0x0b8 -#define QSERDES_TX_PRBS_SEED4 0x0bc -#define QSERDES_TX_RESET_GEN 0x0c0 -#define QSERDES_TX_RESET_GEN_MUXES 0x0c4 -#define QSERDES_TX_TRAN_DRVR_EMP_EN 0x0c8 -#define QSERDES_TX_TX_INTERFACE_MODE 0x0cc -#define QSERDES_TX_PWM_CTRL 0x0d0 -#define QSERDES_TX_PWM_ENCODED_OR_DATA 0x0d4 -#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0d8 -#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0dc -#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0e0 -#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0e4 -#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0e8 -#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0ec -#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0f0 -#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0f4 -#define QSERDES_TX_VMODE_CTRL1 0x0f8 -#define QSERDES_TX_VMODE_CTRL2 0x0fc -#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL 0x100 -#define QSERDES_TX_BIST_STATUS 0x104 -#define QSERDES_TX_BIST_ERROR_COUNT1 0x108 -#define QSERDES_TX_BIST_ERROR_COUNT2 0x10c -#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x110 - -/* Only for QMP V2 PHY - RX registers */ -#define QSERDES_RX_UCDR_FO_GAIN_HALF 0x000 -#define QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x004 -#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH 0x008 -#define QSERDES_RX_UCDR_FO_GAIN 0x00c -#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 -#define QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x014 -#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH 0x018 -#define QSERDES_RX_UCDR_SO_GAIN 0x01c -#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x020 -#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x024 -#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH 0x028 -#define QSERDES_RX_UCDR_SVS_FO_GAIN 0x02c -#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030 -#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 -#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 -#define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c -#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 -#define QSERDES_RX_UCDR_FD_GAIN 0x044 -#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 -#define QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x04c -#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x050 -#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x054 -#define QSERDES_RX_UCDR_MODULATE 0x058 -#define QSERDES_RX_UCDR_PI_CONTROLS 0x05c -#define QSERDES_RX_RBIST_CONTROL 0x060 -#define QSERDES_RX_AUX_CONTROL 0x064 -#define QSERDES_RX_AUX_DATA_TCOARSE 0x068 -#define QSERDES_RX_AUX_DATA_TFINE_LSB 0x06c -#define QSERDES_RX_AUX_DATA_TFINE_MSB 0x070 -#define QSERDES_RX_RCLK_AUXDATA_SEL 0x074 -#define QSERDES_RX_AC_JTAG_ENABLE 0x078 -#define QSERDES_RX_AC_JTAG_INITP 0x07c -#define QSERDES_RX_AC_JTAG_INITN 0x080 -#define QSERDES_RX_AC_JTAG_LVL 0x084 -#define QSERDES_RX_AC_JTAG_MODE 0x088 -#define QSERDES_RX_AC_JTAG_RESET 0x08c -#define QSERDES_RX_RX_TERM_BW 0x090 -#define QSERDES_RX_RX_RCVR_IQ_EN 0x094 -#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x098 -#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x09c -#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0a0 -#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0a4 -#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0a8 -#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x0ac -#define QSERDES_RX_RX_IDAC_EN 0x0b0 -#define QSERDES_RX_RX_IDAC_ENABLES 0x0b4 -#define QSERDES_RX_RX_IDAC_SIGN 0x0b8 -#define QSERDES_RX_RX_HIGHZ_HIGHRATE 0x0bc -#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0c0 -#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 -#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 -#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc -#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x0d4 -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 -#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION 0x0e4 -#define QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x0e8 -#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x0ec -#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW 0x0f0 -#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH 0x0f4 -#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW 0x0f8 -#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH 0x0fc -#define QSERDES_RX_RX_EQ_OFFSET_LSB 0x100 -#define QSERDES_RX_RX_EQ_OFFSET_MSB 0x104 -#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 -#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c -#define QSERDES_RX_SIGDET_ENABLES 0x110 -#define QSERDES_RX_SIGDET_CNTRL 0x114 -#define QSERDES_RX_SIGDET_LVL 0x118 -#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c -#define QSERDES_RX_RX_BAND 0x120 -#define QSERDES_RX_CDR_FREEZE_UP_DN 0x124 -#define QSERDES_RX_CDR_RESET_OVERRIDE 0x128 -#define QSERDES_RX_RX_INTERFACE_MODE 0x12c -#define QSERDES_RX_JITTER_GEN_MODE 0x130 -#define QSERDES_RX_BUJ_AMP 0x134 -#define QSERDES_RX_SJ_AMP1 0x138 -#define QSERDES_RX_SJ_AMP2 0x13c -#define QSERDES_RX_SJ_PER1 0x140 -#define QSERDES_RX_SJ_PER2 0x144 -#define QSERDES_RX_BUJ_STEP_FREQ1 0x148 -#define QSERDES_RX_BUJ_STEP_FREQ2 0x14c -#define QSERDES_RX_PPM_OFFSET1 0x150 -#define QSERDES_RX_PPM_OFFSET2 0x154 -#define QSERDES_RX_SIGN_PPM_PERIOD1 0x158 -#define QSERDES_RX_SIGN_PPM_PERIOD2 0x15c -#define QSERDES_RX_SSC_CTRL 0x160 -#define QSERDES_RX_SSC_COUNT1 0x164 -#define QSERDES_RX_SSC_COUNT2 0x168 -#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL 0x16c -#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x170 -#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x174 -#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x178 -#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x17c -#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x180 -#define QSERDES_RX_PI_CTRL1 0x184 -#define QSERDES_RX_PI_CTRL2 0x188 -#define QSERDES_RX_PI_QUAD 0x18c -#define QSERDES_RX_IDATA1 0x190 -#define QSERDES_RX_IDATA2 0x194 -#define QSERDES_RX_AUX_DATA1 0x198 -#define QSERDES_RX_AUX_DATA2 0x19c -#define QSERDES_RX_AC_JTAG_OUTP 0x1a0 -#define QSERDES_RX_AC_JTAG_OUTN 0x1a4 -#define QSERDES_RX_RX_SIGDET 0x1a8 -#define QSERDES_RX_RX_VDCOFF 0x1ac -#define QSERDES_RX_IDAC_CAL_ON 0x1b0 -#define QSERDES_RX_IDAC_STATUS_I 0x1b4 -#define QSERDES_RX_IDAC_STATUS_IBAR 0x1b8 -#define QSERDES_RX_IDAC_STATUS_Q 0x1bc -#define QSERDES_RX_IDAC_STATUS_QBAR 0x1c0 -#define QSERDES_RX_IDAC_STATUS_A 0x1c4 -#define QSERDES_RX_IDAC_STATUS_ABAR 0x1c8 -#define QSERDES_RX_CALST_STATUS_I 0x1cc -#define QSERDES_RX_CALST_STATUS_Q 0x1d0 -#define QSERDES_RX_CALST_STATUS_A 0x1d4 -#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x1d8 -#define QSERDES_RX_READ_EQCODE 0x1dc -#define QSERDES_RX_READ_OFFSETCODE 0x1e0 -#define QSERDES_RX_IA_ERROR_COUNTER_LOW 0x1e4 -#define QSERDES_RX_IA_ERROR_COUNTER_HIGH 0x1e8 - -#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index cb799015c494..a4ec2d37ea91 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -196,22 +196,22 @@ static const struct qmp_phy_init_tbl msm8996_ufsphy_s= erdes[] =3D { }; =20 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x02), }; =20 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_TERM_BW, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_MSB, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_MSB, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; =20 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] =3D { @@ -377,26 +377,26 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_hs= _b_serdes[] =3D { }; =20 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06), }; =20 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x0F), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_INTERFACE_MODE, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_TERM_BW, 0x5B), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_LSB, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_MSB, 0x3F), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_LSB, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_MSB, 0x3F), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SVS_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; =20 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm= /phy-qcom-qmp-usb.c index f43650f9a45c..c5507168e135 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -248,7 +248,7 @@ static const struct qmp_phy_init_tbl ipq9574_usb3_serde= s_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), @@ -281,22 +281,22 @@ static const struct qmp_phy_init_tbl ipq9574_usb3_ser= des_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06), }; =20 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x0c), }; =20 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] =3D { @@ -330,7 +330,7 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_serde= s_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08), QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x01), QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x06), @@ -363,15 +363,15 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_ser= des_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_ENABLES, 0x0), }; =20 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] =3D { @@ -438,22 +438,22 @@ static const struct qmp_phy_init_tbl msm8996_usb3_ser= des_tbl[] =3D { }; =20 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), - QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), - QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06), }; =20 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] =3D { - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), - QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), - QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), - QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x16), }; =20 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index 19e91f44e84e..11b7e03b4fab 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -6,9 +6,8 @@ #ifndef QCOM_PHY_QMP_H_ #define QCOM_PHY_QMP_H_ =20 -#include "phy-qcom-qmp-qserdes-txrx.h" - #include "phy-qcom-qmp-qserdes-com-v2.h" +#include "phy-qcom-qmp-qserdes-txrx-v2.h" =20 #include "phy-qcom-qmp-qserdes-com-v3.h" #include "phy-qcom-qmp-qserdes-txrx-v3.h" --=20 2.43.0