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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ec94sm18454261fa.22.2026.03.14.02.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Mar 2026 02:22:25 -0700 (PDT) From: Marcus Folkesson Date: Sat, 14 Mar 2026 10:22:40 +0100 Subject: [PATCH v8 1/5] i2c: core: add callback to change bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260314-i2c-mux-v8-1-fb1738a4df0a@gmail.com> References: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> In-Reply-To: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2485; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=XZVd7p9mIBaNy+NIKUZiBgjkJyYONlNCoWZWgB7A9Zk=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBptSjwLT4MaR0DO6Twk7A21vxdQcVbeFomx/EA1 +jDGStKmI6JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCabUo8AAKCRCIgE5vWV1S MkcaD/9VLkaaITlVtQkALLgR9imaLtoSahhvcBaS5hnerW0ZoM415E+OF0n7qMHWx2vJ+6DwVJE cYh4zw/V8t/Vq2WtJgxNNKVobFBmGkI8yN8e10b7v01X/yo8P9aBwkeN2JzllVPjp9z1ottTC71 efLQxd/zVbzEUfscVZBiIDU5jBqnpOx7oIruF5rprombL0+AJky7HBfEBnfltDW24XM3kVRoil/ SUGQ6ab1qFYGEF4sBorFH2CjwqqoIns9L8u3a9MygbkRCuF01C+cTZxBy3MsVHj6E0vBpJlyDOr w7y65qTCcrHUsdNBsAYB0b+KiGgVM74VdisH/ustdjbQVtYhOFulGjyqCkkh0TptdUY4coavYG5 HGprEjwXC47VGsMN/8r8g2cxUWHOC8i9+fz5cToP2jXuQ+gZisDmiXYopoIUVATbAZ3pCB5u8dK kdFEm9aFQmfW4ny1uMHlGQRwtJwChfxSaxInWpH8WuALjtqL/3ZW0NrOAXKln2Mp+GP1SY7nS2V RecUtlCpvSUhntRYBf7E5qfb4ROvicm8zY2bnflp6vyfvH3gr73kAVM8LNskzxfWx9JuhliWEKY klQjmeO3XUz5A2XhPOGyrSlhbNRIqYKoSq06af6RQzq1e1XaZv6lmk6JxufSjHbAyEWxOC22GoD X4PymDvN649/AiQ== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 All devices on the same I2C bus share the same clock line and the bus frequency has therefor be chosen so that all attached devices are able to tolarate that clock rate. IOW, the bus speed must be set for the slowest attached device. With I2C multiplexers/switches on the other hand, it would be possible to have different "domains" that runs with different speeds. Prepare for such a feature by provide an optional callback function to change bus frequency. As a side effect, several bus drivers keep the bus speed in a private structure and can now have this value stored in a uniform way instead. Signed-off-by: Marcus Folkesson --- include/linux/i2c.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 20fd41b51d5c..712f9608108e 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -742,6 +742,8 @@ struct i2c_adapter { struct rt_mutex mux_lock; =20 int timeout; /* in jiffies */ + u32 clock_hz; /* bus clock speed */ + int (*set_clk_freq)(struct i2c_adapter *adap, u32 clock_hz); /* Optional = */ int retries; struct device dev; /* the adapter device */ unsigned long locked_flags; /* owned by the I2C core */ @@ -835,6 +837,39 @@ i2c_unlock_bus(struct i2c_adapter *adapter, unsigned i= nt flags) adapter->lock_ops->unlock_bus(adapter, flags); } =20 +static inline int +__i2c_adapter_set_clk_freq(struct i2c_adapter *adapter, u32 clock_hz) +{ + if (adapter->set_clk_freq) + return adapter->set_clk_freq(adapter, clock_hz); + + /* + * If the adapter is a root adapter without .set_clk_freq() implemented, = this feature is not + * supported. + */ + if (!i2c_parent_is_i2c_adapter(adapter)) + return -EOPNOTSUPP; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ec94sm18454261fa.22.2026.03.14.02.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Mar 2026 02:22:27 -0700 (PDT) From: Marcus Folkesson Date: Sat, 14 Mar 2026 10:22:41 +0100 Subject: [PATCH v8 2/5] i2c: mux: add support for per channel bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260314-i2c-mux-v8-2-fb1738a4df0a@gmail.com> References: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> In-Reply-To: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7627; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=zzwP/dH6nVUsUc4kUSRaQrWbWPe+IT1e5Ig8MAfNhhE=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBptSj1C8TDAhIQpBI60mQB5ccWeB7QNalrfr8hu zgjKTD2Gb6JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCabUo9QAKCRCIgE5vWV1S MpavEADKxjVy45nAOEczctYlkpyhTX3jHAGphbwfKmX1mosiif+XXwdgsxS3L1pbZ+NkdilxS05 9kMxy/9RudKnI8gerWBmYAuQJT8Q4sfCEenOZcemlH51eIq9QOFiux1OLYbzOkutLIxFuTVrWt2 bTU0oWzEsw6HZRPmYM4yBZACWs97rLOsj1M3JCfP4/w1ZKUfSYgTXoPyNpsiMI6EY3MQL3YapAG lQICjE/Lhq3rfDBKdbRo6UDukrMToHKwqLOUSX66GwHYYtxfJXlBx4FUnIYc7fS/s1Chk1XuyvR SjmJRaZZYOJej+Ml+of4e1XmGJOXva3744VvXGsA9fitwjhcuR6qTiPp3N0X5ea+EDiX52DDJFz 0IwslOoJ6E2em3Q52GManFlwIJYnXRpHQsE23bPlgVY/QonG7cBM2wm1RsiPJ4AdDAejkZTcY24 uv47WLc5pn1hyf67GSbUWBmn5taiFDJDL30MWs2jV013KlxydJzugHyf0FHHfRQruo8OqViA8wf rejh2KvOIcX4hIw4VNmlrlBjC2aadLutioqZp+zaa7fo6As90/OXCauZdOcvS6xXgwvwnlDUV2c epNXl2pk7KOcheruGcUINQzse0xOGoV+hvKhlfsyn30kFr5XdLdhrt3xRSlun4u7T70Q86X88sn 3W2M4EW8rs5B9GA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 There may be several reasons why you may need to use a certain speed on an I2C bus. E.g. - When several devices are attached to the bus, the speed must be selected according to the slowest device. - Electrical conditions may limit the usable speed on the bus for different reasons. With an I2C multiplexer, it is possible to group the attached devices after their preferred speed by e.g. putting all "slow" devices on a separate channel on the multiplexer. Consider the following topology: .----------. 100kHz .--------. .--------. 400kHz | |--------| dev D1 | | root |--+-----| I2C MUX | '--------' '--------' | | |--. 400kHz .--------. | '----------' '-------| dev D2 | | .--------. '--------' '--| dev D3 | '--------' One requirement with this design is that a multiplexer may only use the same or lower bus speed as its parent. Otherwise, if the multiplexer would have to increase the bus frequency, then all siblings (D3 in this case) would run into a clock speed it may not support. The bus frequency for each channel is set in the devicetree. As the i2c-mux bindings import the i2c-controller schema, the clock-frequency property is already allowed. If no clock-frequency property is set, the channel inherits their parent bus speed. The following example uses dt bindings to illustrate the topology above: i2c { clock-frequency =3D <400000>; i2c-mux { i2c@0 { clock-frequency =3D <100000>; D1 { ... }; }; i2c@1 { D2 { ... }; }; }; D3 { ... } }; Signed-off-by: Marcus Folkesson --- drivers/i2c/i2c-mux.c | 107 ++++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 95 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index d59644e50f14..6b5c9ae1efde 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -36,21 +36,75 @@ struct i2c_mux_priv { u32 chan_id; }; =20 +static int i2c_mux_select_chan(struct i2c_adapter *adap, u32 chan_id, u32 = *oldclock) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + int ret; + + if (priv->adap.clock_hz && priv->adap.clock_hz < parent->clock_hz) { + *oldclock =3D parent->clock_hz; + + if (muxc->mux_locked) + ret =3D i2c_adapter_set_clk_freq(parent, priv->adap.clock_hz); + else + ret =3D __i2c_adapter_set_clk_freq(parent, priv->adap.clock_hz); + + dev_dbg(&adap->dev, "Set clock frequency %uHz on %s\n", + priv->adap.clock_hz, parent->name); + + if (ret) + dev_err(&adap->dev, + "Failed to set clock frequency %uHz on adapter %s: %d\n", + *oldclock, parent->name, ret); + } + + return muxc->select(muxc, priv->chan_id); +} + +static void i2c_mux_deselect_chan(struct i2c_adapter *adap, u32 chan_id, u= 32 oldclock) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + int ret; + + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); + + if (oldclock && oldclock !=3D priv->adap.clock_hz) { + if (muxc->mux_locked) + ret =3D i2c_adapter_set_clk_freq(parent, oldclock); + else + ret =3D __i2c_adapter_set_clk_freq(parent, oldclock); + + dev_dbg(&adap->dev, "Restored clock frequency %uHz on %s\n", + oldclock, parent->name); + + if (ret) + dev_err(&adap->dev, + "Failed to set clock frequency %uHz on adapter %s: %d\n", + oldclock, parent->name, ret); + } +} + static int __i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D __i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -61,15 +115,16 @@ static int i2c_mux_master_xfer(struct i2c_adapter *ada= p, struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -82,16 +137,17 @@ static int __i2c_mux_smbus_xfer(struct i2c_adapter *ad= ap, struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D __i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -104,16 +160,17 @@ static int i2c_mux_smbus_xfer(struct i2c_adapter *ada= p, struct i2c_mux_priv *priv =3D adap->algo_data; struct i2c_mux_core *muxc =3D priv->muxc; struct i2c_adapter *parent =3D muxc->parent; + u32 oldclock =3D 0; int ret; =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id, &oldclock); if (ret >=3D 0) ret =3D i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id, oldclock); =20 return ret; } @@ -362,6 +419,32 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, } } =20 + of_property_read_u32(child, "clock-frequency", &priv->adap.clock_hz); + + /* If the mux adapter has no clock-frequency property, inherit from pare= nt */ + if (!priv->adap.clock_hz) + priv->adap.clock_hz =3D parent->clock_hz; + + /* + * Warn if the mux adapter is not parent-locked as + * this may cause issues for some hardware topologies. + */ + if ((priv->adap.clock_hz < parent->clock_hz) && muxc->mux_locked) + dev_warn(muxc->dev, + "channel %u is slower than parent on a non parent-locked mux\n", + chan_id); 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ec94sm18454261fa.22.2026.03.14.02.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Mar 2026 02:22:28 -0700 (PDT) From: Marcus Folkesson Date: Sat, 14 Mar 2026 10:22:42 +0100 Subject: [PATCH v8 3/5] i2c: davinci: calculate bus freq from Hz instead of kHz Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260314-i2c-mux-v8-3-fb1738a4df0a@gmail.com> References: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> In-Reply-To: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3233; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=vsSIa0c3XvGrZdSaP0ssvqDlYgrE1wL3DrKCmY5NXO8=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBptSj56Xwy+MgHCIG34d4tFjurt5gk+F9pQ2pq5 kqyoxNp6EyJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCabUo+QAKCRCIgE5vWV1S MlIZEACBCgO7bJ+4AS8gst3qBeg8NEVHmuvcetgmLS99GSwqTUu6+IVEU4oACsNsnQ2p0bIIW+A iNQ9BinXfoc3df0p3yh50lqq6hJUyLKwQCXxE9HDJ1wQxZtxXGIvKg/YcZ8Fz2B57uY/z4voHoe wt1HxuP7qLxrJp2+HaG7nTMJwrLC8nyaTmLYYt+oqykesf33FWZcHY2+tfcvah/L5LctfYoeoeC 1dOdlRvTyvPHlgWlBvvZt9OAGXfcRUw4vJTnR8Y7jK+2UeUq2Z/BYIm872D223apEPEv2c+Tg6E oQJ6srMBoGvGPgq6QKHkFlFP7XLa1cfbFFXI0Rk1GnIJDSYXUfy2dThHQzStZ41eUTXhJJVD3Do hPWsraBXohDkNeqeTFRup3Ef32gAuYztho6eUGY4PcgjOpHQd3FbboGbdRQMOlFPqIizCclzhvK bMikaZXvlGYxhiKNN5Fh5mQ3DjKXUoqTOJ20X3ijEcLXkGIluBsGY3tpaw6Zz+EZgfJzjj2HitY kZ9YbYaCi6Xt9cVQMZYD5lSKq0F0eLcEPEGe6fUohMUUF0m8LW0j4b0OjFUzWTnsX2XS5qPN2fR eFc6J+ar9pi3DLOX7IdyQwZwdmocTmdWFLa3AKf5Z18M9lAI4xjqBm6oria/hQWQSvqLEl1xtK1 ACUE4pJ/Vltr3QQ== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 The bus frequency is unnecessarily converted between Hz and kHz in several places. This is probably an old legacy from the old times (pre-devicetrees) when the davinci_i2c_platform_data took the bus_freq in kHz. Stick to Hz. Reviewed-by: Bartosz Golaszewski Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index a773ba082321..549fb22cdf4f 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -117,8 +117,6 @@ /* timeout for pm runtime autosuspend */ #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ =20 -#define DAVINCI_I2C_DEFAULT_BUS_FREQ 100 - struct davinci_i2c_dev { struct device *dev; void __iomem *base; @@ -134,8 +132,8 @@ struct davinci_i2c_dev { #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; #endif - /* standard bus frequency (kHz) */ - unsigned int bus_freq; + /* standard bus frequency */ + unsigned int bus_freq_hz; /* Chip has a ICPFUNC register */ bool has_pfunc; }; @@ -209,16 +207,16 @@ static void i2c_davinci_calc_clk_dividers(struct davi= nci_i2c_dev *dev) if (device_is_compatible(dev->dev, "ti,keystone-i2c")) d =3D 6; =20 - clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); + clk =3D (input_clock / (psc + 1)) / (dev->bus_freq_hz); /* Avoid driving the bus too fast because of rounding errors above */ - if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) + if (input_clock / (psc + 1) / clk > dev->bus_freq_hz) clk++; /* * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH * to LOW ratio as 1 to 2 is more safe. */ - if (dev->bus_freq > 100) + if (bus_freq_hz > I2C_MAX_STANDARD_MODE_FREQ) clkl =3D (clk << 1) / 3; else clkl =3D (clk >> 1); @@ -242,7 +240,7 @@ static void i2c_davinci_calc_clk_dividers(struct davinc= i_i2c_dev *dev) davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); =20 - dev_dbg(dev->dev, "input_clock =3D %d, CLK =3D %d\n", input_clock, clk); + dev_dbg(dev->dev, "input_clock =3D %u, CLK =3D %u\n", input_clock, clk); } =20 /* @@ -269,7 +267,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); dev_dbg(dev->dev, "CLKH =3D %d\n", davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); - dev_dbg(dev->dev, "bus_freq =3D %dkHz\n", dev->bus_freq); + dev_dbg(dev->dev, "bus_freq_hz =3D %dHz\n", dev->bus_freq_hz); =20 =20 /* Take the I2C module out of reset: */ @@ -760,9 +758,9 @@ static int davinci_i2c_probe(struct platform_device *pd= ev) =20 r =3D device_property_read_u32(&pdev->dev, "clock-frequency", &prop); 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ec94sm18454261fa.22.2026.03.14.02.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Mar 2026 02:22:32 -0700 (PDT) From: Marcus Folkesson Date: Sat, 14 Mar 2026 10:22:43 +0100 Subject: [PATCH v8 4/5] i2c: davinci: add support for setting bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260314-i2c-mux-v8-4-fb1738a4df0a@gmail.com> References: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> In-Reply-To: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3885; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=Lh7Dkm+/uvcdStnc/oNui4Wy85cMEfrtDS4KN8XCm1g=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBptSj+uCJIvW+lUyvN1DTR+9pw5rD1oPcFBJd9x 1nuXwaGxiCJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCabUo/gAKCRCIgE5vWV1S MhQZD/sHVDGLWGQz/rWMZl6TcG+2SxgXoflaNlMTf+9HfNzomB/WDqheVJpLoxDWh5iEwNXutiZ /DgfKzqGuSOn3iEvj7s8BUcZrvBvhpsq/sRDTT0IFZwBa2TmdVpPhYfKEzSyZ/IZGnp/IL5s1Cw iEMsMwEAb70BG4Gg1ilq3tht6S94zis2zZvJ05IW8VcKMwYr0hUSnj5DryTk2ezOEIu3VIyQmTU GSCoqlhQC2m8dyaPs/LulYuIWXnrW1UAw0hVphSjYnv5lJfQ0UAMkRPF0bRoR7MFK0yWsrF35TC bvODG0nal5qsZdVDsWEHl6H6JHvU+bKK8HR3+LCJD42H58CkR24NukoCSU3xFbdPO5N0Wxxx6zv PDcP00RPve20HdiXIpprLCkno7w+Hg5plcX6yHOwH0d+9FDCfj/qLGTmf4+Xq/rg33qV2RHX+5i E4TAYLNtopB3xGeSZpDF7an18Z2Bm/Whq6Ts2c5/0pIJD6NrnqkrHiz+I6263E3vBlXEGBcn9pg Cl7jY/3ErUwyvF9epMwo2rM1kvoi/0yUJRrYanC3tMu4QRVox5nB+VK6MLTN7EMjlJqov7HrRNM BpbzImykbv5BLCd8LH2ia6RCf5EwxSDpLxFUxPfpBcnMnMJi+7J8KwACRweT5+GF4fE366haoaV kOzKtpnTA+6lUXA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Populate adapter with clock_hz and .set_clk_freq() to enable support for dynamic bus frequency. Remove bus_freq_hz entirely and only use clock_hz instead. Acked-by: Bartosz Golaszewski Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 36 +++++++++++++++++++++++++++++------- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index 549fb22cdf4f..72bc3b286d20 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -132,8 +132,6 @@ struct davinci_i2c_dev { #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; #endif - /* standard bus frequency */ - unsigned int bus_freq_hz; /* Chip has a ICPFUNC register */ bool has_pfunc; }; @@ -171,6 +169,8 @@ static void i2c_davinci_calc_clk_dividers(struct davinc= i_i2c_dev *dev) u32 clkh; u32 clkl; u32 input_clock =3D clk_get_rate(dev->clk); + u32 bus_freq_hz =3D dev->adapter.clock_hz; + =20 /* NOTE: I2C Clock divider programming info * As per I2C specs the following formulas provide prescaler @@ -207,9 +207,9 @@ static void i2c_davinci_calc_clk_dividers(struct davinc= i_i2c_dev *dev) if (device_is_compatible(dev->dev, "ti,keystone-i2c")) d =3D 6; =20 - clk =3D (input_clock / (psc + 1)) / (dev->bus_freq_hz); + clk =3D (input_clock / (psc + 1)) / (bus_freq_hz); /* Avoid driving the bus too fast because of rounding errors above */ - if (input_clock / (psc + 1) / clk > dev->bus_freq_hz) + if (input_clock / (psc + 1) / clk > bus_freq_hz) clk++; /* * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at @@ -267,7 +267,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); dev_dbg(dev->dev, "CLKH =3D %d\n", davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); - dev_dbg(dev->dev, "bus_freq_hz =3D %dHz\n", dev->bus_freq_hz); + dev_dbg(dev->dev, "bus_freq_hz =3D %dHz\n", dev->adapter.clock_hz); =20 =20 /* Take the I2C module out of reset: */ @@ -279,6 +279,27 @@ static int i2c_davinci_init(struct davinci_i2c_dev *de= v) return 0; } =20 +static int davinci_i2c_set_clk(struct i2c_adapter *adap, u32 clock_hz) +{ + struct davinci_i2c_dev *dev =3D i2c_get_adapdata(adap); + + if (adap->clock_hz =3D=3D clock_hz) + return 0; + + adap->clock_hz =3D clock_hz; + + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); + + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); + + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); + + return 0; +} + /* * This routine does i2c bus recovery by using i2c_generic_scl_recovery * which is provided by I2C Bus recovery infrastructure. @@ -755,12 +776,13 @@ static int davinci_i2c_probe(struct platform_device *= pdev) dev->dev =3D &pdev->dev; dev->irq =3D irq; platform_set_drvdata(pdev, dev); + adap =3D &dev->adapter; =20 r =3D device_property_read_u32(&pdev->dev, "clock-frequency", &prop); if (r) prop =3D I2C_MAX_STANDARD_MODE_FREQ; =20 - dev->bus_freq_hz =3D prop; + adap->clock_hz =3D prop; =20 dev->has_pfunc =3D device_property_present(&pdev->dev, "ti,has-pfunc"); =20 @@ -800,7 +822,6 @@ static int davinci_i2c_probe(struct platform_device *pd= ev) goto err_unuse_clocks; } =20 - adap =3D &dev->adapter; i2c_set_adapdata(adap, dev); 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67e5ec94sm18454261fa.22.2026.03.14.02.22.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Mar 2026 02:22:33 -0700 (PDT) From: Marcus Folkesson Date: Sat, 14 Mar 2026 10:22:44 +0100 Subject: [PATCH v8 5/5] docs: i2c: i2c-topology: add section about bus speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260314-i2c-mux-v8-5-fb1738a4df0a@gmail.com> References: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> In-Reply-To: <20260314-i2c-mux-v8-0-fb1738a4df0a@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8169; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=GuWaYKwfMV3ENq2uAbPKaKDYJ6qhLIPVj7+qDo+zpgI=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBptSkCCHSLTykCPceE5Eh2DSOK2JRFSqcc28ugL D1Q4S3H19+JAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCabUpAgAKCRCIgE5vWV1S MvRLEADX64l8m4MrCjBOkqP74r/edbqERiO45KRk1Ys+KSZoaN2SvKxB46dBr/dSuUeKKkIeU2E UbZAKVHN/c4O9KQqee3KSOIN06U2LIbsuezGj4/mNhX/tLn7YfGen7Lb1ckfU8eAU98ftJfoAmE WqyI+JIQCPnjWzl4TC/9Y9lFn3w0/KoklRItTV31ZErmKZ3csGChr31ilNJM6x1g0ujwYVt+jkB XaFthkJXDsci7GhfNYHJOUtpAOBRmP1KbTZARcmab0KAb+INqFEDvjIbSY/l04jQ8U58jHfRBA4 vDe850K0z3e9/2hAe/bZpN02pLTFb1i9BOj+8KvPHm6YefCPttwILp5XU15FwykJfxsi9fk61v6 takavO43LHlMu/zm4QhGSdhZ3FAdrJSf/2EBF3V+iAXNib77Nfq6MIR5Qr2WLArVdYNS2fnyeB9 8HPLFDfb6gw6DMbnQbSY41boEjXUcGhMsbcOeTrv2hnUGGSZuKmuVQazZqJWN587FxB/irpe6vc yMaIXe8JaFq9Dcish2BkXMgyf1hkwS50yMAQDJPu92x4PkbncY/o5jA0K2TmaE/mFqd5ZDyfbBv 1FjOSXeFmWNQ1jxTcmKwJHpBBaWVJbN/kZeYyf0TbyoXZ9c9IuB+vNA8VsTYkeEiD8kKwEJ4hwR jjMF3TSIXEobSZA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Describe what needs to be consideraed and taken into account when using different bus speeds for different mux channels. Signed-off-by: Marcus Folkesson --- Documentation/i2c/i2c-topology.rst | 178 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 178 insertions(+) diff --git a/Documentation/i2c/i2c-topology.rst b/Documentation/i2c/i2c-top= ology.rst index 48fce0f7491b..24df553ca8c7 100644 --- a/Documentation/i2c/i2c-topology.rst +++ b/Documentation/i2c/i2c-topology.rst @@ -367,6 +367,184 @@ When D1 or D2 are accessed, accesses to D3 and D4 are= locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out. =20 +Bus Speed and I2C Multiplexers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +I2C bus multiplexers allow multiple downstream channels to be exposed +as separate I2C adapters which also could set their own bus speed. + +The multiplexer itself cannot change the bus speed as it use the upstream +clock and data lines to communicate with the downstream devices. The speed +is therefore changed in the root adapter resulting in that the whole bus is +affected. + +This increases the complexity of the topology and some considerations must +be taken into account. + +Bus speed +---------- + +Downstream channels of an I2C multiplexer can only operate at the same or +lower bus speed as the upstream bus. This is because the upstream bus may +have devices that cannot operate at higher speeds and those will be affect= ed +by the speed change. + +The example below illustrates the problem. +The root adapter is operating at 100kHz. D2 can only operate with 100kHz, +but D1 can operate at 400kHz. When D1 is selected, the bus speed of the +root adapter would have to be set to 400kHz, a speed that D2 may not suppo= rt. + +This topology is therefor not allowed: :: + + .----------. 400kHz .--------. + .--------. 100kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 | + | '----------' + | .--------. + '--| dev D2 | + '--------' + + +This topology is allowed: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Preferred topology +------------------- + +The preferred topology when using different bus speeds is to have the mult= iplexer +connected directly to the root adapter without any devices as siblings. +By this arrangement, the bus speed can be changed without affecting any ot= her devices +and many of the caveats are avoided. + +Other multiplexers in parallel is still okay as those are locked out durin= g transfers. + +This is the preferred topology: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Locking +-------- + +If the multiplexer is mux-locked, transfers to D3 may interleave between t= he +select-transfer-deselect to D1 or D2. +This results in a situation where the bus speed to D3 may be lower than it +is supposed to be. This is usually not a problem. + +This topology is allowed but some transfers to D3 may be at 100kHz: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +Multiple muxes in series +-------------------------- + +When multiple muxes are used in series the same rules applies. + +Transfers to D3 may interleave between select-transfer-deselect to D1, whi= ch +results that the bus speed to D2 or D3 will be at 100KHz. + +Transfers to D2 may interleave between select-transfer-deselect to D1, whi= ch +results in that the bus speed to D1 may be at 400kHz as the transfer to D2 +will set the bus speed to before the transfer to D1 starts. + +This is probably a bad topology :: + + .----------. 400kHz .----------. 100kHz .--------. + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | + | root |--+----| locked | 400kHz | locked | '--------' + '--------' | | mux M1 |--. | mux M2 | + | '----------' | '----------' + | .--------. | .--------. + '--| dev D3 | '--| dev D2 | + '--------' '--------' + +Multiple muxes in parallel +---------------------------- + +When multiple muxes are used in parallel all access to other muxes are loc= ked out +so this is not a problem. + +If the muxes are mux-locked, access to D3 may still interleave though. + +In the example below, D3 may not interleave between select-transfer-desele= ct for D1 +or D2 as both muxes are parent-locked: :: + + + .----------. 100kHz .--------. + | parent- |----------| dev D1 | + .--| locked | '--------' + | | mux M1 | + | '----------' + | .----------. 400KHz .--------. + .--------. 400kHz | parent- |---------| dev D2 | + | root |--+------| locked | '--------' + '--------' | | mux M2 | + | '----------' + | .--------. + '--| dev D3 | + '--------' + +Idle state +----------- + +Muxes have an idle state, which is the state the channels are put into whe= n no channel +is active. The state is typically one of the following: + +- All channels are disconnected +- The last selected channel is left as-is +- A predefined channel is selected + +Muxes that support an idle state where all channels are disconnected are p= referred when using +different bus speeds. Otherwise high bus speeds may "leak" through to devi= ces that +may not support that higher speed. + +Consider the following example: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +If the idle state of M1 is: + +- All channels disconnected: No problem, D1 and D2 are not affected by com= munication + to D3. +- Last selected channel: Problem if D1 was the last selected channel. High= speed + communication to D3 will be "leaked" to D1. +- Predefined channel: Problem if the predefined channel D1. Set predefined= channel + to D2 as D2 may handle 400kHz. + +Supported controllers +----------------------- + +Not all I2C controllers support setting the bus speed dynamically. +At the time of writing, the following controllers have support: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +i2c-davinci Supports dynamic bus speed +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Mux type of existing device drivers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.53.0