From nobody Tue Apr 7 09:18:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 950233DF00A; Fri, 13 Mar 2026 18:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773428019; cv=none; b=QWt5zjlZTjS0h/IPo5nYwpVdj8WH7rLam77j+2lYAOuGZkRciQiWatlROuT/AayF7u7PVgyvAyBZC7/OYzPHc4WHG/3P4tlcXX9rBqqArKKsLF1j+s3QoGCZ6+T2aCvAd6ZlcrfT4MdEE58SOxW/OB1mk1hWoH1E1/ER21o2Z/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773428019; c=relaxed/simple; bh=uLFhRLmnl+H6fX4Tj4A7q2oeiwiC8C76u4nHQ95EG2o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=abcbK4iDiKkMXDopY8Tlqq3U8rZyTD+DY5/N0C38ywVLfAPjAK6X6epAotM3gUAHJ0cWvvh9CLdOhVKACJwBTGttTY4JtfiDT7geXrylfg0iCcGuVdXCjlIkFom8nVN8dE4xDbqCqdTQwk+j4nbdPNn7xc9Bc1gSIb9ii+MjnWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=juRJ4qVk; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="juRJ4qVk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773428018; x=1804964018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uLFhRLmnl+H6fX4Tj4A7q2oeiwiC8C76u4nHQ95EG2o=; b=juRJ4qVkKZZIN+leZ9Uzq7MV8oCh9uaNpCgivAA69fDMlfkaSQhIeNg9 ScM61Hi2sDDeY6qiZUJwlRkNkHhrEFsBPQ4KDJusx+NsiSLhmKW5/YCaR hwqodFSJUBUp/kFaTb9Gwlej/EnddLgxci03nXhWmagQMb7YlgfXa5Ip8 5q/elEowEv1hLc5bsH7FDaAov2T15nqaQLh0rMAYx463Cf+Dpd7shc3WS dFDRRdZ3WWNUL1aiEFqtQyVxPkw1vh8cE22GbbJxMU9L4lyH8iKfQOP/I 7BpbV7x5L9vlC9cf+G7XikFdYdroUAYw3i6Gp1ByYWwOfxS12WCpMN48p Q==; X-CSE-ConnectionGUID: TK24tqfrRA+EEt18pcPbzA== X-CSE-MsgGUID: Ding33vBQaKmavOl3V0OBg== X-IronPort-AV: E=McAfee;i="6800,10657,11728"; a="74242244" X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="74242244" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 X-CSE-ConnectionGUID: 76gfYKJgQNaNjsNSA5FIuQ== X-CSE-MsgGUID: 5aA0rjRqSqGKZrJnZF+wMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225709172" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/6] powercap: intel_rapl: Remove unused AVERAGE_POWER primitive Date: Fri, 13 Mar 2026 11:53:27 -0700 Message-ID: <20260313185333.2370733-2-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The AVERAGE_POWER primitive and RAPL_PRIMITIVE_DERIVED flag are not used anywhere in the code. Remove them to simplify the primitive handling logic. No functional changes. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 13 ------------- include/linux/intel_rapl.h | 1 - 2 files changed, 14 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 2b5c587b222b..8c838e2e457d 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -89,7 +89,6 @@ #define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) =20 /* Non HW constants */ -#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ #define RAPL_PRIMITIVE_DUMMY BIT(2) =20 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit= */ @@ -700,9 +699,6 @@ static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMI= TIVES] =3D { 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), [PSYS_TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_= WINDOW2_MASK, 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - /* non-hardware */ - [AVERAGE_POWER] =3D PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UN= IT, - RAPL_PRIMITIVE_DERIVED), }; =20 /* RAPL primitives for TPMI I/F */ @@ -742,9 +738,6 @@ static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIM= ITIVES] =3D { 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THRO= TTLE_TIME_MASK, 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), - /* non-hardware */ - [AVERAGE_POWER] =3D PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UN= IT, - RAPL_PRIMITIVE_DERIVED), }; =20 static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int pr= im) @@ -837,12 +830,6 @@ static int rapl_read_data_raw(struct rapl_domain *rd, if (!ra.reg.val) return -EINVAL; =20 - /* non-hardware data are collected by the polling thread */ - if (rpi->flag & RAPL_PRIMITIVE_DERIVED) { - *data =3D rd->rdd.primitives[prim]; - return 0; - } - ra.mask =3D rpi->mask; =20 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, pmu_ctx)) { diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h index 6d694099a3ad..9e6bd654be1f 100644 --- a/include/linux/intel_rapl.h +++ b/include/linux/intel_rapl.h @@ -77,7 +77,6 @@ enum rapl_primitives { PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW2, /* below are not raw primitive data */ - AVERAGE_POWER, NR_RAPL_PRIMITIVES, }; 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X-CSE-ConnectionGUID: AFKhohu3S4qOyzVAOZMjSA== X-CSE-MsgGUID: YLg6FMNpTVaHznHnwLB2Og== X-IronPort-AV: E=McAfee;i="6800,10657,11728"; a="74242248" X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="74242248" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 X-CSE-ConnectionGUID: eVevYUkjSQuRstlbep1ORg== X-CSE-MsgGUID: ujMBoOdFS4GF3dYQ9pZQUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225709175" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/6] powercap: intel_rapl: Remove unused macro definitions Date: Fri, 13 Mar 2026 11:53:28 -0700 Message-ID: <20260313185333.2370733-3-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the following unused macro definitions from the RAPL common driver: * DOMAIN_STATE_INACTIVE and DOMAIN_STATE_POWER_LIMIT_SET * IOSF_CPU_POWER_BUDGET_CTL_BYT and IOSF_CPU_POWER_BUDGET_CTL_TNG * MAX_PRIM_NAME No functional changes. Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 8c838e2e457d..fdcac4a173a8 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -96,15 +96,7 @@ /* per domain data, some are optional */ #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) =20 -#define DOMAIN_STATE_INACTIVE BIT(0) -#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) - -/* Sideband MBI registers */ -#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02 -#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF - #define PACKAGE_PLN_INT_SAVED BIT(0) -#define MAX_PRIM_NAME 32 =20 #define RAPL_EVENT_MASK GENMASK(7, 0) =20 --=20 2.43.0 From nobody Tue Apr 7 09:18:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD1603DE42A; Fri, 13 Mar 2026 18:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773428018; cv=none; b=h8EX70sC42OS0XjHtdUZHWpv0+euBgEVV1/uf0dYo6W/PZaw3fZQcWiObeTIvXE6xIPaZfY4RxYZJpL7xhQONr8kH31AlGZ07lLzerdgwwnZ7/6tjlVuw0yYoGygcUvqPbdZv8New/IhHNyEe41nmo/eyrf7i6RNDGxbvhtBIq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773428018; c=relaxed/simple; bh=tevxBjD08c+EmvS2R+hvXC1HUxRaLfEL9OOQYa4Rh6k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OrvikElsqKfWGGqObAfnMN08kbRve1jX1yFl1wSiXX937ugxhmOAHrap5SF+OVaht3KiSsh0iu38eEy4nZ2Ujymbl0F0eUi3ziagshxZ/YrN7OHUlH9hPebnHKQxy2EB1IpGZ4ZcOhwQVLqQxSXLFouYVLb1EK6JihLNSvooHVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ciPT+85z; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ciPT+85z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773428017; x=1804964017; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tevxBjD08c+EmvS2R+hvXC1HUxRaLfEL9OOQYa4Rh6k=; b=ciPT+85zJB7SBclfoLHHfnfpKHZVty5+AdznumlQAeSo3hLcSa4vFaHU YxmDYuK3h8tQKrmm7bgRnHuO7qj8SAfVsNtfAd5AFeGXnv3BmjK3Ztk2G JAu/k6CExBDvbB1NEyVsu9A6YJJpqVRYEB1UaYSqS1V74S66qSsKggQH+ owWGBqii5t1q6n6OYFSQ5VXXFcYOQ00w9v8TNaeVFRbTgreE2pmYjHts0 NwAb6u5I8qRMLFGx1NQs9tCzFZBkTynHZo4m6qBi/An+vDtuPDHMqa4av xWSZW3PoZsJPmlKpToOafTBaCA0r8ePlWYLg1lmwOhOZJDvuei6G3JahV Q==; X-CSE-ConnectionGUID: 4YKyE3j1QEeSLIsTUerQCA== X-CSE-MsgGUID: hQj0Q2m/QwyNYzU8wrANgg== X-IronPort-AV: E=McAfee;i="6800,10657,11728"; a="74242252" X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="74242252" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 X-CSE-ConnectionGUID: ZE/2CXdiT6iAmLerKI2W+Q== X-CSE-MsgGUID: a9zULPIUTSWJ4V4D3u4drg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225709178" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/6] powercap: intel_rapl: Move primitive info to header for interface drivers Date: Fri, 13 Mar 2026 11:53:29 -0700 Message-ID: <20260313185333.2370733-4-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RAPL primitive information varies across different RAPL interfaces (MSR, TPMI, MMIO). Keeping them in the common code adds no benefit, but requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the primitive info infrastructure to the shared header to allow interface drivers to configure RAPL primitives. Specific changes: 1. Move struct rapl_primitive_info, enum unit_type, and PRIMITIVE_INFO_INIT macro to intel_rapl.h. 2. Change the @rpi field in struct rapl_if_priv from void * to struct rapl_primitive_info * to improve type safety and eliminate unnecessary casts. No functional changes. This is a preparatory refactoring to allow interface drivers to supply their own RAPL primitive settings. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 32 ++-------------------------- include/linux/intel_rapl.h | 32 ++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index fdcac4a173a8..d6c2819b1212 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -100,13 +100,6 @@ =20 #define RAPL_EVENT_MASK GENMASK(7, 0) =20 -enum unit_type { - ARBITRARY_UNIT, /* no translation */ - POWER_UNIT, - ENERGY_UNIT, - TIME_UNIT, -}; - static const char *pl_names[NR_POWER_LIMITS] =3D { [POWER_LIMIT1] =3D "long_term", [POWER_LIMIT2] =3D "short_term", @@ -208,27 +201,6 @@ static const struct rapl_defaults *get_defaults(struct= rapl_package *rp) return rp->priv->defaults; } =20 -/* per domain data. used to describe individual knobs such that access fun= ction - * can be consolidated into one instead of many inline functions. - */ -struct rapl_primitive_info { - const char *name; - u64 mask; - int shift; - enum rapl_domain_reg_id id; - enum unit_type unit; - u32 flag; -}; - -#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ - .name =3D #p, \ - .mask =3D m, \ - .shift =3D s, \ - .id =3D i, \ - .unit =3D u, \ - .flag =3D f \ - } - static void rapl_init_domains(struct rapl_package *rp); static int rapl_read_data_raw(struct rapl_domain *rd, enum rapl_primitives prim, @@ -748,10 +720,10 @@ static int rapl_config(struct rapl_package *rp) /* MMIO I/F shares the same register layout as MSR registers */ case RAPL_IF_MMIO: case RAPL_IF_MSR: - rp->priv->rpi =3D (void *)rpi_msr; + rp->priv->rpi =3D rpi_msr; break; case RAPL_IF_TPMI: - rp->priv->rpi =3D (void *)rpi_tpmi; + rp->priv->rpi =3D rpi_tpmi; break; default: return -EINVAL; diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h index 9e6bd654be1f..01f290de3586 100644 --- a/include/linux/intel_rapl.h +++ b/include/linux/intel_rapl.h @@ -137,6 +137,34 @@ struct rapl_defaults { bool spr_psys_bits; }; =20 +#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ + .name =3D #p, \ + .mask =3D m, \ + .shift =3D s, \ + .id =3D i, \ + .unit =3D u, \ + .flag =3D f \ + } + +enum unit_type { + ARBITRARY_UNIT, /* no translation */ + POWER_UNIT, + ENERGY_UNIT, + TIME_UNIT, +}; + +/* per domain data. used to describe individual knobs such that access fun= ction + * can be consolidated into one instead of many inline functions. + */ +struct rapl_primitive_info { + const char *name; + u64 mask; + int shift; + enum rapl_domain_reg_id id; + enum unit_type unit; + u32 flag; +}; + /** * struct rapl_if_priv: private data for different RAPL interfaces * @control_type: Each RAPL interface must have its own powercap @@ -152,7 +180,7 @@ struct rapl_defaults { * @write_raw: Callback for writing RAPL interface specific * registers. * @defaults: pointer to default settings - * @rpi: internal pointer to interface primitive info + * @rpi: pointer to interface primitive info */ struct rapl_if_priv { enum rapl_if_type type; @@ -164,7 +192,7 @@ struct rapl_if_priv { int (*read_raw)(int id, struct reg_action *ra, bool pmu_ctx); int (*write_raw)(int id, struct reg_action *ra); const struct rapl_defaults *defaults; - void *rpi; + struct rapl_primitive_info *rpi; }; =20 #ifdef CONFIG_PERF_EVENTS --=20 2.43.0 From nobody Tue Apr 7 09:18:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12EBE3DFC7C; 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X-CSE-ConnectionGUID: PTLqL6r/Qli/RE+N6QBO2Q== X-CSE-MsgGUID: tHg9DUOKSfSdyXnHppF08Q== X-IronPort-AV: E=McAfee;i="6800,10657,11728"; a="74242257" X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="74242257" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 X-CSE-ConnectionGUID: 0m3Ul3WmTU+DSEdKTGFk3g== X-CSE-MsgGUID: eISZ+RViSZ2BgWJOFCEivg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225709182" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/6] powercap: intel_rapl: Move TPMI primitives to TPMI driver Date: Fri, 13 Mar 2026 11:53:30 -0700 Message-ID: <20260313185333.2370733-5-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TPMI-specific RAPL primitives differ from those used by MSR and MMIO interfaces. Keeping them in the common RAPL driver requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the TPMI primitive definitions and associated bitmasks into the TPMI interface driver. This change includes: 1. Move TPMI-specific bitmask definitions from intel_rapl_common.c to intel_rapl_tpmi.c. 2. Add TPMI-local struct rapl_primitive_info instance and assign it to priv->rpi during TPMI probe. 3. Remove the RAPL TPMI related definitions from the common driver. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 51 -------------------------- drivers/powercap/intel_rapl_tpmi.c | 53 ++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 51 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index d6c2819b1212..545b811fa930 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -79,15 +79,6 @@ #define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) #define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) =20 -/* bitmasks for RAPL TPMI, used by primitive access functions */ -#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0) -#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) -#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18) -#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0) -#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18) -#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36) -#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) - /* Non HW constants */ #define RAPL_PRIMITIVE_DUMMY BIT(2) =20 @@ -665,45 +656,6 @@ static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIM= ITIVES] =3D { 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), }; =20 -/* RAPL primitives for TPMI I/F */ -static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] =3D { - /* name, mask, shift, msr index, unit divisor */ - [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MA= SK, 0, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MA= SK, 0, - RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), - [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MA= SK, 0, - RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), - [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MA= SK, 0, - RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), - [PL1_LOCK] =3D PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_LOCK] =3D PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), - [PL4_LOCK] =3D PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), - [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, - RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), - [PL4_ENABLE] =3D PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, - RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), - [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MA= SK, 18, - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MA= SK, 18, - RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), - [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INF= O_SPEC_MASK, 0, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_= TIME_WIN_MASK, - 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), - [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THRO= TTLE_TIME_MASK, - 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), -}; - static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int pr= im) { struct rapl_primitive_info *rpi =3D rp->priv->rpi; @@ -722,9 +674,6 @@ static int rapl_config(struct rapl_package *rp) case RAPL_IF_MSR: rp->priv->rpi =3D rpi_msr; break; - case RAPL_IF_TPMI: - rp->priv->rpi =3D rpi_tpmi; - break; default: return -EINVAL; } diff --git a/drivers/powercap/intel_rapl_tpmi.c b/drivers/powercap/intel_ra= pl_tpmi.c index c06d687366fc..7f41491d9cd1 100644 --- a/drivers/powercap/intel_rapl_tpmi.c +++ b/drivers/powercap/intel_rapl_tpmi.c @@ -62,6 +62,58 @@ static DEFINE_MUTEX(tpmi_rapl_lock); =20 static struct powercap_control_type *tpmi_control_type; =20 +/* bitmasks for RAPL TPMI, used by primitive access functions */ +#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0) +#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) +#define TPMI_POWER_HIGH_LOCK BIT_ULL(63) +#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18) +#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0) +#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18) +#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36) +#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54) +#define TPMI_ENERGY_STATUS_MASK GENMASK(31, 0) +#define TPMI_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) + +/* RAPL primitives for TPMI I/F */ +static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] =3D { + /* name, mask, shift, msr index, unit divisor */ + [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MA= SK, 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MA= SK, 0, + RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), + [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MA= SK, 0, + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), + [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, TPMI_ENERGY_STAT= US_MASK, 0, + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), + [PL1_LOCK] =3D PRIMITIVE_INFO_INIT(PL1_LOCK, TPMI_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_LOCK] =3D PRIMITIVE_INFO_INIT(PL2_LOCK, TPMI_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), + [PL4_LOCK] =3D PRIMITIVE_INFO_INIT(PL4_LOCK, TPMI_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), + [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, + RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), + [PL4_ENABLE] =3D PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE= , 62, + RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), + [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MA= SK, 18, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MA= SK, 18, + RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), + [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INF= O_SPEC_MASK, 0, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_= TIME_WIN_MASK, + 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), + [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, + TPMI_PERF_STATUS_THROTTLE_TIME_MASK, + 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), +}; + static int tpmi_rapl_read_raw(int id, struct reg_action *ra, bool atomic) { if (!ra->reg.mmio) @@ -344,6 +396,7 @@ static int intel_rapl_tpmi_probe(struct auxiliary_devic= e *auxdev, trp->priv.write_raw =3D tpmi_rapl_write_raw; trp->priv.control_type =3D tpmi_control_type; trp->priv.defaults =3D &defaults_tpmi; + trp->priv.rpi =3D rpi_tpmi; =20 /* RAPL TPMI I/F is per physical package */ trp->rp =3D rapl_find_package_domain(info->package_id, &trp->priv, false); --=20 2.43.0 From nobody Tue Apr 7 09:18:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F0F3C3BED; Fri, 13 Mar 2026 18:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773428020; cv=none; b=EdOISzE8GuaMtxLljZlix+jxtWadSS655YYg81Xy1UfvKPOpjT3pGqrOIuMkj5/Jz3+ybG9AfLYm4zPXMDRT0850J5xDOe8P0KdqXr4B6YR83OmABoezrVe1mLGstubn/OgTIfe3JelzsMtHD1IeijH2c0PZXcZcDXcb7TZI74w= ARC-Message-Signature: i=1; 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d="scan'208";a="225709184" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/6] thermal: intel: int340x: processor: Move MMIO primitives to MMIO driver Date: Fri, 13 Mar 2026 11:53:31 -0700 Message-ID: <20260313185333.2370733-6-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MMIO-specific primitives differ from those used by the TPMI interface. The MSR and MMIO interfaces shared the same primitives in the common driver, but MMIO does not require many MSR-specific entries (like PSYS). Keeping these in the common driver does not add any value and requires interface-specific handling logic that makes the common layer unnecessarily complex. Move the MMIO primitive definitions and associated bitmasks into the MMIO interface driver. This change includes: 1. Add MMIO-local struct rapl_primitive_info instance without MSR-specific entries and assign it to priv->rpi during MMIO initialization. 2. Remove the RAPL MMIO case from rapl_config() in the common driver. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 1 - .../int340x_thermal/processor_thermal_rapl.c | 72 +++++++++++++++++++ 2 files changed, 72 insertions(+), 1 deletion(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 545b811fa930..ffa3f95d8aa2 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -670,7 +670,6 @@ static int rapl_config(struct rapl_package *rp) { switch (rp->priv->type) { /* MMIO I/F shares the same register layout as MSR registers */ - case RAPL_IF_MMIO: case RAPL_IF_MSR: rp->priv->rpi =3D rpi_msr; break; diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c= b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c index 5dbeb0a43c8c..f8b9745c1b8a 100644 --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c @@ -11,6 +11,77 @@ =20 static struct rapl_if_priv rapl_mmio_priv; =20 +/* bitmasks for RAPL MSRs, used by primitive access functions */ +#define MMIO_ENERGY_STATUS_MASK GENMASK(31, 0) + +#define MMIO_POWER_LIMIT1_MASK GENMASK(14, 0) +#define MMIO_POWER_LIMIT1_ENABLE BIT(15) +#define MMIO_POWER_LIMIT1_CLAMP BIT(16) + +#define MMIO_POWER_LIMIT2_MASK GENMASK_ULL(46, 32) +#define MMIO_POWER_LIMIT2_ENABLE BIT_ULL(47) +#define MMIO_POWER_LIMIT2_CLAMP BIT_ULL(48) + +#define MMIO_POWER_LOW_LOCK BIT(31) +#define MMIO_POWER_HIGH_LOCK BIT_ULL(63) + +#define MMIO_POWER_LIMIT4_MASK GENMASK(12, 0) + +#define MMIO_TIME_WINDOW1_MASK GENMASK_ULL(23, 17) +#define MMIO_TIME_WINDOW2_MASK GENMASK_ULL(55, 49) + +#define MMIO_POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) +#define MMIO_POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) +#define MMIO_POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) +#define MMIO_POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) + +#define MMIO_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) +#define MMIO_PP_POLICY_MASK GENMASK(4, 0) + +/* RAPL primitives for MMIO I/F */ +static struct rapl_primitive_info rpi_mmio[NR_RAPL_PRIMITIVES] =3D { + /* name, mask, shift, msr index, unit divisor */ + [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, MMIO_POWER_LIMIT1_M= ASK, 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, MMIO_POWER_LIMIT2_M= ASK, 32, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, MMIO_POWER_LIMIT4_M= ASK, 0, + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), + [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, MMIO_ENERGY_STAT= US_MASK, 0, + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), + [FW_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_LOW_LOCK, 31, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [FW_HIGH_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, MMIO_POWER_LIMIT1_ENABL= E, 15, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_CLAMP] =3D PRIMITIVE_INFO_INIT(PL1_CLAMP, MMIO_POWER_LIMIT1_CLAMP, = 16, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, MMIO_POWER_LIMIT2_ENABL= E, 47, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_CLAMP] =3D PRIMITIVE_INFO_INIT(PL2_CLAMP, MMIO_POWER_LIMIT2_CLAMP, = 48, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, MMIO_TIME_WINDOW1_M= ASK, 17, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, MMIO_TIME_WINDOW2_M= ASK, 49, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, + MMIO_POWER_INFO_THERMAL_SPEC_MASK, 0, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, MMIO_POWER_INFO_MAX_MASK,= 32, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, MMIO_POWER_INFO_MIN_MASK,= 16, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, + MMIO_POWER_INFO_MAX_TIME_WIN_MASK, 48, + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), + [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, + MMIO_PERF_STATUS_THROTTLE_TIME_MASK, 0, + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), + [PRIORITY_LEVEL] =3D PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, MMIO_PP_POLICY_M= ASK, 0, + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), +}; + static const struct rapl_mmio_regs rapl_mmio_default =3D { .reg_unit =3D 0x5938, .regs[RAPL_DOMAIN_PACKAGE] =3D { 0x59a0, 0x593c, 0x58f0, 0, 0x5930, 0x59b= 0}, @@ -75,6 +146,7 @@ int proc_thermal_rapl_add(struct pci_dev *pdev, struct p= roc_thermal_device *proc rapl_mmio_priv.read_raw =3D rapl_mmio_read_raw; rapl_mmio_priv.write_raw =3D rapl_mmio_write_raw; rapl_mmio_priv.defaults =3D &rapl_defaults_mmio; + rapl_mmio_priv.rpi =3D rpi_mmio; =20 rapl_mmio_priv.control_type =3D powercap_register_control_type(NULL, "int= el-rapl-mmio", NULL); if (IS_ERR(rapl_mmio_priv.control_type)) { --=20 2.43.0 From nobody Tue Apr 7 09:18:44 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EECA13DEAE3; Fri, 13 Mar 2026 18:53:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; 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d="scan'208";a="74242265" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 X-CSE-ConnectionGUID: iUUHc19cTOOYofkYoGWxow== X-CSE-MsgGUID: Gen5jhubTD2R+ryRzEwvXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,118,1770624000"; d="scan'208";a="225709188" Received: from skuppusw-desk2.jf.intel.com ([10.165.154.101]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Mar 2026 11:53:34 -0700 From: Kuppuswamy Sathyanarayanan To: "Rafael J . Wysocki" , Daniel Lezcano Cc: Zhang Rui , Lukasz Luba , Srinivas Pandruvada , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 6/6] powercap: intel_rapl: Move MSR primitives to MSR driver Date: Fri, 13 Mar 2026 11:53:32 -0700 Message-ID: <20260313185333.2370733-7-sathyanarayanan.kuppuswamy@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> References: <20260313185333.2370733-1-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MSR-specific RAPL primitives differ from those used by TPMI and MMIO interfaces. Keeping them in the common driver requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the MSR primitive definitions and associated bitmasks into the MSR interface driver. This change includes: 1. Move MSR-specific bitmask definitions to RAPL MSR driver. 2. Add MSR-local struct rapl_primitive_info instance and assign it to priv->rpi during MSR probe. 3. Remove the primitive assignment logic from rapl_config() in the common driver. No functional changes are intended. Co-developed-by: Zhang Rui Signed-off-by: Zhang Rui Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Srinivas Pandruvada --- drivers/powercap/intel_rapl_common.c | 105 --------------------------- drivers/powercap/intel_rapl_msr.c | 99 +++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 105 deletions(-) diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index ffa3f95d8aa2..b2301b30e1ff 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -30,24 +30,8 @@ #include #include =20 -/* bitmasks for RAPL MSRs, used by primitive access functions */ #define ENERGY_STATUS_MASK GENMASK(31, 0) =20 -#define POWER_LIMIT1_MASK GENMASK(14, 0) -#define POWER_LIMIT1_ENABLE BIT(15) -#define POWER_LIMIT1_CLAMP BIT(16) - -#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32) -#define POWER_LIMIT2_ENABLE BIT_ULL(47) -#define POWER_LIMIT2_CLAMP BIT_ULL(48) -#define POWER_HIGH_LOCK BIT_ULL(63) -#define POWER_LOW_LOCK BIT(31) - -#define POWER_LIMIT4_MASK GENMASK(12, 0) - -#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17) -#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49) - #define POWER_UNIT_OFFSET 0x00 #define POWER_UNIT_MASK GENMASK(3, 0) =20 @@ -57,28 +41,6 @@ #define TIME_UNIT_OFFSET 0x10 #define TIME_UNIT_MASK GENMASK(19, 16) =20 -#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) -#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) -#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) -#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) - -#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) -#define PP_POLICY_MASK GENMASK(4, 0) - -/* - * SPR has different layout for Psys Domain PowerLimit registers. - * There are 17 bits of PL1 and PL2 instead of 15 bits. - * The Enable bits and TimeWindow bits are also shifted as a result. - */ -#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0) -#define PSYS_POWER_LIMIT1_ENABLE BIT(17) - -#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32) -#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) - -#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) -#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) - /* Non HW constants */ #define RAPL_PRIMITIVE_DUMMY BIT(2) =20 @@ -598,64 +560,6 @@ static u64 rapl_unit_xlate(struct rapl_domain *rd, enu= m unit_type type, return div64_u64(value, scale); } =20 -/* RAPL primitives for MSR and MMIO I/F */ -static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] =3D { - /* name, mask, shift, msr index, unit divisor */ - [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, = 0, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, = 32, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, = 0, - RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), - [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MA= SK, 0, - RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), - [FW_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [FW_HIGH_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL1_CLAMP] =3D PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [PL2_CLAMP] =3D PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, - RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), - [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, = 17, - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, = 49, - RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, - POWER_INFO_THERMAL_SPEC_MASK, 0, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, - RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), - [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, - POWER_INFO_MAX_TIME_WIN_MASK, 48, - RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), - [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, - PERF_STATUS_THROTTLE_TIME_MASK, 0, - RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), - [PRIORITY_LEVEL] =3D PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, = 0, - RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), - [PSYS_POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER= _LIMIT1_MASK, 0, - RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [PSYS_POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER= _LIMIT2_MASK, - 32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), - [PSYS_PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIM= IT1_ENABLE, - 17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, - 0), - [PSYS_PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIM= IT2_ENABLE, - 49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, - 0), - [PSYS_TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_= WINDOW1_MASK, - 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), - [PSYS_TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_= WINDOW2_MASK, - 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), -}; - static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int pr= im) { struct rapl_primitive_info *rpi =3D rp->priv->rpi; @@ -668,15 +572,6 @@ static struct rapl_primitive_info *get_rpi(struct rapl= _package *rp, int prim) =20 static int rapl_config(struct rapl_package *rp) { - switch (rp->priv->type) { - /* MMIO I/F shares the same register layout as MSR registers */ - case RAPL_IF_MSR: - rp->priv->rpi =3D rpi_msr; - break; - default: - return -EINVAL; - } - /* defaults_msr can be NULL on unsupported platforms */ if (!rp->priv->defaults || !rp->priv->rpi) return -ENODEV; diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rap= l_msr.c index b7c10ed75d69..cfb35973f0b5 100644 --- a/drivers/powercap/intel_rapl_msr.c +++ b/drivers/powercap/intel_rapl_msr.c @@ -44,6 +44,46 @@ #define TIME_UNIT_OFFSET 0x10 #define TIME_UNIT_MASK GENMASK(19, 16) =20 +/* bitmasks for RAPL MSRs, used by primitive access functions */ +#define ENERGY_STATUS_MASK GENMASK(31, 0) + +#define POWER_LIMIT1_MASK GENMASK(14, 0) +#define POWER_LIMIT1_ENABLE BIT(15) +#define POWER_LIMIT1_CLAMP BIT(16) + +#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32) +#define POWER_LIMIT2_ENABLE BIT_ULL(47) +#define POWER_LIMIT2_CLAMP BIT_ULL(48) +#define POWER_HIGH_LOCK BIT_ULL(63) +#define POWER_LOW_LOCK BIT(31) + +#define POWER_LIMIT4_MASK GENMASK(12, 0) + +#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17) +#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49) + +#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32) +#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16) +#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48) +#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0) + +#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0) +#define PP_POLICY_MASK GENMASK(4, 0) + +/* + * SPR has different layout for Psys Domain PowerLimit registers. + * There are 17 bits of PL1 and PL2 instead of 15 bits. + * The Enable bits and TimeWindow bits are also shifted as a result. + */ +#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0) +#define PSYS_POWER_LIMIT1_ENABLE BIT(17) + +#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32) +#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) + +#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19) +#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51) + /* Sideband MBI registers */ #define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02 #define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF @@ -268,6 +308,64 @@ static u64 rapl_compute_time_window_atom(struct rapl_d= omain *rd, u64 value, return value ? value * rd->time_unit : rd->time_unit; } =20 +/* RAPL primitives for MSR I/F */ +static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] =3D { + /* name, mask, shift, msr index, unit divisor */ + [POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, = 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, = 32, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [POWER_LIMIT4] =3D PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, = 0, + RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), + [ENERGY_COUNTER] =3D PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MA= SK, 0, + RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), + [FW_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [FW_HIGH_LOCK] =3D PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL1_CLAMP] =3D PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [PL2_CLAMP] =3D PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, + RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), + [TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, = 17, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, = 49, + RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [THERMAL_SPEC_POWER] =3D PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, + POWER_INFO_THERMAL_SPEC_MASK, 0, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_POWER] =3D PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MIN_POWER] =3D PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, + RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), + [MAX_TIME_WINDOW] =3D PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, + POWER_INFO_MAX_TIME_WIN_MASK, 48, + RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), + [THROTTLED_TIME] =3D PRIMITIVE_INFO_INIT(THROTTLED_TIME, + PERF_STATUS_THROTTLE_TIME_MASK, 0, + RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), + [PRIORITY_LEVEL] =3D PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, = 0, + RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), + [PSYS_POWER_LIMIT1] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER= _LIMIT1_MASK, 0, + RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [PSYS_POWER_LIMIT2] =3D PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER= _LIMIT2_MASK, + 32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), + [PSYS_PL1_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIM= IT1_ENABLE, + 17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, + 0), + [PSYS_PL2_ENABLE] =3D PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIM= IT2_ENABLE, + 49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, + 0), + [PSYS_TIME_WINDOW1] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_= WINDOW1_MASK, + 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), + [PSYS_TIME_WINDOW2] =3D PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_= WINDOW2_MASK, + 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), +}; + static const struct rapl_defaults rapl_defaults_core =3D { .floor_freq_reg_addr =3D 0, .check_unit =3D rapl_default_check_unit, @@ -418,6 +516,7 @@ static int rapl_msr_probe(struct platform_device *pdev) rapl_msr_priv->read_raw =3D rapl_msr_read_raw; rapl_msr_priv->write_raw =3D rapl_msr_write_raw; rapl_msr_priv->defaults =3D (const struct rapl_defaults *)pdev->dev.platf= orm_data; + rapl_msr_priv->rpi =3D rpi_msr; =20 if (id) { rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |=3D BIT(POWER_LIMIT4); --=20 2.43.0