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Fri, 13 Mar 2026 09:53:47 -0700 From: Zhi Wang To: , , , , , , CC: , , , , , , , , , , , , , , , , "Zhi Wang" , Dirk Behme Subject: [RFC v2 01/10] rust: pci: expose sriov_get_totalvfs() helper Date: Fri, 13 Mar 2026 18:53:25 +0200 Message-ID: <20260313165336.935771-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260313165336.935771-1-zhiw@nvidia.com> References: <20260313165336.935771-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000013:EE_|LV8PR12MB9641:EE_ X-MS-Office365-Filtering-Correlation-Id: ee72e3e7-83d2-4d06-632b-08de81212855 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|7416014|56012099003|18002099003|22082099003; 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charset="utf-8" Add a wrapper for the `pci_sriov_get_totalvfs()` helper, allowing drivers to query the number of total SR-IOV virtual functions a PCI device supports. Cc: Dirk Behme Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- rust/helpers/pci.c | 7 +++++++ rust/kernel/pci.rs | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/rust/helpers/pci.c b/rust/helpers/pci.c index 5043c9909d44..a3072fbe2871 100644 --- a/rust/helpers/pci.c +++ b/rust/helpers/pci.c @@ -29,6 +29,13 @@ __rust_helper u32 rust_helper_pci_ext_cap_next(u32 heade= r) return PCI_EXT_CAP_NEXT(header); } =20 +#ifndef CONFIG_PCI_IOV +__rust_helper int rust_helper_pci_sriov_get_totalvfs(struct pci_dev *dev) +{ + return pci_sriov_get_totalvfs(dev); +} +#endif + #ifndef CONFIG_PCI_MSI __rust_helper int rust_helper_pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index fc9c8e2077b2..c787f62b7f53 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -450,6 +450,20 @@ pub fn pci_class(&self) -> Class { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class }) } + + /// Returns total number of VFs, or `Err(ENODEV)` if none available. + pub fn sriov_get_totalvfs(&self) -> Result { + // SAFETY: `self.as_raw()` is a valid pointer to a `struct pci_dev= `. + let vfs =3D unsafe { bindings::pci_sriov_get_totalvfs(self.as_raw(= )) }; + + if vfs =3D=3D 0 { + return Err(ENODEV); + } + + // `pci_sriov_get_totalvfs` reads from the SR-IOV total_VFs field = (u16 + // in the PCI spec), so non-zero values always fit in u16. + Ok(vfs.try_into()?) + } } =20 impl Device { --=20 2.51.0 From nobody Tue Apr 7 09:46:55 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010036.outbound.protection.outlook.com [52.101.56.36]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EFE63988F4; Fri, 13 Mar 2026 16:54:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.36 ARC-Seal: i=2; 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charset="utf-8" FSP supports multiple protocols (COT, PRC) with different message types, all sharing the same MCTP and NVDM header format. Extract common headers into FspMessageHeader with a new() constructor that builds standard MCTP/NVDM headers using the bitfield types. Rename FspMessage to FspCotMessage for clarity. The COT message construction is simplified to FspMessageHeader::new(NVDM_TYPE_COT). Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/fsp.rs | 46 ++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 1bd2ce997d4a..477ed719b757 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -189,24 +189,46 @@ struct NvdmPayloadCot { gsp_boot_args_sysmem_offset: u64, } =20 -/// Complete FSP message structure with MCTP and NVDM headers. +/// Common MCTP and NVDM headers shared by all FSP messages. #[repr(C, packed)] #[derive(Clone, Copy)] -struct FspMessage { +struct FspMessageHeader { mctp_header: u32, nvdm_header: u32, +} + +// SAFETY: FspMessageHeader is a packed C struct with only integral fields. +unsafe impl AsBytes for FspMessageHeader {} + +// SAFETY: FspMessageHeader is a packed C struct with only integral fields. +unsafe impl FromBytes for FspMessageHeader {} + +impl FspMessageHeader { + /// Construct a standard FSP message header for the given NVDM type. + fn new(nvdm_type: NvdmType) -> Self { + Self { + mctp_header: MctpHeader::single_packet().raw(), + nvdm_header: NvdmHeader::new(nvdm_type).raw(), + } + } +} + +/// Complete FSP COT (Chain of Trust) message structure. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspCotMessage { + header: FspMessageHeader, cot: NvdmPayloadCot, } =20 -// SAFETY: FspMessage is a packed C struct with only integral fields. -unsafe impl AsBytes for FspMessage {} +// SAFETY: FspCotMessage is a packed C struct with only integral fields. +unsafe impl AsBytes for FspCotMessage {} =20 /// Complete FSP response structure with MCTP and NVDM headers. #[repr(C, packed)] #[derive(Clone, Copy)] struct FspResponse { - mctp_header: u32, - nvdm_header: u32, + header: FspMessageHeader, response: NvdmPayloadCommandResponse, } =20 @@ -222,7 +244,7 @@ pub(crate) trait MessageToFsp: AsBytes { const NVDM_TYPE: u32; } =20 -impl MessageToFsp for FspMessage { +impl MessageToFsp for FspCotMessage { const NVDM_TYPE: u32 =3D NvdmType::Cot as u32; } =20 @@ -405,10 +427,8 @@ pub(crate) fn boot_fmc( let frts_size: u32 =3D if !args.resume { SZ_1M as u32 } else { 0 }; =20 let msg =3D KBox::new( - FspMessage { - mctp_header: MctpHeader::single_packet().raw(), - nvdm_header: NvdmHeader::new(NvdmType::Cot).raw(), - + FspCotMessage { + header: FspMessageHeader::new(NvdmType::Cot), cot: NvdmPayloadCot { version: args.chipset.fsp_cot_version().ok_or(ENOTSUPP= )?.raw(), size: u16::try_from(core::mem::size_of::()) @@ -469,8 +489,8 @@ fn send_sync_fsp( =20 let response =3D FspResponse::from_bytes(&response_buf[..]).ok_or(= EIO)?; =20 - let mctp_header: MctpHeader =3D response.mctp_header.into(); - let nvdm_header: NvdmHeader =3D response.nvdm_header.into(); + let mctp_header: MctpHeader =3D response.header.mctp_header.into(); + let nvdm_header: NvdmHeader =3D response.header.nvdm_header.into(); let command_nvdm_type =3D response.response.command_nvdm_type; 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Fri, 13 Mar 2026 09:54:07 -0700 From: Zhi Wang To: , , , , , , CC: , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [RFC v2 03/10] gpu: nova-core: return FSP response buffer to caller Date: Fri, 13 Mar 2026 18:53:27 +0200 Message-ID: <20260313165336.935771-4-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260313165336.935771-1-zhiw@nvidia.com> References: <20260313165336.935771-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000014:EE_|MW6PR12MB8835:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c2e05d8-c844-4744-5e2d-08de81213578 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700016|1800799024|82310400026|56012099003|22082099003|18002099003; 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charset="utf-8" Change send_sync_fsp() to return the raw response buffer after validating the common MCTP/NVDM headers and error code. This allows callers to perform protocol-specific parsing on the response payload, which is needed for the upcoming PRC protocol support. For the existing COT caller, the response buffer is unused. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/fsp.rs | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 477ed719b757..69e48b655879 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -454,12 +454,13 @@ pub(crate) fn boot_fmc( } =20 /// Send message to FSP and wait for response. + /// Returns the raw response buffer for protocol-specific parsing. fn send_sync_fsp( dev: &device::Device, bar: &crate::driver::Bar0, fsp_falcon: &crate::falcon::Falcon, msg: &M, - ) -> Result + ) -> Result> where M: MessageToFsp, { @@ -482,12 +483,13 @@ fn send_sync_fsp( response_buf.resize(packet_size, 0, GFP_KERNEL)?; fsp_falcon.recv_msg(bar, &mut response_buf, packet_size)?; =20 - if response_buf.len() < core::mem::size_of::() { + let min_size =3D core::mem::size_of::(); + if response_buf.len() < min_size { dev_err!(dev, "FSP response too small: {}\n", response_buf.len= ()); return Err(EIO); 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charset="utf-8" Add support for querying the vGPU mode configuration from FSP using the PRC (Product Reconfiguration Control) protocol. PRC is an API system exposed through FSP's Management Partition that allows querying device configuration "knobs" without firmware updates. Add a VgpuMode enum that validates the raw PRC response value, returning an error for unexpected values. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/fsp.rs | 175 +++++++++++++++++++++++++++++++--- drivers/gpu/nova-core/mctp.rs | 2 + 2 files changed, 165 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs index 69e48b655879..e342bbf733b3 100644 --- a/drivers/gpu/nova-core/fsp.rs +++ b/drivers/gpu/nova-core/fsp.rs @@ -23,12 +23,18 @@ }, }; =20 -use crate::regs; - -use crate::mctp::{ - MctpHeader, - NvdmHeader, - NvdmType, // +use crate::{ + driver::Bar0, + falcon::{ + fsp::Fsp as FspEngine, + Falcon, // + }, + mctp::{ + MctpHeader, + NvdmHeader, + NvdmType, // + }, + regs, }; =20 /// FSP Chain of Trust protocol version. @@ -55,6 +61,23 @@ pub(crate) const fn raw(self) -> u16 { /// FSP secure boot completion timeout in milliseconds. const FSP_SECURE_BOOT_TIMEOUT_MS: i64 =3D 4000; =20 +/// PRC (Product Reconfiguration Control) protocol constants. +/// +/// PRC is an API system exposed through FSP's Management Partition that a= llows +/// querying and modifying device configuration "knobs" without firmware u= pdates. +/// Each knob is identified by a unique object ID and controls a specific = device +/// behavior (e.g., vGPU mode, ECC, confidential computing). +mod prc { + /// Sub-command to read a PRC knob value. + pub(super) const SUBCMD_READ: u8 =3D 0x0c; + + /// PRC object ID for vGPU mode configuration (knob ID 41). + pub(super) const OBJECT_VGPU_MODE: u8 =3D 0x29; + + /// Request the active knob value (currently effective this boot). + pub(super) const FLAG_ACTIVE: u8 =3D 1 << 1; +} + /// GSP FMC initialization parameters. #[repr(C)] #[derive(Debug, Clone, Copy, Default)] @@ -171,7 +194,61 @@ struct NvdmPayloadCommandResponse { error_code: u32, } =20 -/// NVDM (NVIDIA Device Management) COT (Chain of Trust) payload structure. +// SAFETY: NvdmPayloadCommandResponse is a packed C struct with only integ= ral fields. +unsafe impl FromBytes for NvdmPayloadCommandResponse {} + +/// vGPU operating mode as reported by FSP via the PRC protocol. +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum VgpuMode { + /// vGPU support is disabled on this GPU. + Disabled =3D 0, + /// vGPU support is enabled on this GPU. + Enabled =3D 1, +} + +impl TryFrom for VgpuMode { + type Error =3D kernel::error::Error; + + fn try_from(value: u16) -> Result { + match value { + 0 =3D> Ok(VgpuMode::Disabled), + 1 =3D> Ok(VgpuMode::Enabled), + _ =3D> Err(EINVAL), + } + } +} + +/// PRC message payload. +/// +/// Sent to FSP to query or modify a device configuration knob. +/// The response includes the common FSP response header followed by +/// a [`NvdmPayloadPrcResponse`] with the knob's current state value. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct NvdmPayloadPrc { + sub_message_id: u8, + flags: u8, + object_id: u8, + reserved: u8, +} + +// SAFETY: NvdmPayloadPrc is a packed C struct with only integral fields. +unsafe impl AsBytes for NvdmPayloadPrc {} + +/// PRC response payload containing the knob state value. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct NvdmPayloadPrcResponse { + value_low: u8, + value_high: u8, + reserved1: u8, + reserved2: u8, +} + +// SAFETY: NvdmPayloadPrcResponse is a packed C struct with only integral = fields. +unsafe impl FromBytes for NvdmPayloadPrcResponse {} + +/// NVDM (NVIDIA Vendor Defined Message) COT (Chain of Trust) payload stru= cture. /// This is the main message payload sent to FSP for Chain of Trust. #[repr(C, packed)] #[derive(Clone, Copy)] @@ -224,6 +301,17 @@ struct FspCotMessage { // SAFETY: FspCotMessage is a packed C struct with only integral fields. unsafe impl AsBytes for FspCotMessage {} =20 +/// Complete FSP PRC message. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspPrcMessage { + header: FspMessageHeader, + prc: NvdmPayloadPrc, +} + +// SAFETY: FspPrcMessage is a packed C struct with only integral fields. +unsafe impl AsBytes for FspPrcMessage {} + /// Complete FSP response structure with MCTP and NVDM headers. #[repr(C, packed)] #[derive(Clone, Copy)] @@ -235,6 +323,18 @@ struct FspResponse { // SAFETY: FspResponse is a packed C struct with only integral fields. unsafe impl FromBytes for FspResponse {} =20 +/// Complete FSP PRC response including the knob state payload. +#[repr(C, packed)] +#[derive(Clone, Copy)] +struct FspPrcResponse { + header: FspMessageHeader, + response: NvdmPayloadCommandResponse, + prc_data: NvdmPayloadPrcResponse, +} + +// SAFETY: FspPrcResponse is a packed C struct with only integral fields. +unsafe impl FromBytes for FspPrcResponse {} + /// Trait implemented by types representing a message to send to FSP. /// /// This provides [`Fsp::send_sync_fsp`] with the information it needs to = send @@ -305,17 +405,68 @@ pub(crate) fn boot_params_dma_handle(&self) -> u64 { } } =20 +impl MessageToFsp for FspPrcMessage { + const NVDM_TYPE: u32 =3D NvdmType::Prc as u32; +} + /// FSP interface for Hopper/Blackwell GPUs. pub(crate) struct Fsp; =20 impl Fsp { + /// Read vGPU mode from FSP using the PRC protocol. + /// + /// Queries FSP's Management Partition for the active vGPU mode knob v= alue. + /// Returns [`VgpuMode::Enabled`] if vGPU support is active on this GP= U, + /// [`VgpuMode::Disabled`] otherwise. + pub(crate) fn read_vgpu_mode( + dev: &device::Device, + bar: &Bar0, + fsp_falcon: &Falcon, + ) -> Result { + let msg =3D KBox::new( + FspPrcMessage { + header: FspMessageHeader::new(NvdmType::Prc), + prc: NvdmPayloadPrc { + sub_message_id: prc::SUBCMD_READ, + flags: prc::FLAG_ACTIVE, + object_id: prc::OBJECT_VGPU_MODE, + reserved: 0, + }, + }, + GFP_KERNEL, + )?; + + let response_buf =3D Self::send_sync_fsp(dev, bar, fsp_falcon, &*m= sg)?; + + let prc_resp_size =3D core::mem::size_of::(); + if response_buf.len() < prc_resp_size { + dev_err!( + dev, + "PRC response too small: {} bytes (expected {})\n", + response_buf.len(), + prc_resp_size + ); + return Err(EIO); + } + + let prc_response =3D + FspPrcResponse::from_bytes(&response_buf[..prc_resp_size]).ok_= or(EIO)?; + + let raw_value =3D u16::from(prc_response.prc_data.value_low) + | (u16::from(prc_response.prc_data.value_high) << 8); + + VgpuMode::try_from(raw_value).inspect_err(|_| { + dev_err!(dev, "unexpected vGPU mode value: {:#x}\n", raw_value= ); + }) + } + /// Wait for FSP secure boot completion. /// /// Polls the thermal scratch register until FSP signals boot completi= on /// or timeout occurs. pub(crate) fn wait_secure_boot( dev: &device::Device, - bar: &crate::driver::Bar0, + bar: &Bar0, arch: crate::gpu::Architecture, ) -> Result { debug_assert!( @@ -403,8 +554,8 @@ pub(crate) fn extract_fmc_signatures( /// to FSP, and waits for the response. pub(crate) fn boot_fmc( dev: &device::Device, - bar: &crate::driver::Bar0, - fsp_falcon: &crate::falcon::Falcon, + bar: &Bar0, + fsp_falcon: &Falcon, args: &FmcBootArgs<'_>, ) -> Result { dev_dbg!(dev, "Starting FSP boot sequence for {}\n", args.chipset); @@ -457,8 +608,8 @@ pub(crate) fn boot_fmc( /// Returns the raw response buffer for protocol-specific parsing. fn send_sync_fsp( dev: &device::Device, - bar: &crate::driver::Bar0, - fsp_falcon: &crate::falcon::Falcon, + bar: &Bar0, + fsp_falcon: &Falcon, msg: &M, ) -> Result> where diff --git a/drivers/gpu/nova-core/mctp.rs b/drivers/gpu/nova-core/mctp.rs index c4e36a46fd69..5c53e156d482 100644 --- a/drivers/gpu/nova-core/mctp.rs +++ b/drivers/gpu/nova-core/mctp.rs @@ -10,6 +10,8 @@ #[derive(Debug, Clone, Copy, PartialEq, Eq)] #[repr(u32)] pub(crate) enum NvdmType { + /// PRC (Product Reconfiguration Control) message. + Prc =3D 0x13, /// Chain of Trust boot message. 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Fri, 13 Mar 2026 09:54:26 -0700 From: Zhi Wang To: , , , , , , CC: , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [RFC v2 05/10] gpu: nova-core: add FSP and PRC protocol documentation Date: Fri, 13 Mar 2026 18:53:29 +0200 Message-ID: <20260313165336.935771-6-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260313165336.935771-1-zhiw@nvidia.com> References: <20260313165336.935771-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000012:EE_|DS7PR12MB9551:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a8210e2-0226-43a4-05c6-08de812141ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700016|56012099003|18002099003|22082099003|7142099003; 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charset="utf-8" Add documentation for the Falcon Security Processor (FSP) interface covering the simplified Hopper/Blackwell boot flow, the Chain of Trust (COT) message protocol, the MCTP/NVDM message format, and the Product Reconfiguration Control (PRC) protocol used to query device configuration knobs such as vGPU mode. Suggested-by: Joel Fernandes Signed-off-by: Zhi Wang --- Documentation/gpu/nova/core/fsp.rst | 135 ++++++++++++++++++++++++++++ Documentation/gpu/nova/index.rst | 1 + 2 files changed, 136 insertions(+) create mode 100644 Documentation/gpu/nova/core/fsp.rst diff --git a/Documentation/gpu/nova/core/fsp.rst b/Documentation/gpu/nova/c= ore/fsp.rst new file mode 100644 index 000000000000..dedad680b20e --- /dev/null +++ b/Documentation/gpu/nova/core/fsp.rst @@ -0,0 +1,135 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +FSP (Falcon Security Processor) and Secure Boot +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This document describes the role of the FSP in the GPU boot sequence on +Hopper and Blackwell GPUs, It also provides a brief overview of the PRC +(Product Reconfiguration Control) protocol used to query device +configuration through FSP. + +What is FSP? +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Falcon Security Processor (FSP) is the GPU's Internal Root of Trust +(IROT). It is a dedicated security processor that boots from immutable ROM +(Boot ROM) inside the GPU and is responsible for establishing the Chain of +Trust before any other firmware is allowed to run. + +FSP runs independently of the host CPU and starts executing as soon as the +GPU is powered on. By the time the nova-core driver is loaded, FSP has +already completed its own secure boot and is ready to accept commands from +the driver. + +Simplified boot flow (Hopper/Blackwell) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Starting with Hopper, the boot flow is significantly simplified compared to +earlier GPU generations like Ampere. + +On an Ampere GPU, the boot verification chain involves multiple Falcon +engines and multiple ucode stages (see falcon.rst for details):: + + Hardware BROM (SEC2) + -> HS Booter (SEC2) + -> LS GSP-RM (GSP) + +The driver must extract ucode from VBIOS, manage SEC2 and GSP, and +orchestrate the Booter to load GSP-RM. This involves FWSEC-FRTS, devinit, +and the Booter stages. + +On Hopper/Blackwell GPUs, FSP replaces this multi-stage process with a +single message-driven interface:: + + FSP (hardware root of trust, boots from ROM) + -> FMC (Falcon Microcontroller, verified by FSP) + -> GSP-RM (verified and loaded by FMC) + +The driver only needs to: + +1. Wait for FSP to complete its own secure boot (polling a scratch registe= r). +2. Send a Chain of Trust (COT) message to FSP with the FMC firmware locati= on, + cryptographic signatures, and GSP boot parameters. +3. FSP authenticates the FMC firmware and boots it, FMC in turn loads GSP-= RM. + +There is no SEC2 involvement, no Booter ucode, and no FWSEC-FRTS stage. The +entire secure boot is driven by a single FSP message exchange. + +Chain of Trust (COT) protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +The Chain of Trust establishes a cryptographically enforced boot sequence, +ensuring the GPU reaches a known, trusted state. + +The driver communicates with FSP using a message queue (Falcon MSGQ +interface). Each message consists of an MCTP (Management Component Transpo= rt +Protocol) transport header and an NVDM (NVIDIA Vendor Defined Message) hea= der, +followed by a protocol-specific payload. + +For Chain of Trust, the payload includes: + +- The system memory address of the FMC firmware image. +- Cryptographic material: a SHA-384 hash, RSA-3K public key, and RSA-3K + signature extracted from the FMC ELF firmware. +- FRTS (Firmware Runtime Services) region information (vidmem offset and s= ize). +- The system memory address of the GSP boot arguments structure. + +FSP verifies the signature against the provided public key and hash, and if +verification succeeds, boots the FMC. The FMC then authenticates and launc= hes +GSP-RM. + +The message flow is:: + + nova-core FSP + | | + | 1. Poll scratch register | + | (wait for FSP boot complete) | + | | + | 2. COT message ------------> | + | (FMC addr, signatures, | + | boot params) | + | | + | |--- Verify FMC signature + | |--- Boot FMC + | |--- FMC loads GSP-RM + | | + | 3. COT response <------------ | + | (success/error) | + | | + +FSP message format +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +All FSP messages share a common header format consisting of two 32-bit wor= ds: + +MCTP header (Management Component Transport Protocol): + +- Bit 31: SOM (Start of Message) +- Bit 30: EOM (End of Message) +- Bits 29:28: Packet sequence number +- Bits 23:16: Source Endpoint ID + +NVDM header (NVIDIA Vendor Defined Message): + +- Bits 6:0: MCTP message type (0x7e =3D vendor-defined PCI) +- Bits 23:8: PCI vendor ID (0x10de =3D NVIDIA) +- Bits 31:24: NVDM type (0x14 =3D COT, 0x13 =3D PRC, 0x15 =3D FSP response) + +PRC (Product Reconfiguration Control) protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PRC is an API system exposed through FSP's Management Partition that allows +querying and modifying device configuration without firmware updates. + +Configuration parameters are called "knobs". Each knob has a unique object +ID and controls a specific device behavior. Examples include vGPU mode, ECC +enable, confidential computing mode, and NVLINK configuration. + +The nova-core driver uses PRC to read the vGPU mode knob (object ID 0x29) +during early boot, before firmware loading, to determine whether the GPU +should operate in vGPU mode. + +The PRC message format follows the same MCTP/NVDM header structure as COT, +with NVDM type 0x13. The payload contains: + +- A sub-command (e.g., 0x0c for read). +- Flags indicating which value to read (bit 0 =3D persistent, bit 1 =3D ac= tive). +- The knob object ID. + +The response includes the common FSP response header (with error status) +followed by the knob's 16-bit state value. diff --git a/Documentation/gpu/nova/index.rst b/Documentation/gpu/nova/inde= x.rst index e39cb3163581..1783513cbd05 100644 --- a/Documentation/gpu/nova/index.rst +++ b/Documentation/gpu/nova/index.rst @@ -30,5 +30,6 @@ vGPU manager VFIO driver and the nova-drm driver. core/todo core/vbios core/devinit + core/fsp core/fwsec core/falcon --=20 2.51.0 From nobody Tue Apr 7 09:46:56 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013022.outbound.protection.outlook.com [40.107.201.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55C4E3CAE7D; Fri, 13 Mar 2026 16:55:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Introduce a kernel module param to set vGPU support in nova-core. vgpu_support =3D 1 (default): automatic The driver automatically enables or disables vGPU support based on if the GPU advertises SRIOV caps. vgpu_support =3D 0: disabled Explicitly disables vGPU support. The driver will not enable vGPU support regardless. Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gpu.rs | 37 +++++++++++++++++-- drivers/gpu/nova-core/gsp.rs | 25 +++++++++++++ drivers/gpu/nova-core/gsp/boot.rs | 59 +++++++++++++++++------------- drivers/gpu/nova-core/nova_core.rs | 15 ++++++++ drivers/gpu/nova-core/vgpu.rs | 37 +++++++++++++++++++ 5 files changed, 143 insertions(+), 30 deletions(-) create mode 100644 drivers/gpu/nova-core/vgpu.rs diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index e9d07750fafe..e1c16e1b9ec4 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -23,8 +23,12 @@ fb::SysmemFlush, fsp::FspCotVersion, gfw, - gsp::Gsp, + gsp::{ + Gsp, + GspBootContext, // + }, regs, + vgpu::Vgpu, // }; =20 macro_rules! define_chipset { @@ -180,6 +184,16 @@ pub(crate) enum Architecture { } =20 impl Architecture { + /// Whether this architecture uses SEC2 for GSP boot (vs FSP Chain of = Trust). + pub(crate) const fn uses_sec2_boot(&self) -> bool { + matches!(self, Self::Turing | Self::Ampere | Self::Ada) + } + + /// Whether this architecture supports vGPU. + pub(crate) const fn supports_vgpu(&self) -> bool { + matches!(self, Self::Ada | Self::Blackwell) + } + /// Returns the DMA mask supported by this architecture. /// /// Hopper and Blackwell support 52-bit DMA addresses, while earlier a= rchitectures @@ -313,7 +327,7 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Resul= t { pub(crate) struct Gpu { spec: Spec, /// MMIO mapping of PCI BAR 0 - bar: Arc>, + pub bar: Arc>, /// System memory page required for flushing all pending GPU-side memo= ry writes done through /// PCIE into system memory, via sysmembar (A GPU-initiated HW memory-= barrier operation). sysmem_flush: SysmemFlush, @@ -323,7 +337,8 @@ pub(crate) struct Gpu { sec2_falcon: Falcon, /// GSP runtime data. Temporarily an empty placeholder. #[pin] - gsp: Gsp, + pub(crate) gsp: Gsp, + vgpu: Vgpu, } =20 impl Gpu { @@ -351,6 +366,8 @@ pub(crate) fn new<'a>( } }, =20 + vgpu: Vgpu::new(pdev, chipset)?, + sysmem_flush: SysmemFlush::register(pdev.as_ref(), bar, ch= ipset)?, =20 gsp_falcon: Falcon::new( @@ -363,7 +380,19 @@ pub(crate) fn new<'a>( =20 gsp <- Gsp::new(pdev), =20 - _: { gsp.boot(pdev, bar, chipset, gsp_falcon, sec2_falcon)= ? }, + _: { + let mut ctx =3D GspBootContext { + pdev, + bar, + chipset, + gsp_falcon, + sec2_falcon, + fsp_falcon: None, + vgpu_requested: vgpu.vgpu_requested, + }; + gsp.boot(&mut ctx)?; + vgpu.vgpu_enabled =3D ctx.vgpu_requested; + }, =20 bar: devres_bar, spec, diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 1756ab4732e7..9435c7430dfe 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -31,6 +31,14 @@ }; =20 use crate::{ + driver::Bar0, + falcon::{ + fsp::Fsp as FspFalcon, + gsp::Gsp as GspFalcon, + sec2::Sec2 as Sec2Falcon, + Falcon, // + }, + gpu::Chipset, gsp::cmdq::Cmdq, gsp::fw::{ GspArgumentsPadded, @@ -45,6 +53,23 @@ /// Number of GSP pages to use in a RM log buffer. const RM_LOG_BUFFER_NUM_PAGES: usize =3D 0x10; =20 +/// Common context for the GSP boot process. +pub(crate) struct GspBootContext<'a> { + pub(crate) pdev: &'a pci::Device, + pub(crate) bar: &'a Bar0, + pub(crate) chipset: Chipset, + pub(crate) gsp_falcon: &'a Falcon, + pub(crate) sec2_falcon: &'a Falcon, + pub(crate) fsp_falcon: Option>, + pub(crate) vgpu_requested: bool, +} + +impl GspBootContext<'_> { + pub(crate) fn dev(&self) -> &device::Device { + self.pdev.as_ref() + } +} + /// Array of page table entries, as understood by the GSP bootloader. #[repr(C)] struct PteArray([u64; NUM_ENTRIES]); diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index b2037ecb9a7f..4238df5c8104 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -5,7 +5,6 @@ dma::Coherent, io::poll::read_poll_timeout, io_write, - pci, prelude::*, time::Delta, // }; @@ -36,12 +35,10 @@ }, fsp::{ FmcBootArgs, - Fsp, // - }, - gpu::{ - Architecture, - Chipset, // + Fsp, + VgpuMode, // }, + gpu::Chipset, gsp::{ commands, fw::LibosMemoryRegionInitArgument, @@ -98,7 +95,7 @@ fn lockdown_released(&self, bar: &Bar0, fmc_boot_params_a= ddr: u64) -> bool { return true; } =20 - let hwcfg2 =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &crate::f= alcon::gsp::Gsp::ID); + let hwcfg2 =3D regs::NV_PFALCON_FALCON_HWCFG2::read(bar, &Gsp::ID); !hwcfg2.riscv_br_priv_lockdown() } } @@ -255,9 +252,8 @@ fn boot_via_fsp( gsp_falcon: &Falcon, wpr_meta: &Coherent, libos: &Coherent<[LibosMemoryRegionInitArgument]>, + fsp_falcon: &Falcon, ) -> Result { - let fsp_falcon =3D Falcon::::new(dev, chipset)?; - Fsp::wait_secure_boot(dev, bar, chipset.arch())?; =20 let fsp_fw =3D FspFirmware::new(dev, chipset, FIRMWARE_VERSION)?; @@ -275,7 +271,7 @@ fn boot_via_fsp( &signatures, )?; =20 - Fsp::boot_fmc(dev, bar, &fsp_falcon, &args)?; + Fsp::boot_fmc(dev, bar, fsp_falcon, &args)?; =20 let fmc_boot_params_addr =3D args.boot_params_dma_handle(); Self::wait_for_gsp_lockdown_release(dev, bar, gsp_falcon, fmc_boot= _params_addr)?; @@ -320,18 +316,31 @@ fn wait_for_gsp_lockdown_release( /// Upon return, the GSP is up and running, and its runtime object giv= en as return value. pub(crate) fn boot( self: Pin<&mut Self>, - pdev: &pci::Device, - bar: &Bar0, - chipset: Chipset, - gsp_falcon: &Falcon, - sec2_falcon: &Falcon, + ctx: &mut super::GspBootContext<'_>, ) -> Result { - let dev =3D pdev.as_ref(); - let uses_sec2 =3D matches!( - chipset.arch(), - Architecture::Turing | Architecture::Ampere | Architecture::Ada - ); + let bar =3D ctx.bar; + let chipset =3D ctx.chipset; + let arch =3D chipset.arch(); + let pdev =3D ctx.pdev; + let gsp_falcon =3D ctx.gsp_falcon; + let sec2_falcon =3D ctx.sec2_falcon; + + // For FSP-based architectures (Blackwell), refine the vGPU request + // by reading the PRC knob from FSP - only keep the request if the + // hardware knob is set. + // + // SEC2-based architectures (Ada) keep the initial request as-is + // (module parameter + SR-IOV, already filtered by Vgpu::new). + if !arch.uses_sec2_boot() { + let fsp_falcon =3D Falcon::::new(ctx.dev(), chipset= )?; + Fsp::wait_secure_boot(ctx.dev(), bar, arch)?; + let vgpu_mode =3D Fsp::read_vgpu_mode(ctx.dev(), bar, &fsp_fal= con)?; + dev_dbg!(ctx.dev(), "vGPU mode: {:?}\n", vgpu_mode); + ctx.fsp_falcon =3D Some(fsp_falcon); + ctx.vgpu_requested &=3D vgpu_mode =3D=3D VgpuMode::Enabled; + } =20 + let dev =3D ctx.dev(); let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIRMW= ARE_VERSION), GFP_KERNEL)?; =20 let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; @@ -341,7 +350,7 @@ pub(crate) fn boot( io_write!(wpr_meta, , GspFwWprMeta::new(&gsp_fw, &fb_layout)); =20 // Architecture-specific boot path - if uses_sec2 { + if arch.uses_sec2_boot() { // SEC2 path: send commands before GSP reset/boot (original or= der). self.cmdq .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset))?; @@ -366,6 +375,7 @@ pub(crate) fn boot( gsp_falcon, &wpr_meta, &self.libos, + ctx.fsp_falcon.as_ref().ok_or(ENODEV)?, )?; } =20 @@ -383,10 +393,7 @@ pub(crate) fn boot( dev_dbg!(dev, "RISC-V active? {}\n", gsp_falcon.is_riscv_active(ba= r)); =20 // For FSP path, send commands after GSP becomes active. - if matches!( - chipset.arch(), - Architecture::Hopper | Architecture::Blackwell - ) { + if !arch.uses_sec2_boot() { self.cmdq .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset))?; self.cmdq @@ -394,7 +401,7 @@ pub(crate) fn boot( } =20 // SEC2-based architectures need to run the GSP sequencer - if uses_sec2 { + if arch.uses_sec2_boot() { let libos_handle =3D self.libos.dma_handle(); let seq_params =3D GspSequencerParams { bootloader_app_version: gsp_fw.bootloader.app_version, diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nov= a_core.rs index c554ec544ddd..bccdbb412dd0 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -27,6 +27,7 @@ mod regs; mod sbuffer; mod vbios; +mod vgpu; =20 pub(crate) const MODULE_NAME: &core::ffi::CStr =3D ::NAME; =20 @@ -75,6 +76,20 @@ fn init(module: &'static kernel::ThisModule) -> impl Pin= Init { description: "Nova Core GPU driver", license: "GPL v2", firmware: [], + params: { + // vgpu_support =3D 1 (default): automatic + // + // The driver automatically enables or disables vGPU support based= on if the GPU + // advertises SRIOV caps. + // + // vgpu_support =3D 0: disabled + // + // Explicitly disables vGPU support. The driver will not enable vG= PU support regardless. + vgpu_support: u32 { + default: 1, + description: "Enable vGPU support - (1 =3D auto (default), 0 = =3D disable)", + }, + }, } =20 kernel::module_firmware!(firmware::ModInfoBuilder); diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs new file mode 100644 index 000000000000..d35081a088cf --- /dev/null +++ b/drivers/gpu/nova-core/vgpu.rs @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 + +use kernel::{ + device, + pci, + prelude::*, // +}; + +use crate::{ + gpu::Chipset, + module_parameters, // +}; + +pub(crate) struct Vgpu { + pub(crate) vgpu_requested: bool, + pub(crate) vgpu_enabled: bool, + pub total_vfs: u16, +} + +impl Vgpu { + pub(crate) fn new(pdev: &pci::Device, chipset: Chipset)= -> Result { + let total_vfs =3D if chipset.arch().supports_vgpu() { + match *module_parameters::vgpu_support.value() { + 0 =3D> 0, + _ =3D> pdev.sriov_get_totalvfs().unwrap_or(0), + } + } else { + 0 + }; + + Ok(Vgpu { + vgpu_requested: total_vfs > 0, + vgpu_enabled: false, + total_vfs, + }) + } +} --=20 2.51.0 From nobody Tue Apr 7 09:46:56 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011004.outbound.protection.outlook.com [52.101.52.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B9D93CAE61; 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Fri, 13 Mar 2026 09:54:52 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 13 Mar 2026 09:54:52 -0700 Received: from inno-dell.nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Fri, 13 Mar 2026 09:54:44 -0700 From: Zhi Wang To: , , , , , , CC: , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [RFC v2 07/10] gpu: nova-core: populate GSP_VF_INFO when vGPU is enabled Date: Fri, 13 Mar 2026 18:53:31 +0200 Message-ID: <20260313165336.935771-8-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260313165336.935771-1-zhiw@nvidia.com> References: <20260313165336.935771-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000011:EE_|DS0PR12MB7509:EE_ X-MS-Office365-Filtering-Correlation-Id: 960908f6-bf3f-454b-dfbc-08de81214b28 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|1800799024|22082099003|56012099003|18002099003; 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The VF BAR information is stored in GSP_VF_INFO, which needs to be initialized and uploaded together with the GSP_SYSTEM_INFO. Populate GSP_VF_INFO when nova-core uploads the GSP_SYSTEM_INFO if NVIDIA vGPU is enabled. Cc: Joel Fernandes Cc: John Hubbard Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gsp/boot.rs | 15 ++++++++-- drivers/gpu/nova-core/gsp/commands.rs | 16 ++++++++-- drivers/gpu/nova-core/gsp/fw.rs | 38 ++++++++++++++++++++++++ drivers/gpu/nova-core/gsp/fw/commands.rs | 12 +++++++- 4 files changed, 74 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 4238df5c8104..921d5e892f8a 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -41,7 +41,10 @@ gpu::Chipset, gsp::{ commands, - fw::LibosMemoryRegionInitArgument, + fw::{ + GspVfInfo, + LibosMemoryRegionInitArgument, // + }, sequencer::{ GspSequencer, GspSequencerParams, // @@ -349,11 +352,17 @@ pub(crate) fn boot( let wpr_meta =3D Coherent::::zeroed(dev, GFP_KERNEL)= ?; io_write!(wpr_meta, , GspFwWprMeta::new(&gsp_fw, &fb_layout)); =20 + let vf_info =3D if ctx.vgpu_requested { + Some(GspVfInfo::new(ctx.pdev)?) + } else { + None + }; + // Architecture-specific boot path if arch.uses_sec2_boot() { // SEC2 path: send commands before GSP reset/boot (original or= der). self.cmdq - .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset))?; + .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset, vf_info))?; self.cmdq .send_command_no_wait(bar, commands::SetRegistry::new())?; =20 @@ -395,7 +404,7 @@ pub(crate) fn boot( // For FSP path, send commands after GSP becomes active. if !arch.uses_sec2_boot() { self.cmdq - .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset))?; + .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset, vf_info))?; self.cmdq .send_command_no_wait(bar, commands::SetRegistry::new())?; } diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index d31ee782ff8b..0445d05990e7 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -29,6 +29,7 @@ }, fw::{ commands::*, + GspVfInfo, MsgFunction, // }, }, @@ -39,12 +40,21 @@ pub(crate) struct SetSystemInfo<'a> { pdev: &'a pci::Device, chipset: Chipset, + vf_info: Option, } =20 impl<'a> SetSystemInfo<'a> { /// Creates a new `GspSetSystemInfo` command using the parameters of `= pdev`. - pub(crate) fn new(pdev: &'a pci::Device, chipset: Chips= et) -> Self { - Self { pdev, chipset } + pub(crate) fn new( + pdev: &'a pci::Device, + chipset: Chipset, + vf_info: Option, + ) -> Self { + Self { + pdev, + chipset, + vf_info, + } } } =20 @@ -55,7 +65,7 @@ impl<'a> CommandToGsp for SetSystemInfo<'a> { type InitError =3D Error; =20 fn init(&self) -> impl Init { - GspSetSystemInfo::init(self.pdev, self.chipset) + GspSetSystemInfo::init(self.pdev, self.chipset, self.vf_info) } } =20 diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index e5f8db74a677..6d56b9b920fb 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -10,7 +10,9 @@ use core::ops::Range; =20 use kernel::{ + device, dma::Coherent, + pci, prelude::*, ptr::{ Alignable, @@ -1309,3 +1311,39 @@ fn new(cmdq: &Cmdq) -> Self { }) } } + +/// VF information =E2=80=94 `gspVFInfo` in `GspSetSystemInfo`. +/// +/// Populated from the PCI SR-IOV extended capability when vGPU support +/// is enabled. +#[derive(Clone, Copy, Zeroable)] +#[repr(transparent)] +pub(crate) struct GspVfInfo(pub(crate) bindings::GSP_VF_INFO); + +impl GspVfInfo { + /// Reads SR-IOV capability data from the PCI extended configuration + /// space and builds the VF information required by GSP firmware. + pub(crate) fn new(pdev: &pci::Device) -> Result { + let total_vfs =3D pdev.sriov_get_totalvfs()?; + + let cfg =3D pdev.config_space_extended()?; + let sriov =3D pci::ExtSriovCapability::find(&cfg)?; + + Ok(GspVfInfo(bindings::GSP_VF_INFO { + totalVFs: u32::from(total_vfs), + firstVFOffset: u32::from(kernel::io_read!(sriov, .vf_offset)), + FirstVFBar0Address: u64::from(kernel::io_read!(sriov, .vf_bar[= 0]?)), + b64bitBar1: u8::from(sriov.vf_bar_is_64bit(1)?), + FirstVFBar1Address: sriov.read_vf_bar64_addr(1)?, + b64bitBar2: u8::from(sriov.vf_bar_is_64bit(3)?), + FirstVFBar2Address: sriov.read_vf_bar64_addr(3)?, + ..Zeroable::zeroed() + })) + } +} + +// SAFETY: Padding is explicit and does not contain uninitialized data. +unsafe impl AsBytes for GspVfInfo {} + +// SAFETY: This struct only contains integer types for which all bit patte= rns are valid. +unsafe impl FromBytes for GspVfInfo {} diff --git a/drivers/gpu/nova-core/gsp/fw/commands.rs b/drivers/gpu/nova-co= re/gsp/fw/commands.rs index c9822fcbc499..3edd451e531b 100644 --- a/drivers/gpu/nova-core/gsp/fw/commands.rs +++ b/drivers/gpu/nova-core/gsp/fw/commands.rs @@ -15,7 +15,10 @@ Architecture, Chipset, // }, - gsp::GSP_PAGE_SIZE, // + gsp::{ + fw::GspVfInfo, + GSP_PAGE_SIZE, // + }, }; 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Fri, 13 Mar 2026 09:55:01 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 13 Mar 2026 09:55:01 -0700 Received: from inno-dell.nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Fri, 13 Mar 2026 09:54:52 -0700 From: Zhi Wang To: , , , , , , CC: , , , , , , , , , , , , , , , , "Zhi Wang" , Timur Tabi Subject: [RFC v2 08/10] gpu: nova-core: set RMSetSriovMode when NVIDIA vGPU is enabled Date: Fri, 13 Mar 2026 18:53:32 +0200 Message-ID: <20260313165336.935771-9-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260313165336.935771-1-zhiw@nvidia.com> References: <20260313165336.935771-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000012:EE_|DS0PR12MB7900:EE_ X-MS-Office365-Filtering-Correlation-Id: 462867a3-442e-4605-2f74-08de81214e5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700016|56012099003|18002099003|22082099003; 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charset="utf-8" The registry object "RMSetSriovMode" is required to be set when vGPU is enabled. Set "RMSetSriovMode" to 1 when nova-core is loading the GSP firmware and initialize the GSP registry objects, if vGPU is enabled. Cc: Timur Tabi Cc: Joel Fernandes Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/gsp/boot.rs | 4 +- drivers/gpu/nova-core/gsp/commands.rs | 89 +++++++++++++++++---------- drivers/gpu/nova-core/gsp/fw.rs | 44 +++++++++++++ 3 files changed, 104 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 921d5e892f8a..ed8729041d46 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -364,7 +364,7 @@ pub(crate) fn boot( self.cmdq .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset, vf_info))?; self.cmdq - .send_command_no_wait(bar, commands::SetRegistry::new())?; + .send_command_no_wait(bar, commands::SetRegistry::new(ctx.= vgpu_requested)?)?; =20 Self::boot_via_sec2( dev, @@ -406,7 +406,7 @@ pub(crate) fn boot( self.cmdq .send_command_no_wait(bar, commands::SetSystemInfo::new(pd= ev, chipset, vf_info))?; self.cmdq - .send_command_no_wait(bar, commands::SetRegistry::new())?; + .send_command_no_wait(bar, commands::SetRegistry::new(ctx.= vgpu_requested)?)?; } =20 // SEC2-based architectures need to run the GSP sequencer diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/= gsp/commands.rs index 0445d05990e7..c96580d0f433 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -75,38 +75,62 @@ struct RegistryEntry { } =20 /// The `SetRegistry` command. +/// +/// Registry entries are built dynamically at runtime based on the current +/// configuration (e.g. whether vGPU is enabled). pub(crate) struct SetRegistry { - entries: [RegistryEntry; Self::NUM_ENTRIES], + entries: KVec, } =20 impl SetRegistry { - // For now we hard-code the registry entries. Future work will allow o= thers to - // be added as module parameters. - const NUM_ENTRIES: usize =3D 3; - - /// Creates a new `SetRegistry` command, using a set of hardcoded entr= ies. - pub(crate) fn new() -> Self { - Self { - entries: [ - // RMSecBusResetEnable - enables PCI secondary bus reset - RegistryEntry { - key: "RMSecBusResetEnable", - value: 1, - }, - // RMForcePcieConfigSave - forces GSP-RM to preserve PCI c= onfiguration registers on - // any PCI reset. - RegistryEntry { - key: "RMForcePcieConfigSave", - value: 1, - }, - // RMDevidCheckIgnore - allows GSP-RM to boot even if the = PCI dev ID is not found - // in the internal product name database. + /// Creates a new `SetRegistry` command. + /// + /// The base set of registry entries is always included. Additional en= tries + /// are appended dynamically based on runtime conditions (e.g. vGPU). + pub(crate) fn new(vgpu_requested: bool) -> Result { + let mut entries =3D KVec::new(); + + // RMSecBusResetEnable - enables PCI secondary bus reset + entries.push( + RegistryEntry { + key: "RMSecBusResetEnable", + value: 1, + }, + GFP_KERNEL, + )?; + + // RMForcePcieConfigSave - forces GSP-RM to preserve PCI configura= tion registers on + // any PCI reset. + entries.push( + RegistryEntry { + key: "RMForcePcieConfigSave", + value: 1, + }, + GFP_KERNEL, + )?; + + // RMDevidCheckIgnore - allows GSP-RM to boot even if the PCI dev = ID is not found + // in the internal product name database. + entries.push( + RegistryEntry { + key: "RMDevidCheckIgnore", + value: 1, + }, + GFP_KERNEL, + )?; + + // RMSetSriovMode - required when vGPU is enabled. + if vgpu_requested { + entries.push( RegistryEntry { - key: "RMDevidCheckIgnore", + key: "RMSetSriovMode", value: 1, }, - ], + GFP_KERNEL, + )?; } + + Ok(Self { entries }) } } =20 @@ -117,28 +141,31 @@ impl CommandToGsp for SetRegistry { type InitError =3D Infallible; =20 fn init(&self) -> impl Init { - PackedRegistryTable::init(Self::NUM_ENTRIES as u32, self.variable_= payload_len() as u32) + PackedRegistryTable::init( + self.entries.len() as u32, + self.variable_payload_len() as u32, + ) } =20 fn variable_payload_len(&self) -> usize { let mut key_size =3D 0; - for i in 0..Self::NUM_ENTRIES { - key_size +=3D self.entries[i].key.len() + 1; // +1 for NULL te= rminator + for entry in self.entries.iter() { + key_size +=3D entry.key.len() + 1; // +1 for NULL terminator } - Self::NUM_ENTRIES * size_of::() + key_size + self.entries.len() * size_of::() + key_size } =20 fn init_variable_payload( &self, dst: &mut SBufferIter>, ) -> Result { - let string_data_start_offset =3D - size_of::() + Self::NUM_ENTRIES * size_of= ::(); + let string_data_start_offset =3D size_of::() + + self.entries.len() * size_of::(); =20 // Array for string data. let mut string_data =3D KVec::new(); =20 - for entry in self.entries.iter().take(Self::NUM_ENTRIES) { + for entry in self.entries.iter() { dst.write_all( PackedRegistryEntry::new( (string_data_start_offset + string_data.len()) as u32, diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index 6d56b9b920fb..ca01ac3af9c6 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -664,9 +664,50 @@ pub(crate) enum MsgFunction { OsErrorLog =3D bindings::NV_VGPU_MSG_EVENT_OS_ERROR_LOG, PostEvent =3D bindings::NV_VGPU_MSG_EVENT_POST_EVENT, RcTriggered =3D bindings::NV_VGPU_MSG_EVENT_RC_TRIGGERED, + GpuacctPerfmonUtilSamples =3D bindings::NV_VGPU_MSG_EVENT_GPUACCT_PERF= MON_UTIL_SAMPLES, UcodeLibOsPrint =3D bindings::NV_VGPU_MSG_EVENT_UCODE_LIBOS_PRINT, } =20 +impl fmt::Display for MsgFunction { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + // Common function codes + MsgFunction::Nop =3D> write!(f, "NOP"), + MsgFunction::SetGuestSystemInfo =3D> write!(f, "SET_GUEST_SYST= EM_INFO"), + MsgFunction::AllocRoot =3D> write!(f, "ALLOC_ROOT"), + MsgFunction::AllocDevice =3D> write!(f, "ALLOC_DEVICE"), + MsgFunction::AllocMemory =3D> write!(f, "ALLOC_MEMORY"), + MsgFunction::AllocCtxDma =3D> write!(f, "ALLOC_CTX_DMA"), + MsgFunction::AllocChannelDma =3D> write!(f, "ALLOC_CHANNEL_DMA= "), + MsgFunction::MapMemory =3D> write!(f, "MAP_MEMORY"), + MsgFunction::BindCtxDma =3D> write!(f, "BIND_CTX_DMA"), + MsgFunction::AllocObject =3D> write!(f, "ALLOC_OBJECT"), + MsgFunction::Free =3D> write!(f, "FREE"), + MsgFunction::Log =3D> write!(f, "LOG"), + MsgFunction::GetGspStaticInfo =3D> write!(f, "GET_GSP_STATIC_I= NFO"), + MsgFunction::SetRegistry =3D> write!(f, "SET_REGISTRY"), + MsgFunction::GspSetSystemInfo =3D> write!(f, "GSP_SET_SYSTEM_I= NFO"), + MsgFunction::GspInitPostObjGpu =3D> write!(f, "GSP_INIT_POST_O= BJGPU"), + MsgFunction::GspRmControl =3D> write!(f, "GSP_RM_CONTROL"), + MsgFunction::GetStaticInfo =3D> write!(f, "GET_STATIC_INFO"), + + // Event codes + MsgFunction::GpuacctPerfmonUtilSamples =3D> write!(f, "GPUACCT= _PERFMON_UTIL_SAMPLES"), + MsgFunction::GspInitDone =3D> write!(f, "INIT_DONE"), + MsgFunction::GspRunCpuSequencer =3D> write!(f, "RUN_CPU_SEQUEN= CER"), + MsgFunction::PostEvent =3D> write!(f, "POST_EVENT"), + MsgFunction::RcTriggered =3D> write!(f, "RC_TRIGGERED"), + MsgFunction::MmuFaultQueued =3D> write!(f, "MMU_FAULT_QUEUED"), + MsgFunction::OsErrorLog =3D> write!(f, "OS_ERROR_LOG"), + MsgFunction::GspPostNoCat =3D> write!(f, "NOCAT"), + MsgFunction::GspLockdownNotice =3D> write!(f, "LOCKDOWN_NOTICE= "), + MsgFunction::ContinuationRecord =3D> write!(f, "CONTINUATION_R= ECORD"), + MsgFunction::UcodeLibOsPrint =3D> write!(f, "LIBOS_PRINT"), + } + } +} + + impl TryFrom for MsgFunction { type Error =3D kernel::error::Error; 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charset="utf-8" To support the maximum vGPUs on devices that support vGPU, a larger WPR2 heap size is required. On Ada with vGPU supported, the size should be set to at least 581MB. When vGPU support is enabled: - Reserve a larger WPR2 heap size of 581MB. - Set vf_partition_count to MAX_PARTITIONS_WITH_GFID_32VM (32) to support the maximum number of virtual functions in the WPR2 meta, or MAX_PARTITIONS_WITH_GFID (48) when total VFs exceeds 32. When vGPU support is not enabled, the original heap size calculation and partition count of 0 are preserved. Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/fb.rs | 21 +++++++++++++++---- drivers/gpu/nova-core/gpu.rs | 13 +++++++++++- drivers/gpu/nova-core/gsp.rs | 7 ++++++- drivers/gpu/nova-core/gsp/boot.rs | 2 +- drivers/gpu/nova-core/gsp/fw.rs | 6 ++++++ .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 4 ++++ drivers/gpu/nova-core/vgpu.rs | 2 +- 7 files changed, 47 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 1a84a15581a4..2228b6b08699 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -181,7 +181,15 @@ pub(crate) struct FbLayout { =20 impl FbLayout { /// Computes the FB layout for `chipset` required to run the `gsp_fw` = GSP firmware. - pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw: &GspFirmware) = -> Result { + /// + /// When `vf_partition_count` is non-zero, a larger WPR2 heap is reser= ved to support + /// vGPU virtual functions: 1370 MiB for 48 partitions, 581 MiB for 32= or fewer. + pub(crate) fn new( + chipset: Chipset, + bar: &Bar0, + gsp_fw: &GspFirmware, + vf_partition_count: u8, + ) -> Result { let hal =3D hal::fb_hal(chipset); =20 let fb =3D { @@ -243,8 +251,13 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw= : &GspFirmware) -> Result< =20 let wpr2_heap =3D { const WPR2_HEAP_DOWN_ALIGN: Alignment =3D Alignment::new::(); - let wpr2_heap_size =3D - gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chip= set, fb.end)?; + let wpr2_heap_size =3D if vf_partition_count =3D=3D 0 { + gsp::LibosParams::from_chipset(chipset).wpr_heap_size(chip= set, fb.end)? + } else if vf_partition_count > gsp::MAX_PARTITIONS_WITH_GFID_3= 2VM { + gsp::GSP_FW_HEAP_SIZE_VGPU_48VMS + } else { + gsp::GSP_FW_HEAP_SIZE_VGPU_DEFAULT + }; let wpr2_heap_addr =3D (elf.start - wpr2_heap_size).align_down= (WPR2_HEAP_DOWN_ALIGN); =20 FbRange(wpr2_heap_addr..(elf.start).align_down(WPR2_HEAP_DOWN_= ALIGN)) @@ -272,7 +285,7 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gsp_fw:= &GspFirmware) -> Result< wpr2_heap, wpr2, heap, - vf_partition_count: 0, + vf_partition_count, }) } } diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index e1c16e1b9ec4..e254ddca0fa4 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -25,7 +25,9 @@ gfw, gsp::{ Gsp, - GspBootContext, // + GspBootContext, + MAX_PARTITIONS_WITH_GFID, + MAX_PARTITIONS_WITH_GFID_32VM, // }, regs, vgpu::Vgpu, // @@ -389,6 +391,15 @@ pub(crate) fn new<'a>( sec2_falcon, fsp_falcon: None, vgpu_requested: vgpu.vgpu_requested, + vf_partition_count: if vgpu.vgpu_requested { + if vgpu.total_vfs > u16::from(MAX_PARTITIONS_W= ITH_GFID_32VM) { + MAX_PARTITIONS_WITH_GFID + } else { + MAX_PARTITIONS_WITH_GFID_32VM + } + } else { + 0 + }, }; gsp.boot(&mut ctx)?; vgpu.vgpu_enabled =3D ctx.vgpu_requested; diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs index 9435c7430dfe..528f37e581c7 100644 --- a/drivers/gpu/nova-core/gsp.rs +++ b/drivers/gpu/nova-core/gsp.rs @@ -26,8 +26,12 @@ mod sequencer; =20 pub(crate) use fw::{ + GSP_FW_HEAP_SIZE_VGPU_48VMS, + GSP_FW_HEAP_SIZE_VGPU_DEFAULT, GspFwWprMeta, - LibosParams, // + LibosParams, + MAX_PARTITIONS_WITH_GFID, + MAX_PARTITIONS_WITH_GFID_32VM, // }; =20 use crate::{ @@ -62,6 +66,7 @@ pub(crate) struct GspBootContext<'a> { pub(crate) sec2_falcon: &'a Falcon, pub(crate) fsp_falcon: Option>, pub(crate) vgpu_requested: bool, + pub(crate) vf_partition_count: u8, } =20 impl GspBootContext<'_> { diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index ed8729041d46..86b7a7aa8f5a 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -346,7 +346,7 @@ pub(crate) fn boot( let dev =3D ctx.dev(); let gsp_fw =3D KBox::pin_init(GspFirmware::new(dev, chipset, FIRMW= ARE_VERSION), GFP_KERNEL)?; =20 - let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw)?; + let fb_layout =3D FbLayout::new(chipset, bar, &gsp_fw, ctx.vf_part= ition_count)?; dev_dbg!(dev, "{:#x?}\n", fb_layout); =20 let wpr_meta =3D Coherent::::zeroed(dev, GFP_KERNEL)= ?; diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index ca01ac3af9c6..b46ab6b921e3 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -454,6 +454,12 @@ enum GspFwHeapParams {} /// Minimum required alignment for the GSP heap. const GSP_HEAP_ALIGNMENT: Alignment =3D Alignment::new::<{ 1 << 20 }>(); =20 +// vGPU constants from the bindings, re-exported for use by fb.rs and gpu.= rs. +pub(crate) const GSP_FW_HEAP_SIZE_VGPU_DEFAULT: u64 =3D bindings::GSP_FW_H= EAP_SIZE_VGPU_DEFAULT as u64; +pub(crate) const GSP_FW_HEAP_SIZE_VGPU_48VMS: u64 =3D bindings::GSP_FW_HEA= P_SIZE_VGPU_48VMS as u64; +pub(crate) const MAX_PARTITIONS_WITH_GFID: u8 =3D bindings::MAX_PARTITIONS= _WITH_GFID; +pub(crate) const MAX_PARTITIONS_WITH_GFID_32VM: u8 =3D bindings::MAX_PARTI= TIONS_WITH_GFID_32VM; + // These constants override the generated bindings for architecture-specif= ic heap sizing. // See Open RM: kgspCalculateGspFwHeapSize and related functions. // diff --git a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs b/drivers/gp= u/nova-core/gsp/fw/r570_144/bindings.rs index 354ee2cfa295..1273152266ad 100644 --- a/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs +++ b/drivers/gpu/nova-core/gsp/fw/r570_144/bindings.rs @@ -40,6 +40,10 @@ fn fmt(&self, fmt: &mut ::core::fmt::Formatter<'_>) -> := :core::fmt::Result { pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB: u32 =3D 256; pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB: u32 =3D 88; pub const GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB: u32 =3D 280; +pub const GSP_FW_HEAP_SIZE_VGPU_DEFAULT: u32 =3D 581 << 20; +pub const GSP_FW_HEAP_SIZE_VGPU_48VMS: u32 =3D 1370 << 20; +pub const MAX_PARTITIONS_WITH_GFID: u8 =3D 48; +pub const MAX_PARTITIONS_WITH_GFID_32VM: u8 =3D 32; pub const GSP_FW_WPR_META_REVISION: u32 =3D 1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cNzyz0mzf/geGPs1lxybHfH5TggKDDOpkiAnLHYPoQZHpHpLBg7vY6GV9WSgdgZtcANasQzLQbBR6Nl7aNQ4p3QwFebZ/szDUm7s1xLrYdCSCre3nK/R6b1QgH0fuEw3IMc9JgHdwwtcJb1kIekGAmlVvW3cMCQRZqk3xizZ7ii376xuKUSBYJmrvYYpxr59Y66+Xc+gnKHfFeKXpLodBmLVb/uQHnR3tTOR3rL2XR6PgKBKgc4e0XzXulTprRvUTMrjFT0uFYZ+1r96uQfJCyG8mpZRt5XkEPtLKWdL3jr1bOMOI/lzqARPHFNJ3D8wyp7/weGgjhIddwezMNfLjcwanggbJB750XhWUWRUkcB9Y153K2LePhTU/tB+sUihMxi0rz94FjS4AP1t8u7FQsTeaPVBZnJZG5u/XQ4UHHHeWB/Kz5l23px8N6q1hA+k X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2026 16:55:42.1963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00364ea4-9949-4385-10e2-08de81215cc7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000013.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4406 To support the maximum vGPUs on the device that support vGPU, a larger WPR2 heap size is required. By setting the WPR2 heap size larger than 256MB the scrubber ucode image is required to scrub the FB memory before any other ucode image is executed. If not, the GSP firmware hangs when booting. When the WPR2 heap exceeds 256MB, execute the scrubber ucode image to scrub the FB memory before executing any other ucode images. Cc: Dirk Behme Cc: Joel Fernandes Cc: Alexandre Courbot Signed-off-by: Zhi Wang --- drivers/gpu/nova-core/firmware.rs | 3 +- drivers/gpu/nova-core/firmware/booter.rs | 2 + drivers/gpu/nova-core/gsp/boot.rs | 53 ++++++++++++++++++++++++ drivers/gpu/nova-core/gsp/fw.rs | 2 +- drivers/gpu/nova-core/regs.rs | 12 ++++++ 5 files changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firm= ware.rs index ab5889fa6a56..d13615864198 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -437,7 +437,8 @@ const fn make_entry_chipset(self, chipset: gpu::Chipset= ) -> Self { .make_entry_file(name, "booter_load") .make_entry_file(name, "booter_unload") .make_entry_file(name, "bootloader") - .make_entry_file(name, "gsp"); + .make_entry_file(name, "gsp") + .make_entry_file(name, "scrubber"); =20 if chipset.needs_fwsec_bootloader() { this.make_entry_file(name, "gen_bootloader") diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-co= re/firmware/booter.rs index 04a887bea888..8642957923a2 100644 --- a/drivers/gpu/nova-core/firmware/booter.rs +++ b/drivers/gpu/nova-core/firmware/booter.rs @@ -284,6 +284,7 @@ fn new_booter(data: &[u8]) -> Result { =20 #[derive(Copy, Clone, Debug, PartialEq)] pub(crate) enum BooterKind { + Scrubber, Loader, #[expect(unused)] Unloader, @@ -301,6 +302,7 @@ pub(crate) fn new( bar: &Bar0, ) -> Result { let fw_name =3D match kind { + BooterKind::Scrubber =3D> "scrubber", BooterKind::Loader =3D> "booter_load", BooterKind::Unloader =3D> "booter_unload", }; diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/= boot.rs index 86b7a7aa8f5a..8f6e2536db1c 100644 --- a/drivers/gpu/nova-core/gsp/boot.rs +++ b/drivers/gpu/nova-core/gsp/boot.rs @@ -6,6 +6,7 @@ io::poll::read_poll_timeout, io_write, prelude::*, + sizes::SZ_256M_U64, time::Delta, // }; =20 @@ -188,6 +189,49 @@ fn run_fwsec_frts( } } =20 + /// Load and execute the scrubber ucode via SEC2 to scrub FB memory. + /// + /// This is required when the WPR2 heap exceeds 256MB (which happens w= hen + /// vGPU is enabled). Without scrubbing, GSP firmware will hang during= boot. + fn run_scrubber(ctx: &super::GspBootContext<'_>) -> Result { + let dev =3D ctx.dev(); + let bar =3D ctx.bar; + + let scrubber =3D BooterFirmware::new( + dev, + BooterKind::Scrubber, + ctx.chipset, + FIRMWARE_VERSION, + ctx.sec2_falcon, + bar, + )?; + + ctx.sec2_falcon.reset(bar)?; + ctx.sec2_falcon.load(dev, bar, &scrubber)?; + + let (mbox0, mbox1) =3D ctx.sec2_falcon.boot(bar, None, None)?; + dev_dbg!( + dev, + "Scrubber SEC2 MBOX0: {:#x}, MBOX1: {:#x}\n", + mbox0, + mbox1 + ); + + // Poll for scrubber completion via BSI_SECURE_SCRATCH_15. + read_poll_timeout( + || Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_15::read(bar)), + |val| val.scrubber_completed(), + Delta::from_millis(10), + Delta::from_secs(2), + ) + .inspect_err(|_| { + dev_err!(dev, "Scrubber did not complete in time\n"); + })?; + + dev_dbg!(dev, "Scrubber completed successfully\n"); + Ok(()) + } + fn run_booter( dev: &device::Device, bar: &Bar0, @@ -221,11 +265,19 @@ fn boot_via_sec2( fb_layout: &FbLayout, libos: &Coherent<[LibosMemoryRegionInitArgument]>, wpr_meta: &Coherent, + ctx: &super::GspBootContext<'_>, ) -> Result { // Run FWSEC-FRTS to set up the WPR2 region let bios =3D Vbios::new(dev, bar)?; Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, fb_layo= ut)?; =20 + // When the WPR2 heap exceeds 256MB (e.g. when vGPU is enabled), t= he + // scrubber ucode must scrub FB memory before any other ucode imag= es + // execute =E2=80=94 without this, GSP firmware hangs during boot. + if fb_layout.wpr2_heap.len() > SZ_256M_U64 { + Self::run_scrubber(ctx)?; + } + // Reset and boot GSP before SEC2 gsp_falcon.reset(bar)?; let libos_handle =3D libos.dma_handle(); @@ -375,6 +427,7 @@ pub(crate) fn boot( &fb_layout, &self.libos, &wpr_meta, + ctx, )?; } else { Self::boot_via_fsp( diff --git a/drivers/gpu/nova-core/gsp/fw.rs b/drivers/gpu/nova-core/gsp/fw= .rs index b46ab6b921e3..30d82501faba 100644 --- a/drivers/gpu/nova-core/gsp/fw.rs +++ b/drivers/gpu/nova-core/gsp/fw.rs @@ -7,7 +7,7 @@ // Alias to avoid repeating the version number with every use. use r570_144 as bindings; =20 -use core::ops::Range; +use core::{fmt, ops::Range}; =20 use kernel::{ device, diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 8d424dd23a5a..5692114c710c 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -216,6 +216,18 @@ pub(crate) fn higher_bound(self) -> u64 { 26:26 boot_stage_3_handoff as bool; }); =20 +// BSI secure scratch 15: scrubber handoff status. +register!(NV_PGC6_BSI_SECURE_SCRATCH_15 @ 0x001180fc { + 31:29 scrubber_handoff as u8; +}); + +impl NV_PGC6_BSI_SECURE_SCRATCH_15 { + /// Returns `true` if scrubber has completed. + pub(crate) fn scrubber_completed(self) -> bool { + self.scrubber_handoff() >=3D 0x3 + } +} + // Privilege level mask register. It dictates whether the host CPU has pri= vilege to access the // `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW= _BOOT). register!(NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK @ 0x00118128, --=20 2.51.0