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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aece84d57asm18120745ad.85.2026.03.13.03.35.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 03:35:11 -0700 (PDT) From: Sibi Sankar To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: sudeep.holla@kernel.org, angelogioacchino.delregno@collabora.com, viresh.kumar@linaro.org, neil.armstrong@linaro.org, festevam@gmail.com, Frank.Li@nxp.com, danila@jiaxyga.com, lpieralisi@kernel.org, dmitry.baryshkov@oss.qualcomm.com, tengfei.fan@oss.qualcomm.com, jingyi.wang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH V2 2/2] arm64: dts: qcom: glymur: Fix deprecated cpu compatibles Date: Fri, 13 Mar 2026 16:04:39 +0530 Message-Id: <20260313103439.1255247-3-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260313103439.1255247-1-sibi.sankar@oss.qualcomm.com> References: <20260313103439.1255247-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA4MiBTYWx0ZWRfX2g1VKlWMrcNw Y0Ivp5EAAN62L0UfubOyxXbqckOg6AUAcoM3Hhn7EfXlvkIC3dmiuK7+IyDcDlSyNZ2oYNdlpMQ T6ba7olsAFO474+qR0TePSvHOpYu+w6KBGsKyY375Pc4QUMhZQ75TnNM0OjV/Cn6iHGRJ6ulo/3 MZuCBSk+koZBPIgPNnWjf5tsWVDfevT3DCUzRkmfEd4wdauNK30NrFZKAScgEt7vPqqc+5WqqCD t0+APf78so0ZCJRlfORtBBZspt474OWvYzPQgsVqBsX0h9n3soeOjlXQFyk+ZXu/tuWjguPTDc2 /4yGhFazGjS3hnnXj3wa4G0gdJofDnrkbOLoti3MT6d7T4oSogigQGWqBaKAMe7glNUZcHAu0Lf S+RmEYKeG2m6mQnmRtNTaN05CpnEeNkdvHBsa1mDCWHtwHvdv81NVUr+32GWCBWm7ZoOoFtMKQ1 v8jXVGsOUY7ZFmiB50w== X-Proofpoint-GUID: K9GeGsRrC6ZHMVFp_JY6q2KHy4EZ-1HW X-Proofpoint-ORIG-GUID: K9GeGsRrC6ZHMVFp_JY6q2KHy4EZ-1HW X-Authority-Analysis: v=2.4 cv=H+vWAuYi c=1 sm=1 tr=0 ts=69b3e861 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=ISJSzXulsw8YtW9LTRMA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_02,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130082 Content-Type: text/plain; charset="utf-8" The generic Qualcomm Oryon CPU compatible used by the Glymur SoC is deprecated and incorrect since it uses a single compatible to describe two different core variants. It is now replaced with two different core-specific compatibles based on MIDR part and variant number. CPUS 0-5: MIDR_EL1[PART_NUM] - 0x2 MIDR_EL1[VARIANT] - 0x2 CPUS 6-17: MIDR_EL1[PART_NUM] - 0x2 MIDR_EL1[VARIANT] - 0x1 Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Sibi Sankar Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/glymur.dtsi | 36 ++++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..5de4b2801321 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -33,7 +33,7 @@ cpus { =20 cpu0: cpu@0 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-2"; reg =3D <0x0 0x0>; enable-method =3D "psci"; power-domains =3D <&cpu_pd0>, <&scmi_perf 0>; @@ -49,7 +49,7 @@ l2_0: l2-cache { =20 cpu1: cpu@100 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-2"; reg =3D <0x0 0x100>; enable-method =3D "psci"; power-domains =3D <&cpu_pd1>, <&scmi_perf 0>; @@ -59,7 +59,7 @@ cpu1: cpu@100 { =20 cpu2: cpu@200 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-2"; reg =3D <0x0 0x200>; enable-method =3D "psci"; power-domains =3D <&cpu_pd2>, <&scmi_perf 0>; @@ -69,7 +69,7 @@ cpu2: cpu@200 { =20 cpu3: cpu@300 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-2"; reg =3D <0x0 0x300>; enable-method =3D "psci"; power-domains =3D <&cpu_pd3>, <&scmi_perf 0>; @@ -79,7 +79,7 @@ cpu3: cpu@300 { =20 cpu4: cpu@400 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-2"; reg =3D <0x0 0x400>; enable-method =3D "psci"; power-domains =3D <&cpu_pd4>, <&scmi_perf 0>; @@ -89,7 +89,7 @@ cpu4: cpu@400 { =20 cpu5: cpu@500 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-2"; reg =3D <0x0 0x500>; enable-method =3D "psci"; power-domains =3D <&cpu_pd5>, <&scmi_perf 0>; @@ -99,7 +99,7 @@ cpu5: cpu@500 { =20 cpu6: cpu@10000 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x10000>; enable-method =3D "psci"; power-domains =3D <&cpu_pd6>, <&scmi_perf 1>; @@ -115,7 +115,7 @@ l2_1: l2-cache { =20 cpu7: cpu@10100 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x10100>; enable-method =3D "psci"; power-domains =3D <&cpu_pd7>, <&scmi_perf 1>; @@ -125,7 +125,7 @@ cpu7: cpu@10100 { =20 cpu8: cpu@10200 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x10200>; enable-method =3D "psci"; power-domains =3D <&cpu_pd8>, <&scmi_perf 1>; @@ -135,7 +135,7 @@ cpu8: cpu@10200 { =20 cpu9: cpu@10300 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x10300>; enable-method =3D "psci"; power-domains =3D <&cpu_pd9>, <&scmi_perf 1>; @@ -145,7 +145,7 @@ cpu9: cpu@10300 { =20 cpu10: cpu@10400 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x10400>; enable-method =3D "psci"; power-domains =3D <&cpu_pd10>, <&scmi_perf 1>; @@ -155,7 +155,7 @@ cpu10: cpu@10400 { =20 cpu11: cpu@10500 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x10500>; enable-method =3D "psci"; power-domains =3D <&cpu_pd11>, <&scmi_perf 1>; @@ -165,7 +165,7 @@ cpu11: cpu@10500 { =20 cpu12: cpu@20000 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x20000>; enable-method =3D "psci"; power-domains =3D <&cpu_pd12>, <&scmi_perf 2>; @@ -181,7 +181,7 @@ l2_2: l2-cache { =20 cpu13: cpu@20100 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x20100>; enable-method =3D "psci"; power-domains =3D <&cpu_pd13>, <&scmi_perf 2>; @@ -191,7 +191,7 @@ cpu13: cpu@20100 { =20 cpu14: cpu@20200 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x20200>; enable-method =3D "psci"; power-domains =3D <&cpu_pd14>, <&scmi_perf 2>; @@ -201,7 +201,7 @@ cpu14: cpu@20200 { =20 cpu15: cpu@20300 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x20300>; enable-method =3D "psci"; power-domains =3D <&cpu_pd15>, <&scmi_perf 2>; @@ -211,7 +211,7 @@ cpu15: cpu@20300 { =20 cpu16: cpu@20400 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x20400>; enable-method =3D "psci"; power-domains =3D <&cpu_pd16>, <&scmi_perf 2>; @@ -221,7 +221,7 @@ cpu16: cpu@20400 { =20 cpu17: cpu@20500 { device_type =3D "cpu"; - compatible =3D "qcom,oryon"; + compatible =3D "qcom,oryon-2-1"; reg =3D <0x0 0x20500>; enable-method =3D "psci"; power-domains =3D <&cpu_pd17>, <&scmi_perf 2>; --=20 2.34.1