From nobody Tue Apr 7 11:18:25 2026 Received: from smtpout.sipearl.com (smtpout.sipearl.com [178.170.11.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 501432FE074 for ; Fri, 13 Mar 2026 10:16:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.170.11.57 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773397013; cv=none; b=NiBDj+ZGnOiuthh0aVzTeEHXiNqJgtfdydOJBrm7hgWDa9/Xp7/4pOO2f0D4b0P/4yKntiMFYUFf9HFT5KX9/Hb5rYpKuxOL0cred8ThJawUZxv/ZwGir4/DDBZgmwooWTzoEZsJsDVMzQ4odEB9Q5U/59aVuqCzh15cP+uDj7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773397013; c=relaxed/simple; bh=K37UXr8VdFfLQpv0MEvwMYu+WgENhPaa0Up1Uoj85I4=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=WjfQgT1CU1gChc7yuirmHCr5KBN9SrTW9lWG2WkpP+Ii+IQsyDXLxrW+PKucn6ur+YwjEyDDcNCJrOysX4VeJMevNZk7biyXtOD951x5VNCxEMGWEC8lGh//A6gTPKoIORDmxLGEdHyBUUdTpa4+hK3r1ImiNPfyTlwDRGwSUIQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sipearl.com; spf=pass smtp.mailfrom=sipearl.com; dkim=pass (2048-bit key) header.d=sipearl.com header.i=@sipearl.com header.b=cqK6669w; arc=none smtp.client-ip=178.170.11.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sipearl.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sipearl.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sipearl.com header.i=@sipearl.com header.b="cqK6669w" Received: from smtpout.sipearl.com ([172.31.29.1]) by smtpin.sipearl.com with ESMTPS id 62DA1LqW014300-62DA1LqY014300 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 13 Mar 2026 11:01:21 +0100 Received: from dc2pvlnosz001.pub.int.sipearl.com (172.31.65.18) by dc2pvwexcz001.sipearl.corp (172.31.29.1) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.36; Fri, 13 Mar 2026 11:01:20 +0100 From: Andrea Tomassetti To: Peter Rosin CC: Andrea Tomassetti , Srinivas Kandagatla , Johan Hovold , Krzysztof Kozlowski , Subject: [PATCH] mux: gpio-mux: add support for 4:1 2-channels mux Date: Fri, 13 Mar 2026 11:00:13 +0100 Message-ID: <20260313100042.2937983-1-andrea.tomassetti@sipearl.com> X-Mailer: git-send-email 2.51.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dc2pvwexcz002.sipearl.corp (172.31.29.2) To dc2pvwexcz001.sipearl.corp (172.31.29.1) X-FEAS-BEC-Info: WlpIGw0aAQkEARIJHAEHBlJSCRoLAAEeDUhZUEhYSFhIWUhZXkguLT4lWFo8JVpcWFhZW1xcSFpRSAkGDBoNCUYcBwUJGxsNHBwBKBsBGA0JGgRGCwcFSFlIWV1IGA0MCSgJEA0GHAEJRhsNSFhIWkhZWUhZX1pGW1lGWlFGWUhQSFhIWEhbSFhIWEhYSFpbSAIHAAkGQwQBBgkaBygDDRoGDQRGBxoPSFhIWlBIBAEGHRBFAw0aBg0EKB4PDRpGAw0aBg0ERgcaD0hYSFldSBgNDAkoCRANBhwBCUYbDUhY X-FEAS-Client-IP: 172.31.29.1 X-FE-Policy-ID: 2:2:2:SYSTEM DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; d=sipearl.com; s=sipearl2024; c=relaxed/relaxed; h=from:to:cc:subject:date:message-id:mime-version:content-type; bh=Bo20XJW94j3oeM9VKNJpCiXRiOk4qtx3BStw4WttyNk=; b=cqK6669wIxcDeJKJXod0YFV6aPKr9TS3qo4vNb+HEjpzbl3KXRCqJ+EZIx4Rq+2fAGXOREUK88BX xFR0Cu+r8Q9ZZpn92PxMB5hnA8avLn2rmJsEKt+eLjUwONMurvUQb2wIBkoxdrwHb1WpFY1lGc0g 1bN05S0k1dXn268+puh7qBndNtssFgcBi2RBrk9RsoAu5OunhQl5Sa0CI0zzrMClP8j8Ri8VJINz vCClmXPXBl0Ghl0jl/fKck356nTGlBPTPR9YDb1nw5PI81/HUDcJBRkOYkIRzso/rcND5FZp6T7U eiioYrXXly0++Ol8NsZ8lW8wCdLSHuVrj5c2+Q== Content-Type: text/plain; charset="utf-8" Some gpio multiplexers, like TMUX1209, offer differential 4:1 or dual 4:1 single-ended channels. Similarly to what already done by the adg792a driver, the gpio-mux driver has to take into account the #mux-control-cells property and allocate as many controllers as advised by it. So, in the DTS you can now define: tmux1209: mux-controller { compatible =3D "gpio-mux"; #mux-control-cells =3D <1>; mux-gpios =3D <&gpio_expander 01 GPIO_ACTIVE_HIGH>, <&gpio_expander 02 GPIO_ACTIVE_HIGH>; }; adcmux30: adcmux30 { compatible =3D "io-channel-mux"; io-channels =3D <&adc1 4>; io-channel-names =3D "parent"; #io-channel-cells =3D <1>; mux-controls =3D <&tmux1209 0>; channels =3D "S1A", "S2A", "S3A", "S4A"; }; adcmux31: adcmux31 { compatible =3D "io-channel-mux"; io-channels =3D <&adc1 5>; io-channel-names =3D "parent"; #io-channel-cells =3D <1>; mux-controls =3D <&tmux1209 1>; channels =3D "S1B", "S2B", "S3B", "S4B"; }; Signed-off-by: Andrea Tomassetti --- drivers/mux/gpio.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c index 4cc3202c58f3..01ce3f878b9e 100644 --- a/drivers/mux/gpio.c +++ b/drivers/mux/gpio.c @@ -52,12 +52,23 @@ static int mux_gpio_probe(struct platform_device *pdev) int pins; s32 idle_state; int ret; + u32 cells; + int i; =20 pins =3D gpiod_count(dev, "mux"); if (pins < 0) return pins; =20 - mux_chip =3D devm_mux_chip_alloc(dev, 1, sizeof(*mux_gpio)); + ret =3D device_property_read_u32(dev, "#mux-control-cells", &cells); + if (ret < 0) + cells =3D 0; + + if (cells >=3D 2) { + dev_err(dev, "invalid control-cells %u\n", cells); + return -EINVAL; + } + + mux_chip =3D devm_mux_chip_alloc(dev, cells + 1, sizeof(*mux_gpio)); if (IS_ERR(mux_chip)) return PTR_ERR(mux_chip); =20 @@ -69,7 +80,9 @@ static int mux_gpio_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(mux_gpio->gpios), "failed to get gpios\n"); WARN_ON(pins !=3D mux_gpio->gpios->ndescs); - mux_chip->mux->states =3D BIT(pins); + + for (i =3D 0; i < mux_chip->controllers; ++i) + mux_chip->mux[i].states =3D BIT(pins); =20 ret =3D device_property_read_u32(dev, "idle-state", (u32 *)&idle_state); if (ret >=3D 0 && idle_state !=3D MUX_IDLE_AS_IS) { base-commit: 80234b5ab240f52fa45d201e899e207b9265ef91 --=20 2.51.2