From nobody Tue Apr 7 10:40:44 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1A58374197; Fri, 13 Mar 2026 08:13:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773389632; cv=none; b=f3wfRwX9CcinsO+aGrajRlFTEFRhW1j+XtqTYVL20bL8ygOhcyTxWO4CdTAzOG8wIiFKOVEBYf0W04YCHy3jjpNl0zMI++4/a4SNJv8tTiI/htpOBLhWPP0edNRkut9Xp4mH7RQzwHSYEVqBk+wd+eJMjOWhhi8S8ErrQ3/CWqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773389632; c=relaxed/simple; bh=kdEVL1ZMjT/LjY6vd+LZywbVE5TZTzCBbVhptqRjGUI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ucCKJpqXlRTdqgrWcFeHuJwhz4hr5zTrAlZkACBkqB+TzyKAD7ozUcxm0XeqmhL+rNMcrH5vtvxZObK9xZZQcuQjveYJkXl3fOxPmwX1kgWy+PBa04rwLQdNM+dT0/66yWVzYJmOMtTcDj15QCuMX1wpmtEayiikMSwJbXl//rQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=FKp6fK+z; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="FKp6fK+z" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 62D8B14U0053079, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1773389461; bh=ZUIRwDRLqnHgtlC5DhqIs5z86/XmY8KuyoDsiTpfYU4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=FKp6fK+zdQ/Dw12153fvS+XAtYmZIkJoqif3WYLhSPcqLRgJdL22t5TB0bC8CeOk+ 6fGwpLL1c+EVAa7HE8gJs+ulEqmFNU4Ob1jUWZNBLPqZlC7kBUORSFlUJqJ5qeH9Py s5k9+aicQFv37YnsiGhkIMWwn/9jPDNMJM+C4O8P/d003brqkEdFBOcIIcuZ8xCtk8 DLcl+LwYQCJ+PlXSuV1Pxw8Q6jn+qbgVsaPNosxpxg5uD3HcPbNQCBjzsk6P6UFzpm XNgHQ08x9iPNrY3lZ5UCQp//Y5UZ678hkAm+g+4+FCxJKIVUj/44THqjcH5nh9WcCP K8FYoZJGURnfA== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 62D8B14U0053079 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Mar 2026 16:11:01 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Mar 2026 16:11:01 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Mar 2026 16:11:01 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 02/10] arm64: dts: realtek: Add clock support for RTD1625 Date: Fri, 13 Mar 2026 16:10:52 +0800 Message-ID: <20260313081100.596224-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260313081100.596224-1-eleanor.lin@realtek.com> References: <20260313081100.596224-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the clock controller nodes and osc27m fixed clock for the Realtek RTD1625 SoC. Signed-off-by: Yu-Chun Lin --- Changes in v4: - This is a new patch. --- arch/arm64/boot/dts/realtek/kent.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/re= altek/kent.dtsi index ae006ce24420..eaff586c1806 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -26,6 +26,15 @@ timer { ; }; =20 + clocks { + osc27m: osc { + compatible =3D "fixed-clock"; + clock-frequency =3D <27000000>; + clock-output-names =3D "osc27m"; + #clock-cells =3D <0>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -141,6 +150,20 @@ rbus: bus@98000000 { #address-cells =3D <1>; #size-cells =3D <1>; =20 + cc: clock-controller@0 { + compatible =3D "realtek,rtd1625-crt-clk"; + reg =3D <0x0 0x900>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + ic: clock-controller@7088 { + compatible =3D "realtek,rtd1625-iso-clk"; + reg =3D <0x7088 0x8>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + uart0: serial@7800 { compatible =3D "snps,dw-apb-uart"; reg =3D <0x7800 0x100>; @@ -150,6 +173,13 @@ uart0: serial@7800 { reg-shift =3D <2>; status =3D "disabled"; }; + + iso_s_cc: clock-controller@146310 { + compatible =3D "realtek,rtd1625-iso-s-clk"; + reg =3D <0x146310 0x8>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 gic: interrupt-controller@ff100000 { --=20 2.34.1