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smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=64.106.246.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mailsc.amlogic.com (10.8.11.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.35; Thu, 12 Mar 2026 23:59:48 -0700 From: Jian Hu To: Jerome Brunet , Neil Armstrong , Kevin Hilman , "Martin Blumenstingl" , Stephen Boyd , Michael Turquette , robh+dt , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Jian Hu , Ronald Claveau , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel , Ferass El Hafidi Subject: [PATCH v2 3/3] arm64: dts: amlogic: t7: Add clock controller nodes Date: Fri, 13 Mar 2026 15:00:22 +0800 Message-ID: <20260313070022.700437-4-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260313070022.700437-1-jian.hu@amlogic.com> References: <20260313070022.700437-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: mailsh.amlogic.com (10.18.11.5) To mailsc.amlogic.com (10.8.11.35) Content-Type: text/plain; charset="utf-8" Add the required clock controller nodes for Amlogic T7 SoC family: - SCMI clock controller - PLL clock controller - Peripheral clock controller Signed-off-by: Jian Hu Signed-off-by: Ronald Claveau --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index 6510068bcff9..a610f642953d 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -6,6 +6,9 @@ #include #include #include "amlogic-t7-reset.h" +#include +#include +#include =20 / { interrupt-parent =3D <&gic>; @@ -201,6 +204,34 @@ pwrc: power-controller { }; }; =20 + sram@f7042000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xf7042000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0xf7042000 0x100>; + + scmi_shmem: sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; + + firmware { + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x820000c1>; + shmem =3D <&scmi_shmem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + soc { compatible =3D "simple-bus"; #address-cells =3D <2>; @@ -224,6 +255,42 @@ apb4: bus@fe000000 { #size-cells =3D <2>; ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; =20 + clkc_periphs: clock-controller@0 { + compatible =3D "amlogic,t7-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x1c8>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&hifi CLKID_HIFI_PLL>, + <&gp0 CLKID_GP0_PLL>, + <&gp1 CLKID_GP1_PLL>, + <&mpll CLKID_MPLL1>, + <&mpll CLKID_MPLL2>, + <&mpll CLKID_MPLL3>; + clock-names =3D "xtal", + "sys", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "hifi", + "gp0", + "gp1", + "mpll1", + "mpll2", + "mpll3"; + }; + reset: reset-controller@2000 { compatible =3D "amlogic,t7-reset"; reg =3D <0x0 0x2000 0x0 0x98>; @@ -269,6 +336,64 @@ uart_a: serial@78000 { status =3D "disabled"; }; =20 + gp0: clock-controller@8080 { + compatible =3D "amlogic,t7-gp0-pll"; + reg =3D <0x0 0x8080 0x0 0x20>; + clocks =3D <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + gp1: clock-controller@80c0 { + compatible =3D "amlogic,t7-gp1-pll"; + reg =3D <0x0 0x80c0 0x0 0x14>; + clocks =3D <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + hifi: clock-controller@8100 { + compatible =3D "amlogic,t7-hifi-pll"; + reg =3D <0x0 0x8100 0x0 0x20>; + clocks =3D <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + pcie: clock-controller@8140 { + compatible =3D "amlogic,t7-pcie-pll"; + reg =3D <0x0 0x8140 0x0 0x1c>; + clocks =3D <&scmi_clk CLKID_PCIE_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + mpll: clock-controller@8180 { + compatible =3D "amlogic,t7-mpll"; + reg =3D <0x0 0x8180 0x0 0x28>; + clocks =3D <&scmi_clk CLKID_FIXED_PLL_DCO>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + hdmi: clock-controller@81c0 { + compatible =3D "amlogic,t7-hdmi-pll"; + reg =3D <0x0 0x81c0 0x0 0x20>; + clocks =3D <&scmi_clk CLKID_HDMI_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + mclk: clock-controller@8300 { + compatible =3D "amlogic,t7-mclk-pll"; + reg =3D <0x0 0x8300 0x0 0x18>; + clocks =3D <&scmi_clk CLKID_MCLK_PLL_OSC>, + <&xtal>, + <&scmi_clk CLKID_FCLK_50M>; + clock-names =3D "in0", "in1", "in2"; + #clock-cells =3D <1>; + }; + sec_ao: ao-secure@10220 { compatible =3D "amlogic,t7-ao-secure", "amlogic,meson-gx-ao-secure", --=20 2.47.1