From nobody Tue Apr 7 12:55:14 2026 Received: from mail-sc.amlogic.com (unknown [64.106.246.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93E2634F24B; Fri, 13 Mar 2026 07:05:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=64.106.246.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773385544; cv=none; b=OAvs0UkLYAo6Togp/AfJ7oji0tTZCjzxpObO6VVeXzd86+of3Sg81ecYVX2C/ccL6RkA7zjoQnyG+NowkTTriLGJArG6KKUKcbdwlGrOH9hdL/VHGp+uZs0FBlXNHouy28uopfSQaCKF00qXkP7p1w6pd1oS06nR+2oEkM51Eic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773385544; c=relaxed/simple; bh=whlpUtXUBMICD/iMHzCH6i7RAA1F/626XsL2yoVhsrM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YdzPEO0X5krEOp4b9Ge25VS0vlcqsXjXUEbDeOj7xBIK+isC+QylsKWfpxd8yENFE9f9J8C6Pf+Xrd0D/N/lFDlSdWTQAoyNx7FxTxNANxuvk6f01abJLdXlUej8AW827j4XPZmsgbPftOCJ7gN0afsSUeb2cfowUCN1qctCtOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=64.106.246.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mailsc.amlogic.com (10.8.11.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.35; Thu, 12 Mar 2026 23:59:40 -0700 From: Jian Hu To: Jerome Brunet , Neil Armstrong , Kevin Hilman , "Martin Blumenstingl" , Stephen Boyd , Michael Turquette , robh+dt , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Jian Hu , Ronald Claveau , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel , Ferass El Hafidi Subject: [PATCH v2 1/3] dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string. Date: Fri, 13 Mar 2026 15:00:20 +0800 Message-ID: <20260313070022.700437-2-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260313070022.700437-1-jian.hu@amlogic.com> References: <20260313070022.700437-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: mailsh.amlogic.com (10.18.11.5) To mailsc.amlogic.com (10.8.11.35) Content-Type: text/plain; charset="utf-8" Fix redundant hyphen in "amlogic,t7-gp1--pll" string. Fixes: 5437753728ac ("dt-bindings: clock: add Amlogic T7 PLL clock controll= er") Signed-off-by: Jian Hu Signed-off-by: Ronald Claveau --- .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml index 49c61f65deff..b488d92b7984 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -72,7 +72,7 @@ allOf: contains: enum: - amlogic,t7-gp0-pll - - amlogic,t7-gp1--pll + - amlogic,t7-gp1-pll - amlogic,t7-hifi-pll - amlogic,t7-pcie-pll - amlogic,t7-mpll --=20 2.47.1 From nobody Tue Apr 7 12:55:14 2026 Received: from mail-sc.amlogic.com (unknown [64.106.246.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ACEA8F4A; Fri, 13 Mar 2026 07:00:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=64.106.246.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773385245; cv=none; b=GdAruy5NfUr3i1ijV8ENX66Q2gy8f/dy/dSMhDLy7/wuyP1YAdy5J8OULAQiX9tFWmnrOdvFT52gfp8JLghvLGtgWZlXozaUPJE4YdEp6NXDml3bHSmlCtTDmX2YA8qx+6CO7I8j8Co/0VmNtQCEFujyL22N2HXEAv+jvkuZlLI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773385245; c=relaxed/simple; bh=2wXmocWPnqfS4NGOOuLVo2/ubv2+wE8kYuk8LVnRAxE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZSC5VIAJ+bu9t8H6Te9D+5d6fo2eSpNvZTn1hC2uDJwvG4AxNAdj51s2iLJ+xYyD7bWU3QGMla2+BZZyV42i89dmT/tC+Y3VLvMKzpLhRsMY8EiBsyp4Gr2OzcpdFLbAxbpiqtYxhqSc+G+Sd/LuCGjadnE5+LPx3/hsUt8amCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=64.106.246.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mailsc.amlogic.com (10.8.11.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.35; Thu, 12 Mar 2026 23:59:44 -0700 From: Jian Hu To: Jerome Brunet , Neil Armstrong , Kevin Hilman , "Martin Blumenstingl" , Stephen Boyd , Michael Turquette , robh+dt , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel , Ronald Claveau , Ferass El Hafidi Subject: [PATCH v2 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock Date: Fri, 13 Mar 2026 15:00:21 +0800 Message-ID: <20260313070022.700437-3-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260313070022.700437-1-jian.hu@amlogic.com> References: <20260313070022.700437-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: mailsh.amlogic.com (10.18.11.5) To mailsc.amlogic.com (10.8.11.35) Content-Type: text/plain; charset="utf-8" The mpll3 clock is one parent clock of the sd_emmc and mipi_isp clocks on the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml bindings. Add the mpll3 clock source to the T7 peripherals clock controller input clock list, so that sd_emmc and mipi_isp can use it. For logical consistency, place the required mpll3 entry before the optional entry. This change breaks the ABI, but while the amlogic,t7-peripherals-clkc bindings have been merged upstream, the corresponding DT has not been merged yet. Thus, no real users or systems are affected. Fixes: b4156204e0f5 ("dt-bindings: clock: add Amlogic T7 peripherals clock = controller") Signed-off-by: Jian Hu Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/amlogic,t7-peripherals-clkc.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals= -clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals= -clkc.yaml index 55bb73707d58..a4b214a941ea 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.y= aml +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.y= aml @@ -24,7 +24,7 @@ properties: const: 1 =20 clocks: - minItems: 14 + minItems: 15 items: - description: input oscillator - description: input sys clk @@ -40,12 +40,13 @@ properties: - description: input gp1 pll - description: input mpll1 - description: input mpll2 + - description: input mpll3 - description: external input rmii oscillator (optional) - description: input video pll0 (optional) - description: external pad input for rtc (optional) =20 clock-names: - minItems: 14 + minItems: 15 items: - const: xtal - const: sys @@ -61,6 +62,7 @@ properties: - const: gp1 - const: mpll1 - const: mpll2 + - const: mpll3 - const: ext_rmii - const: vid_pll0 - const: ext_rtc @@ -97,7 +99,8 @@ examples: <&gp0 1>, <&gp1 1>, <&mpll 4>, - <&mpll 6>; + <&mpll 6>, + <&mpll 8>; clock-names =3D "xtal", "sys", "fix", @@ -111,6 +114,7 @@ examples: "gp0", "gp1", "mpll1", - "mpll2"; + "mpll2", + "mpll3"; }; }; --=20 2.47.1 From nobody Tue Apr 7 12:55:14 2026 Received: from mail-sc.amlogic.com (unknown [64.106.246.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88FAD8F4A; Fri, 13 Mar 2026 07:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=64.106.246.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773385248; cv=none; b=hy8C/t5wqH+uZwOr8Qk12+PCxmqQsW2hwKhOWT/6Xa9jGJmQduLu/I67FR4Ag/QHKmXS9Tnc5gdVed5dMjUCrwAd7kL5rRIpfE0TSaE6KwgmsMgPx4HClloZiUAcOXFURqHrwewiZcs6MoPFTRPwFvZYScmemYUTU8UmqhSSKrU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773385248; c=relaxed/simple; bh=FHdSJ8mw5PpIcjIOIw6V3xjRl777RW/ssB4i5Pbz0lc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uWWJ43Qt5Idduo+NSpI0WZHWa1KPllzd33yqOrmVKyWukQCBZctbJ+snhWIArazz/su4CkrItmOE/nXuLQ2IrtsdMnXwEhKS5EEZXY1ieCaJfG67u/5n0sj2AewX88exiW73ExAhacAIBqHAV4+GfjU9Ceb9+/bx8w8JLs7jSgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com; spf=pass smtp.mailfrom=amlogic.com; arc=none smtp.client-ip=64.106.246.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amlogic.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amlogic.com Received: from rd03-sz.software.amlogic (10.28.11.121) by mailsc.amlogic.com (10.8.11.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.35; Thu, 12 Mar 2026 23:59:48 -0700 From: Jian Hu To: Jerome Brunet , Neil Armstrong , Kevin Hilman , "Martin Blumenstingl" , Stephen Boyd , Michael Turquette , robh+dt , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Jian Hu , Ronald Claveau , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel , Ferass El Hafidi Subject: [PATCH v2 3/3] arm64: dts: amlogic: t7: Add clock controller nodes Date: Fri, 13 Mar 2026 15:00:22 +0800 Message-ID: <20260313070022.700437-4-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260313070022.700437-1-jian.hu@amlogic.com> References: <20260313070022.700437-1-jian.hu@amlogic.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: mailsh.amlogic.com (10.18.11.5) To mailsc.amlogic.com (10.8.11.35) Content-Type: text/plain; charset="utf-8" Add the required clock controller nodes for Amlogic T7 SoC family: - SCMI clock controller - PLL clock controller - Peripheral clock controller Signed-off-by: Jian Hu Signed-off-by: Ronald Claveau --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-t7.dtsi index 6510068bcff9..a610f642953d 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -6,6 +6,9 @@ #include #include #include "amlogic-t7-reset.h" +#include +#include +#include =20 / { interrupt-parent =3D <&gic>; @@ -201,6 +204,34 @@ pwrc: power-controller { }; }; =20 + sram@f7042000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0xf7042000 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0xf7042000 0x100>; + + scmi_shmem: sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x100>; + }; + }; + + firmware { + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x820000c1>; + shmem =3D <&scmi_shmem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + soc { compatible =3D "simple-bus"; #address-cells =3D <2>; @@ -224,6 +255,42 @@ apb4: bus@fe000000 { #size-cells =3D <2>; ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; =20 + clkc_periphs: clock-controller@0 { + compatible =3D "amlogic,t7-peripherals-clkc"; + reg =3D <0x0 0x0 0x0 0x1c8>; + #clock-cells =3D <1>; + clocks =3D <&xtal>, + <&scmi_clk CLKID_SYS_CLK>, + <&scmi_clk CLKID_FIXED_PLL>, + <&scmi_clk CLKID_FCLK_DIV2>, + <&scmi_clk CLKID_FCLK_DIV2P5>, + <&scmi_clk CLKID_FCLK_DIV3>, + <&scmi_clk CLKID_FCLK_DIV4>, + <&scmi_clk CLKID_FCLK_DIV5>, + <&scmi_clk CLKID_FCLK_DIV7>, + <&hifi CLKID_HIFI_PLL>, + <&gp0 CLKID_GP0_PLL>, + <&gp1 CLKID_GP1_PLL>, + <&mpll CLKID_MPLL1>, + <&mpll CLKID_MPLL2>, + <&mpll CLKID_MPLL3>; + clock-names =3D "xtal", + "sys", + "fix", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "hifi", + "gp0", + "gp1", + "mpll1", + "mpll2", + "mpll3"; + }; + reset: reset-controller@2000 { compatible =3D "amlogic,t7-reset"; reg =3D <0x0 0x2000 0x0 0x98>; @@ -269,6 +336,64 @@ uart_a: serial@78000 { status =3D "disabled"; }; =20 + gp0: clock-controller@8080 { + compatible =3D "amlogic,t7-gp0-pll"; + reg =3D <0x0 0x8080 0x0 0x20>; + clocks =3D <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + gp1: clock-controller@80c0 { + compatible =3D "amlogic,t7-gp1-pll"; + reg =3D <0x0 0x80c0 0x0 0x14>; + clocks =3D <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + hifi: clock-controller@8100 { + compatible =3D "amlogic,t7-hifi-pll"; + reg =3D <0x0 0x8100 0x0 0x20>; + clocks =3D <&scmi_clk CLKID_TOP_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + pcie: clock-controller@8140 { + compatible =3D "amlogic,t7-pcie-pll"; + reg =3D <0x0 0x8140 0x0 0x1c>; + clocks =3D <&scmi_clk CLKID_PCIE_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + mpll: clock-controller@8180 { + compatible =3D "amlogic,t7-mpll"; + reg =3D <0x0 0x8180 0x0 0x28>; + clocks =3D <&scmi_clk CLKID_FIXED_PLL_DCO>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + hdmi: clock-controller@81c0 { + compatible =3D "amlogic,t7-hdmi-pll"; + reg =3D <0x0 0x81c0 0x0 0x20>; + clocks =3D <&scmi_clk CLKID_HDMI_PLL_OSC>; + clock-names =3D "in0"; + #clock-cells =3D <1>; + }; + + mclk: clock-controller@8300 { + compatible =3D "amlogic,t7-mclk-pll"; + reg =3D <0x0 0x8300 0x0 0x18>; + clocks =3D <&scmi_clk CLKID_MCLK_PLL_OSC>, + <&xtal>, + <&scmi_clk CLKID_FCLK_50M>; + clock-names =3D "in0", "in1", "in2"; + #clock-cells =3D <1>; + }; + sec_ao: ao-secure@10220 { compatible =3D "amlogic,t7-ao-secure", "amlogic,meson-gx-ao-secure", --=20 2.47.1