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charset="utf-8" The MCDMA BD format differs between MM2S and S2MM directions, but the driver was using generic 'status' and 'sideband_status' fields for both. This could lead to incorrect residue calculations when the hardware updates direction-specific fields. Refactor the descriptor structure to use unions with direction-specific field names (mm2s_status/s2mm_status, etc.). This ensures the driver accesses the correct hardware fields based on channel direction and matches the hardware documentation. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine dr= iver support") Signed-off-by: Srinivas Neeli --- drivers/dma/xilinx/xilinx_dma.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index b53292e02448..4a83492f2435 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -275,8 +275,10 @@ struct xilinx_axidma_desc_hw { * @buf_addr_msb: MSB of Buffer address @0x0C * @rsvd: Reserved field @0x10 * @control: Control Information field @0x14 - * @status: Status field @0x18 - * @sideband_status: Status of sideband signals @0x1C + * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18 + * @s2mm_status: Status field for s2mm @0x18 + * @mm2s_status: Status field for mm2s @0x1C + * @s2mm_sideband_status: Sideband status for s2mm @0x1C * @app: APP Fields @0x20 - 0x30 */ struct xilinx_aximcdma_desc_hw { @@ -286,8 +288,14 @@ struct xilinx_aximcdma_desc_hw { u32 buf_addr_msb; u32 rsvd; u32 control; - u32 status; - u32 sideband_status; + union { + u32 mm2s_ctrl_sideband; + u32 s2mm_status; + }; + union { + u32 mm2s_status; + u32 s2mm_sideband_status; + }; u32 app[XILINX_DMA_NUM_APP_WORDS]; } __aligned(64); =20 @@ -1013,9 +1021,16 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_= chan *chan, struct xilinx_aximcdma_tx_segment, node); aximcdma_hw =3D &aximcdma_seg->hw; - residue +=3D - (aximcdma_hw->control - aximcdma_hw->status) & - chan->xdev->max_buffer_len; + if (chan->direction =3D=3D DMA_DEV_TO_MEM) + residue +=3D + (aximcdma_hw->control - + aximcdma_hw->s2mm_status) & + chan->xdev->max_buffer_len; + else + residue +=3D + (aximcdma_hw->control - + aximcdma_hw->mm2s_status) & + chan->xdev->max_buffer_len; } } =20 --=20 2.43.0 From nobody Thu Apr 2 19:00:03 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011064.outbound.protection.outlook.com [52.101.52.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 050DB34DB57; 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charset="utf-8" In AXIMCDMA scatter-gather mode, the hardware sets the completion bit when a transfer finishes. The driver now checks this bit to free descriptors from the active list and move them to the done list. This is required when interrupt delay timeout Dly_IrqEn is enabled, as interrupts may be triggered before the configured threshold is reached, even if not all descriptors have completed. Signed-off-by: Srinivas Neeli --- drivers/dma/xilinx/xilinx_dma.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 4a83492f2435..00200b4c2372 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1762,6 +1762,18 @@ static void xilinx_dma_complete_descriptor(struct xi= linx_dma_chan *chan) struct xilinx_axidma_tx_segment, node); if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) break; + } else if (chan->xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; + bool completed; + + seg =3D list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, + node); + completed =3D (chan->direction =3D=3D DMA_DEV_TO_MEM) ? + (seg->hw.s2mm_status & XILINX_DMA_BD_COMP_MASK) : + (seg->hw.mm2s_status & XILINX_DMA_BD_COMP_MASK); + if (!completed) + break; } if (chan->has_sg && chan->xdev->dma_config->dmatype !=3D XDMA_TYPE_VDMA) --=20 2.43.0 From nobody Thu Apr 2 19:00:03 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010059.outbound.protection.outlook.com [40.93.198.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 224613537C6; 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charset="utf-8" From: Suraj Gupta Extend probe logic to detect AXI Stream connections for MCDMA. When an AXI Stream interface is present, metadata operations are enabled for the MCDMA channel. The xilinx_dma_get_metadata_ptr() is enhanced to retrieve metadata directly from MCDMA descriptors. Add corresponding channel reference in struct xilinx_dma_tx_descriptor to retrieve associated channel. These changes ensure proper metadata handling and accurate transfer size reporting for MCDMA transfers. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli --- drivers/dma/xilinx/xilinx_dma.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 00200b4c2372..52203d44e7a4 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -222,6 +222,8 @@ #define XILINX_MCDMA_BD_EOP BIT(30) #define XILINX_MCDMA_BD_SOP BIT(31) =20 +struct xilinx_dma_chan; + /** * struct xilinx_vdma_desc_hw - Hardware Descriptor * @next_desc: Next Descriptor Pointer @0x00 @@ -371,6 +373,7 @@ struct xilinx_cdma_tx_segment { =20 /** * struct xilinx_dma_tx_descriptor - Per Transaction structure + * @chan: DMA channel for which this descriptor is allocated * @async_tx: Async transaction descriptor * @segments: TX segments list * @node: Node in the channel descriptors list @@ -379,6 +382,7 @@ struct xilinx_cdma_tx_segment { * @residue: Residue of the completed descriptor */ struct xilinx_dma_tx_descriptor { + struct xilinx_dma_chan *chan; struct dma_async_tx_descriptor async_tx; struct list_head segments; struct list_head node; @@ -653,12 +657,23 @@ static void *xilinx_dma_get_metadata_ptr(struct dma_a= sync_tx_descriptor *tx, size_t *payload_len, size_t *max_len) { struct xilinx_dma_tx_descriptor *desc =3D to_dma_tx_descriptor(tx); - struct xilinx_axidma_tx_segment *seg; + void *metadata_ptr; + + if (desc->chan->xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; =20 + seg =3D list_first_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, node); + metadata_ptr =3D seg->hw.app; + } else { + struct xilinx_axidma_tx_segment *seg; + + seg =3D list_first_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + metadata_ptr =3D seg->hw.app; + } *max_len =3D *payload_len =3D sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; - seg =3D list_first_entry(&desc->segments, - struct xilinx_axidma_tx_segment, node); - return seg->hw.app; + return metadata_ptr; } =20 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops =3D { @@ -848,6 +863,7 @@ xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *= chan) if (!desc) return NULL; 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charset="utf-8" Add an optional boolean DT property "xlnx,include-stscntrl-strm" to indicate that the AXI DMA IP is configured with the AXI4-Stream status and control interface. This enables the use of APP fields in DMA descriptors for metadata reporting. This property is distinct from "xlnx,axistream-connected" and serves a different purpose: - "xlnx,include-stscntrl-strm": Indicates whether APP fields are present in DMA descriptors. When enabled, the driver can access status/control metadata through these descriptor fields. - "xlnx,axistream-connected": Indicates whether a streaming IP (client) is connected to the DMA IP. These two configurations are independent of each other. For example, in TSN (Time-Sensitive Networking) designs, a streaming client may be connected to the DMA IP, but the status/control stream interface is not enabled. In such cases, "xlnx,axistream-connected" would be present while "xlnx,include-stscntrl-strm" would be absent. Adding this property allows the driver to correctly determine descriptor layout and access APP fields only when the hardware supports them. Signed-off-by: Suraj Gupta Signed-off-by: Srinivas Neeli Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml= b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml index 340ae9e91cb0..ad8afefe7ee3 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml @@ -105,6 +105,10 @@ properties: type: boolean description: Tells whether DMA is connected to AXI stream IP. =20 + xlnx,include-stscntrl-strm: + type: boolean + description: Tells hardware is configured with AXI4-stream status and = control interface. + patternProperties: "^dma-channel(-mm2s|-s2mm)?$": type: object --=20 2.43.0 From nobody Thu Apr 2 19:00:03 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010070.outbound.protection.outlook.com [52.101.201.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E1D433D4E5; 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charset="utf-8" From: Suraj Gupta The AXI4-stream status and control interface is optional in the AXI DMA / MCDMA IP design; when it is not present, app fields are not available in DMA descriptor. In such cases, the transferred byte count can be communicated to the client using the status field (bits 0-25) of AXI DMA / MCDMA descriptor. Add a xferred_bytes field to struct xilinx_dma_tx_descriptor to record the number of bytes transferred for each transaction. The value is calculated using the existing xilinx_dma_get_residue() function, which traverses all hardware descriptors associated with the async transaction descriptor, avoiding redundant traversal. The driver uses the xlnx,include-stscntrl-strm device tree property to determine if the status/control stream interface is present and selects the appropriate metadata source accordingly. Signed-off-by: Suraj Gupta --- drivers/dma/xilinx/xilinx_dma.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 52203d44e7a4..f5ef03a1297c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -380,6 +380,8 @@ struct xilinx_cdma_tx_segment { * @cyclic: Check for cyclic transfers. * @err: Whether the descriptor has an error. * @residue: Residue of the completed descriptor + * @xferred_bytes: Number of bytes transferred by this transaction + * descriptor. */ struct xilinx_dma_tx_descriptor { struct xilinx_dma_chan *chan; @@ -389,6 +391,7 @@ struct xilinx_dma_tx_descriptor { bool cyclic; bool err; u32 residue; + u32 xferred_bytes; }; =20 /** @@ -515,6 +518,7 @@ struct xilinx_dma_config { * @mm2s_chan_id: DMA mm2s channel identifier * @max_buffer_len: Max buffer length * @has_axistream_connected: AXI DMA connected to AXI Stream IP + * @has_stsctrl_stream: AXI4-stream status and control interface is enabled */ struct xilinx_dma_device { void __iomem *regs; @@ -534,6 +538,7 @@ struct xilinx_dma_device { u32 mm2s_chan_id; u32 max_buffer_len; bool has_axistream_connected; + bool has_stsctrl_stream; }; =20 /* Macros */ @@ -672,8 +677,12 @@ static void *xilinx_dma_get_metadata_ptr(struct dma_as= ync_tx_descriptor *tx, struct xilinx_axidma_tx_segment, node); metadata_ptr =3D seg->hw.app; } - *max_len =3D *payload_len =3D sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; - return metadata_ptr; + if (desc->chan->xdev->has_stsctrl_stream) { + *max_len =3D *payload_len =3D sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; + return metadata_ptr; + } + *max_len =3D *payload_len =3D sizeof(desc->xferred_bytes); + return (void *)&desc->xferred_bytes; } =20 static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops =3D { @@ -864,6 +873,7 @@ xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *= chan) return NULL; =20 desc->chan =3D chan; + desc->xferred_bytes =3D 0; INIT_LIST_HEAD(&desc->segments); =20 return desc; @@ -1014,6 +1024,7 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_c= han *chan, struct xilinx_aximcdma_desc_hw *aximcdma_hw; struct list_head *entry; u32 residue =3D 0; + u32 xferred =3D 0; =20 list_for_each(entry, &desc->segments) { if (chan->xdev->dma_config->dmatype =3D=3D XDMA_TYPE_CDMA) { @@ -1031,25 +1042,32 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma= _chan *chan, axidma_hw =3D &axidma_seg->hw; residue +=3D (axidma_hw->control - axidma_hw->status) & chan->xdev->max_buffer_len; + xferred +=3D axidma_hw->status & chan->xdev->max_buffer_len; } else { aximcdma_seg =3D list_entry(entry, struct xilinx_aximcdma_tx_segment, node); aximcdma_hw =3D &aximcdma_seg->hw; - if (chan->direction =3D=3D DMA_DEV_TO_MEM) + if (chan->direction =3D=3D DMA_DEV_TO_MEM) { residue +=3D (aximcdma_hw->control - aximcdma_hw->s2mm_status) & chan->xdev->max_buffer_len; - else + xferred +=3D aximcdma_hw->s2mm_status & + chan->xdev->max_buffer_len; + } else { residue +=3D (aximcdma_hw->control - aximcdma_hw->mm2s_status) & chan->xdev->max_buffer_len; + xferred +=3D aximcdma_hw->mm2s_status & + chan->xdev->max_buffer_len; + } } } =20 + desc->xferred_bytes =3D xferred; return residue; } =20 @@ -3284,6 +3302,8 @@ static int xilinx_dma_probe(struct platform_device *p= dev) xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIMCDMA) { xdev->has_axistream_connected =3D of_property_read_bool(node, "xlnx,axistream-connected"); + xdev->has_stsctrl_stream =3D + of_property_read_bool(node, "xlnx,include-stscntrl-strm"); } =20 if (xdev->dma_config->dmatype =3D=3D XDMA_TYPE_VDMA) { --=20 2.43.0