From nobody Fri Apr 3 03:18:55 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49FA22F39AB for ; Fri, 13 Mar 2026 10:24:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773397448; cv=none; b=kS9LqSIZdCD+l2vsen1xE8lYs4ILqs8PbyWqmS3Lc7zY9GEyCtt7jWe+PdubjfzuSY9bLg+wBa0CbY4dABgtJuXen+7EuL99u62vkNE10C6KrtkZgTg63pyvOm0SOPxk5gsEb+zRSQQDuhvPtM+zRMK/id5EbBb1EjM7eO51yH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773397448; c=relaxed/simple; bh=QhBtjbDloLdUGe4ameEFnwT0gkXTioWGK4diNOa+ibA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=Mihod9TJV2eH9QdJpqBGuh8Mm40FzT87UekNW8xr9hvyu8XU84AmCrKTzs7HM9kHrKkMakUcJRGjBFjSRX3Ie0nKcKluePmRPT2mBaHCB9JnA8erDBuuU9f8lVEus8gUqPaU9nZ8HY1mT6Im/Wtg9mGEFGEQqNXEq2bMCj8+Z6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nEgHuo5s; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=N941CIUd; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nEgHuo5s"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="N941CIUd" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62D7in6A2263477 for ; Fri, 13 Mar 2026 10:24:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=xdroUf42OnaRsZaNXVIwjI uoiVOsASCk4ZWCqNs2gp8=; b=nEgHuo5sHIlSGtourKRKx/NaKjQE0MTjlXa1ae JlsOEV2ZJ1aS72PzqWf504d/PBjC8yqUYg2RJ2yE6K7/6EeGztR6zH6ZX3vSUbe3 BVUt9ES9/gT8I4J6R95nnMcERZDKH5/qo+hWjFT7g4Hk3Edvc6Nw0wl0PT4IOrY3 idi26aY1Y0w4rq7ybs7miaupTsAzn/HdfT2KmK2ZoObRgv9ntU3raX9cqTeTv49F NC47V4wEs7TDZ5UoAYiwF4MWuFkGH0P0euZxOSunNsekQH29ealV5Sorsr2rc18q VlF6p+litw26pjqsy5rBa6choxenef97ZC6xoGxK+Fu8PZjA== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cvef4rjuc-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 13 Mar 2026 10:24:06 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-35a1a752191so1405085a91.2 for ; Fri, 13 Mar 2026 03:24:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773397446; x=1774002246; darn=vger.kernel.org; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=xdroUf42OnaRsZaNXVIwjIuoiVOsASCk4ZWCqNs2gp8=; b=N941CIUddwCpDHmYsOxBDq2uJukpwGzRUxFiXgE0uePcXkzXZqK9spgjC7p2R3qsFV Q+yMQlvB+TmhWuM60a2oYrZzCiO7CIrT3sCaRWZY1U1Ng2QH+/B6ClhkJ9Ug5asgllyY PkWRRT9a9Su3QjGPttzP6ZVogFEspPhm2oQFPxGWK8X8nfW2PybnwqlOojEsRLJZIVku +Q9Rn+dKiPwf+/Ysp6S4SGjsxiAiAGaxa/NKkj2mYm0v08snwvmb7yH/IC1TmYja3ZtX rPxMlZb/AQjxlSEm4zouVPlkZA0YrVGF6UkHHVR5/k5rzaBXKctyrZ4aTRwqA9UobgSj kY7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773397446; x=1774002246; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=xdroUf42OnaRsZaNXVIwjIuoiVOsASCk4ZWCqNs2gp8=; b=Z9MvCJPrpribJvYyH0HHhLey4SsO9Ve8cmec0cpKfILy/eNRHf6IIW1tNhmWECuJsN nP8Cr1FnKl93PzJKCCJpfukMEfeeYELGMVt5EwUAM6yUgfayU6yovRvrEppOyP/Z8ebe beP1LqlVFFl5NHOINteuhviFJ+AfYao1gQgrM8vWHV8LESmGuVhitMtrV1UD/CJvsIsD 9nll9uyRbPvrAF4tBCTOIndXtggNNwTMmQdnOo0jkI7ijakYytj5Q/O8fRPa5r3PkRl8 3nyxIOJ3uRJ6h7NH/HNeKW3nt1Q534CDrHZgpnx6peGsC3KoLpm4wCGrTZmCW2eAO3IR FCyg== X-Forwarded-Encrypted: i=1; AJvYcCVrEJvMgJ4EjQ67E40hEZNgblX/X+zmVYgcddoGBybGHBxG5aRAuwrfDXBGonTlF2yu8WKYalfYdrUdlrA=@vger.kernel.org X-Gm-Message-State: AOJu0YzcWG+hQNMV4rZsRrQ930XIN5jGViqDAvSkEjmVZjpH2I4Xs0Ss JKoabB/2liZIXoMAxcjIi9FbEs82g6jxQwVIY3l7nhHmPlUf2dralQU/Suu0dRw7bGd/Gf4+qCl gPqIhGHJk2MwDj7zHoHc2AmtiXsFx3xWLqyuQZu+y333spuA6Z/o80Wsxk9JHT4PTf/EW7Em84F 0= X-Gm-Gg: ATEYQzz9zr/tF9AFLCKfrmDp1ex1tUrk1NrkFX23nzZf8O5jsTURJ9EZJpW8otHsKqB R1IbsPq7RcELkNHB8ALtSnaSkyxcwqnxKO8SNvmVVakbF3pKr45byELfSRUK0WCCKJBu0avNH2K HIMIIdEEYr8l3kbQgXph8ndOOWWCzignjphoANLT6MonJoTkYsHdDECzEtwR4SoDc0Qv7SYbtbh eu6XI+gsp9mDlcWQul9VheeAmlfWS/ZhM3FLuEdm/LzVv1EkO6w7aw6kyCEt9P1s0vEGrNwXIth T+X/xHK84dpHWkwP8hHGP+ZPR4IEJpnxLEhhlfyvBrUzBJhrxKHYq22ZY7RmBswJFqBLIzf7QMt 2qsysR4MjYZuAVFcEISW1KwD+eVcUDpiOKWD/AG/vQouN3s/7DRqe X-Received: by 2002:a17:90b:4a46:b0:359:f0e1:f8c0 with SMTP id 98e67ed59e1d1-35a21e1ca44mr2497544a91.6.1773397445739; Fri, 13 Mar 2026 03:24:05 -0700 (PDT) X-Received: by 2002:a17:90b:4a46:b0:359:f0e1:f8c0 with SMTP id 98e67ed59e1d1-35a21e1ca44mr2497521a91.6.1773397445204; Fri, 13 Mar 2026 03:24:05 -0700 (PDT) Received: from hu-guptap-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35a02ffe078sm8437602a91.13.2026.03.13.03.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 03:24:04 -0700 (PDT) From: Prakash Gupta Date: Fri, 13 Mar 2026 15:53:53 +0530 Subject: [PATCH v2] iommu/arm-smmu: Use pm_runtime in fault handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-smmu-rpm-v2-1-8c2236b402b0@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIALnls2kC/0XMQQ6DIBCF4auYWRcDY1HbVe/RuFDASlLEMpW0M dy96KabSf7Jy7cBmWANwbXYIJhoyfo5B54KUFM/PwyzOjcgRymQt4ycW1lYHGsHXTd6uFRa9ZD nSzCj/RzUvcs9WXr78D3kKPbvjtRcYPNHomCCoRlxPKtWVlzePFH5Wvun8s6V+UCXUvoBXtg2u 6cAAAA= X-Change-ID: 20251208-smmu-rpm-8bd67db93dca To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Clark , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Akhil P Oommen , Pranjal Shrivastava , Pratyush Brahma , Prakash Gupta X-Mailer: b4 0.15-dev-47773 X-Proofpoint-ORIG-GUID: QSwUuMGPYWUamKcRVqlk8bWUtsTgo4of X-Proofpoint-GUID: QSwUuMGPYWUamKcRVqlk8bWUtsTgo4of X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA4MSBTYWx0ZWRfXzuMHO4Sr/eYm R4wWnlrKpzBZFpb8RiY4dsAdhTPrwNTV/vkl9i9EM7mbh7aRkZphSaNgSO+jcaxqYocjNS4Ju45 4K7qo0OtMmV8r4q/4ZY8l4gRAVpOEuCmAXwCYIPdpayqwviCTRL4U/x8NuYVgdP4/oJ6RqCBuqz sjNNqOUD/4lgcj07RFylY/Rq7pIXqk6SViQCPaELkuRU2jEUAJRt870V2JsBAm4inSu/2r3uZ0t HxwOGFnrC3F0SI6+3xb2BkoGc2A/FPZeQmLo0EMiIEbCT8D/7p7z3unrk0YUiqtvnm53AX+I1bA c8UjXGZBhjF4bPTMMofJFUJuawJv3vqXbAItFLLvU0ukT1Zdgwqg/iyyJ4oRPNiYb/H5hrvd7Pa jIF0PotwZMCQxSZVbJo5KyHtpG+/x5OswRTszyZ2Ji5eXuGX8h+irFdmwDYCra2tX8g6zbX+wGh mNWDnAoBDnqMnUEjukA== X-Authority-Analysis: v=2.4 cv=S9nUAYsP c=1 sm=1 tr=0 ts=69b3e5c6 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=FOn0AWhus2eDxXApaSoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_02,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130081 Commit d4a44f0750bb ("iommu/arm-smmu: Invoke pm_runtime across the driver") enabled pm_runtime for the arm-smmu device. On systems where the SMMU sits in a power domain, all register accesses must be done while the device is runtime active to avoid unclocked register reads and potential NoC errors. So far, this has not been an issue for most SMMU clients because stall-on-fault is enabled by default. While a translation fault is being handled, the SMMU stalls further translations for that context bank, so the fault handler would not race with a powered-down SMMU. Adreno SMMU now disables stall-on-fault in the presence of fault storms to avoid saturating SMMU resources and hanging the GMU. With stall-on-fault disabled, the SMMU can generate faults while its power domain may no longer be enabled, which makes unclocked accesses to fault-status registers in the SMMU fault handlers possible. Guard the context and global fault handlers with pm_runtime_get_if_active() and pm_runtime_put_autosuspend() so that all SMMU fault register accesses are done with the SMMU powered. In case pm_runtime is not active we can safely ignore the fault as for pm runtime resume the smmu device is reset and fault registers are cleared. Fixes: b13044092c1e ("drm/msm: Temporarily disable stall-on-fault after a p= age fault") Co-developed-by: Pratyush Brahma Signed-off-by: Pratyush Brahma Signed-off-by: Prakash Gupta --- Changes in v2: - Switched from arm_smmu_rpm_get()/arm_smmu_rpm_put() wrappers to pm_runtime_get_if_active()/pm_runtime_put_autosuspend() APIs - Added support for smmu->impl->global_fault callback in global fault handl= er - Remove threaded irq context fault restriction to allow modifying stall mode for adreno smmu - Link to v1: https://patch.msgid.link/20260127-smmu-rpm-v1-1-2ef2f4c85305@= oss.qualcomm.com --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 60 +++++++++++++++++++++++--------= ---- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-= smmu/arm-smmu.c index 5e690cf85ec9..f4c46491a03d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -462,10 +462,20 @@ static irqreturn_t arm_smmu_context_fault(int irq, vo= id *dev) int idx =3D smmu_domain->cfg.cbndx; int ret; =20 + if (!pm_runtime_get_if_active(smmu->dev)) + return IRQ_NONE; + + if (smmu->impl && smmu->impl->context_fault) { + ret =3D smmu->impl->context_fault(irq, dev); + goto out_power_off; + } + arm_smmu_read_context_fault_info(smmu, idx, &cfi); =20 - if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) - return IRQ_NONE; + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) { + ret =3D IRQ_NONE; + goto out_power_off; + } =20 ret =3D report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_REA= D); @@ -480,7 +490,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, voi= d *dev) ret =3D=3D -EAGAIN ? 0 : ARM_SMMU_RESUME_TERMINATE); } =20 - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + +out_power_off: + pm_runtime_put_autosuspend(smmu->dev); + + return ret; } =20 static irqreturn_t arm_smmu_global_fault(int irq, void *dev) @@ -489,14 +504,25 @@ static irqreturn_t arm_smmu_global_fault(int irq, voi= d *dev) struct arm_smmu_device *smmu =3D dev; static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); + int ret; + + if (!pm_runtime_get_if_active(smmu->dev)) + return IRQ_NONE; + + if (smmu->impl && smmu->impl->global_fault) { + ret =3D smmu->impl->global_fault(irq, dev); + goto out_power_off; + } =20 gfsr =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); gfsynr0 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); gfsynr1 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); gfsynr2 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); =20 - if (!gfsr) - return IRQ_NONE; + if (!gfsr) { + ret =3D IRQ_NONE; + goto out_power_off; + } =20 if (__ratelimit(&rs)) { if (IS_ENABLED(CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT) && @@ -513,7 +539,11 @@ static irqreturn_t arm_smmu_global_fault(int irq, void= *dev) } =20 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + +out_power_off: + pm_runtime_put_autosuspend(smmu->dev); + return ret; } =20 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, @@ -683,7 +713,6 @@ static int arm_smmu_init_domain_context(struct arm_smmu= _domain *smmu_domain, enum io_pgtable_fmt fmt; struct iommu_domain *domain =3D &smmu_domain->domain; struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; - irqreturn_t (*context_fault)(int irq, void *dev); =20 mutex_lock(&smmu_domain->init_mutex); if (smmu_domain->smmu) @@ -850,19 +879,14 @@ static int arm_smmu_init_domain_context(struct arm_sm= mu_domain *smmu_domain, */ irq =3D smmu->irqs[cfg->irptndx]; =20 - if (smmu->impl && smmu->impl->context_fault) - context_fault =3D smmu->impl->context_fault; - else - context_fault =3D arm_smmu_context_fault; - if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) ret =3D devm_request_threaded_irq(smmu->dev, irq, NULL, - context_fault, + arm_smmu_context_fault, IRQF_ONESHOT | IRQF_SHARED, "arm-smmu-context-fault", smmu_domain); else - ret =3D devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, + ret =3D devm_request_irq(smmu->dev, irq, arm_smmu_context_fault, IRQF_SH= ARED, "arm-smmu-context-fault", smmu_domain); =20 if (ret < 0) { @@ -2125,7 +2149,6 @@ static int arm_smmu_device_probe(struct platform_devi= ce *pdev) struct device *dev =3D &pdev->dev; int num_irqs, i, err; u32 global_irqs, pmu_irqs; - irqreturn_t (*global_fault)(int irq, void *dev); =20 smmu =3D devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); if (!smmu) { @@ -2205,18 +2228,13 @@ static int arm_smmu_device_probe(struct platform_de= vice *pdev) smmu->num_context_irqs =3D smmu->num_context_banks; } =20 - if (smmu->impl && smmu->impl->global_fault) - global_fault =3D smmu->impl->global_fault; - else - global_fault =3D arm_smmu_global_fault; - for (i =3D 0; i < global_irqs; i++) { int irq =3D platform_get_irq(pdev, i); =20 if (irq < 0) return irq; =20 - err =3D devm_request_irq(dev, irq, global_fault, IRQF_SHARED, + err =3D devm_request_irq(dev, irq, arm_smmu_global_fault, IRQF_SHARED, "arm-smmu global fault", smmu); if (err) return dev_err_probe(dev, err, --- base-commit: fcb70a56f4d81450114034b2c61f48ce7444a0e2 change-id: 20251208-smmu-rpm-8bd67db93dca Best regards, -- =20 Prakash Gupta