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Fri, 13 Mar 2026 06:20:45 -0700 (PDT) Received: from hu-vgarodia-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a0724407csm5775254b3a.8.2026.03.13.06.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 06:20:44 -0700 (PDT) From: Vikash Garodia Date: Fri, 13 Mar 2026 18:49:40 +0530 Subject: [PATCH v3 6/7] media: iris: add iris4 specific H265 line buffer calculation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-kaanapali-iris-v3-6-9c0d1a67af4b@oss.qualcomm.com> References: <20260313-kaanapali-iris-v3-0-9c0d1a67af4b@oss.qualcomm.com> In-Reply-To: <20260313-kaanapali-iris-v3-0-9c0d1a67af4b@oss.qualcomm.com> To: Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov , Conor Dooley , Saravana Kannan , Joerg Roedel , Will Deacon , Robin Murphy , Stefan Schmidt , Hans Verkuil , Krzysztof Kozlowski , Vishnu Reddy , Hans Verkuil Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Bryan O'Donoghue , Vikash Garodia X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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While this works for most resolutions, certain configurations require a larger buffer size on iris4, causing firmware errors during decode. This resolves firmware failures seen with specific test vectors on kaanapali (iris4), and fixes the following failing fluster tests - PICSIZE_C_Bossen_1 - WPP_E_ericsson_MAIN_2 Co-developed-by: Vishnu Reddy Signed-off-by: Vishnu Reddy Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 51 ++++++++++++++++++= +++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 9270422c16019ba658ee8813940cb9110ad030a1..a4d599c49ce9052b609b9cedf65= f669ba78b5407 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -1755,6 +1755,55 @@ static u32 hfi_vpu4x_buffer_line_vp9d(u32 frame_widt= h, u32 frame_height, u32 _yu return lb_size + dpb_obp_size; } =20 +static u32 hfi_vpu4x_buffer_line_h265d(u32 frame_width, u32 frame_height, = bool is_opb, + u32 num_vpp_pipes) +{ + u32 num_lcu_per_pipe, fe_left_lb, se_left_lb, vsp_left_lb, top_lb, qp_siz= e, + dpb_obp =3D 0, lcu_size =3D 16; + + num_lcu_per_pipe =3D (DIV_ROUND_UP(frame_height, lcu_size) / num_vpp_pipe= s) + + (DIV_ROUND_UP(frame_height, lcu_size) % num_vpp_pipes); + + fe_left_lb =3D ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT) * + FE_LFT_CTRL_LINE_NUMBERS; + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * 2 * num_lcu_per_pipe), DMA_ALIGNME= NT) * + FE_LFT_DB_DATA_LINE_NUMBERS; + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * num_lcu_per_pipe), DMA_ALIGNMENT); + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * 2 * num_lcu_per_pipe), DMA_ALIGNME= NT); + fe_left_lb +=3D ALIGN((DMA_ALIGNMENT * 8 * num_lcu_per_pipe), DMA_ALIGNME= NT) * + FE_LFT_LR_DATA_LINE_NUMBERS; + + if (is_opb) + dpb_obp =3D size_dpb_opb(frame_height, lcu_size) * num_vpp_pipes; + + se_left_lb =3D max_t(u32, (ALIGN(frame_height, BUFFER_ALIGNMENT_16_BYTES)= >> 3) * + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE, + max_t(u32, (ALIGN(frame_height, BUFFER_ALIGNMENT_32_BYTES) >> 3) * + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE, + (ALIGN(frame_height, BUFFER_ALIGNMENT_64_BYTES) >> 3) * + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)); + + vsp_left_lb =3D ALIGN(DIV_ROUND_UP(frame_height, BUFFER_ALIGNMENT_64_BYTE= S) * + H265_NUM_TILE_ROW, DMA_ALIGNMENT); + + top_lb =3D ALIGN((DMA_ALIGNMENT * DIV_ROUND_UP(frame_width, lcu_size)), D= MA_ALIGNMENT) * + FE_TOP_CTRL_LINE_NUMBERS; + top_lb +=3D ALIGN(DMA_ALIGNMENT * 2 * DIV_ROUND_UP(frame_width, lcu_size)= , DMA_ALIGNMENT) * + FE_TOP_DATA_LUMA_LINE_NUMBERS; + top_lb +=3D ALIGN(DMA_ALIGNMENT * 2 * (DIV_ROUND_UP(frame_width, lcu_size= ) + 1), + DMA_ALIGNMENT) * FE_TOP_DATA_CHROMA_LINE_NUMBERS; + top_lb +=3D ALIGN(ALIGN(frame_width, BUFFER_ALIGNMENT_64_BYTES) * 2, DMA_= ALIGNMENT); + top_lb +=3D ALIGN(ALIGN(frame_width, BUFFER_ALIGNMENT_64_BYTES) * 6, DMA_= ALIGNMENT); + top_lb +=3D size_h265d_lb_vsp_top(frame_width, frame_height); + + qp_size =3D size_h265d_qp(frame_width, frame_height); + + return ((ALIGN(dpb_obp, DMA_ALIGNMENT) + ALIGN(se_left_lb, DMA_ALIGNMENT)= + + ALIGN(vsp_left_lb, DMA_ALIGNMENT)) * num_vpp_pipes) + + ALIGN(fe_left_lb, DMA_ALIGNMENT) + ALIGN(top_lb, DMA_ALIGNMENT) + + ALIGN(qp_size, DMA_ALIGNMENT); +} + static u32 iris_vpu4x_dec_line_size(struct iris_inst *inst) { u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; @@ -1770,7 +1819,7 @@ static u32 iris_vpu4x_dec_line_size(struct iris_inst = *inst) if (inst->codec =3D=3D V4L2_PIX_FMT_H264) return hfi_buffer_line_h264d(width, height, is_opb, num_vpp_pipes); else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) - return hfi_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); + return hfi_vpu4x_buffer_line_h265d(width, height, is_opb, num_vpp_pipes); else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) return hfi_vpu4x_buffer_line_vp9d(width, height, out_min_count, is_opb, num_vpp_pipes); --=20 2.34.1