From nobody Tue Apr 7 10:37:55 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88AFE3E558C for ; Fri, 13 Mar 2026 20:13:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773432798; cv=none; b=iwSeyLZfgkfFr+Kdrg5mrNEvWhE7/KLFaYlvI0FIx1mufu7KOHrX41p+T6JNv/371EVGqK+XuQrw4j1vwwba0/vrtxiOY8+vJkLfiMwg4qzDOtlinh4P0wx5NfQVmu19n+izbSIC+8E8WT0L6rkEUb0UIilvL/dznqAKTHgaLvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773432798; c=relaxed/simple; bh=eFfa8pngS/DmKEvFCXsC4nsmNtptODwmhs1lhpJ2xcU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JNLgFyaSsL3VYIoeW7OLIuXz9xLFJtBIUwmmBO/qAlwFGAGHF2eE7ikynqrkVylWZ/FQQVydTtdoCuAI532VWbwYTglhdpzP77TbY/w9hwYDTB73sgdFL+rdVslmTh0RILLv5Hd+hJhFozEJsgRB6S6gG+oDAkm4Vp9stVhAKBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=k5nIuEvJ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=TzRAbAn4; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="k5nIuEvJ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="TzRAbAn4" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62DG5tXO481675 for ; Fri, 13 Mar 2026 20:13:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nHs9LlqhbMQ+E2mRQnCbSgV7w6tqAO562A7rX+P2sX4=; b=k5nIuEvJ0zhg7sCH 04S54+jgIXyIZarX18+PZ6xUNWkqqV+Hrdsd2vabwQCVO+g5EwGiNzGtLzKvg+oO 3mN0WhVQdqKWq9FD43H8R4cxX30OGhkYZxgifN/B9DEuXsrLboo5uMff85tGGXja /N6K1XPLoFTNTLE/fyxe6FEAM8xtKvH7ebn0TlAz1Itxul2MvV9sXwpdtvYYqEeA +bMhWcddKXQJ9F5N8kS1HrI9PF5D4I6L6rsNbMK1x6tpCUf5vv0eSc62JRwYFGR7 psmOqCWVJBzF9FaeHkHth5Z7vyUU3X6gCdKbuZL7Zir1Ows3R4V7D0EeS5NA1wXd kLv69A== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cvfh7tbug-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 13 Mar 2026 20:13:15 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-8cb52a9c0eeso2421416885a.2 for ; Fri, 13 Mar 2026 13:13:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773432794; x=1774037594; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nHs9LlqhbMQ+E2mRQnCbSgV7w6tqAO562A7rX+P2sX4=; b=TzRAbAn4Zm4O74avGuIkaJvZqu+lpZyNNyaWpr+woXE6rHhlHgm2s0FgcIz8gA38fG TX+/+P5TvaPtBzcfsMiFL0h172NcL8u+snNzV6lr96FHQkdO+clBBq0lGVqHWrdFOQ00 nmamkoV7AYV0kp0yjVK0BC+0HHplIGM0eXFYa5wgZd1WanaBTCttij0jtEgbqHTvYvhC cn65IeUVv92vhqSCgUxlMO82Ty0sZ8chAquzD9I/06lVM653XQQnZrvPXEKSAxjbn/KB ZRrJNnJwYM7sHI+tHM0U1o0975E4PMj1mraQhcVUQ1bAnNUWpd4L77BAvKwGJglWMkTA WNOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773432794; x=1774037594; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nHs9LlqhbMQ+E2mRQnCbSgV7w6tqAO562A7rX+P2sX4=; b=ZXTQPpR7qKxgSJ2vACjfoYRQGVtT4sIpO76S2+VCz1Dp4KE/cfRdBxIx5GQ8cwRkb/ 3igGurBHkLvMR6kvdH+Zad5DDGONGQzxvEPgXXQdPMOe+giCJIswEk4fwSWSRZvvcGUi CHZwalIuBoLfTr1tDoPNriz+vNi2oxvvSUPBHyczmPjrq77cIBlZSTP1Nlovx7rXzEUj Bgq8MA7hPH/1DSbAp/L7HQOK+vfYRxRu2/COy2HVTpm/9jeqs2KAI9tECXZ6SMW/Qd9H B5slR4vMCpyGU1TzRhL95pUkIMTBchbHyhcJPdDAXA9YkrblJD7UT0xQh8lf1E2/MHNZ tLJw== X-Forwarded-Encrypted: i=1; AJvYcCV2GvP7/SyHeVohekGWrYVI6dedQbWJWaPG4okdDGMXhLp+ty8UwBU800GhHXm3emE0qPlYHlRu4DcwPpg=@vger.kernel.org X-Gm-Message-State: AOJu0YyRz3qcirZEctwvcFrR8+O0TCEkEg1Qr96JYaTd9BaK7VR7eyYe 1TVfBJ3e99wbYHbhbKa8e1cLNWUVyMml/Y4S8SN6I/LKE/UUdM3VurwRUy9p7CmLQepFiRouQ7x 9h7/RJMKBZBooolxlRllQw2nQVMxTpsVyHMn2LdTNZCs8yJZ2l9SBcA1qkUnIkwj0M0av9+cOra o= X-Gm-Gg: ATEYQzzYzD2Z0tZo2X0E1RybK1hi9t+Yb6MnDf/nXn574c+gUORcAnNlsCJtS0+UVGP a2UTVrvxipH3Dgep9/3ND2wzx9l8JbtjHa7wSZ3Dlvt/WyAcfJ6j8RmC1W50al5VqnWaXTH/Cb2 2ubtQGYBJZsEIL6fEK2ibbeTItyz/QgohBal+0Ukd3j3K3s0KYBeIjq+p+eyX2FCnINtWlSfH/e 7rFmOC4j7/hEeA7IeTTFifzaA2uhRZYHuRE50fIDR8Rpkbq6mfvhqrzrdAyM5tkFJMDX+zglPaf fxnvacSxJ3mHStyCDHSLi0iBFGhVpeXLidWT9yOrcCx+BkdZJDX3R87rnP30Wi0o83SfA7Gj3Vl TaEr1+xk2QNwFbhWMuJUugO6PABLXOzqwCb6hBRAAO66DeiHB5kveHp5bc8lnKE8rBc6DObTMjd VKxUuq9uViTVgSzVizpN8qpWiGW0Y3g7AwrLw= X-Received: by 2002:a05:620a:170f:b0:8cb:3505:443c with SMTP id af79cd13be357-8cdb5b5f2famr636444285a.44.1773432794076; Fri, 13 Mar 2026 13:13:14 -0700 (PDT) X-Received: by 2002:a05:620a:170f:b0:8cb:3505:443c with SMTP id af79cd13be357-8cdb5b5f2famr636439585a.44.1773432793414; Fri, 13 Mar 2026 13:13:13 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a155f33c15sm1681259e87.17.2026.03.13.13.13.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 13:13:12 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 13 Mar 2026 22:12:56 +0200 Subject: [PATCH v6 8/8] media: qcom: iris: split platform data from firmware data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-iris-platform-data-v6-8-1763bb837fd2@oss.qualcomm.com> References: <20260313-iris-platform-data-v6-0-1763bb837fd2@oss.qualcomm.com> In-Reply-To: <20260313-iris-platform-data-v6-0-1763bb837fd2@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=32745; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=eFfa8pngS/DmKEvFCXsC4nsmNtptODwmhs1lhpJ2xcU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBptG/EKh9V0jMbOmhJBYJ+qftanV6790d1lYQBa x9xKaqqJq2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabRvxAAKCRCLPIo+Aiko 1fcKB/9iQU4fgKuBZ/YgfwWMz5dQI/N1Z52WS+O+y8Iqg/nM9Nssej781ESKu0W/wvcZca/9dUV NC8iD/no2bzSS/+oRrU7KiUUIUrcO3Sct6A/6D0hPBoyXQngbe3djzntHQT8l6AG/4l+2zHoY9C neKlWbVbOcOxCTTKUhY50DaoCCdtIccWAd8PURBHW22t/ooHZi8jsXhe54LfmxiZ24vn0mJzZTu pEbBLrSQg8ejMuihe5W4S9ZSBHQ6uMmMbktwZWs8o2HfkjAip4ReBShUTiE597FmR3Enlxc+bbQ sjdLi9++22+gz5EBcEICfSYaru+jCqV5C5nKw3baXsFY1Ipf X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: WKKeLZIcW1G4zeHivRxvXvnTwIBkXc5u X-Proofpoint-GUID: WKKeLZIcW1G4zeHivRxvXvnTwIBkXc5u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDE2MSBTYWx0ZWRfX8k4r0GhdEe1D 96DEnrvXyjI8XKyU9shWJsCHStJjLqo5lMQ8+s1etwvQA+gqpEDsvkJYw0IIPqekoWUVpVAJr41 okG2jQviMcIahD8EnZ0lgnJFW4Bo/0B66vSk7/OfcrKenUSYvV8cnnkqEdycltyGVcFodriCEyw pigP/QmSMlgSA9WrXKeKUMiVshhXqauTWvdxRUmKXVbvAHgme0b4MPOELIsXBu6K72WIMENkHsR jPpGiFqjrXrWiJX3eTi6oKVCQGOEF+gPs8vXCj/X7Xlo47QTnOFHVtnX5qdgKgkcgaT8Xg6G2Ie 4lVtU/bKNqHe2FIRV5Gn6pQRe7ly6RCkH+WjTHqT4V2/OxNO9aROJx64jdIlbh57UHxIskjrw3z aQm0T6XKLhocal9WGSBu2MKh9cAp6zNJCeQXA0c+rE3b2t5jvmbwj4OiyRaL42LjGywNotVc59t nnpKlnbkki/bQKS/a+g== X-Authority-Analysis: v=2.4 cv=BpiQAIX5 c=1 sm=1 tr=0 ts=69b46fdb cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=Q_Tj2gVLSrreCV9GCYEA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_04,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130161 Finalize the logical separation of the software and hardware interface descriptions by moving hardware properties to the files specific to the particular VPU version. Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 6 +- .../iris/{iris_platform_gen1.c =3D> iris_hfi_gen1.c} | 136 ------------- .../iris/{iris_platform_gen2.c =3D> iris_hfi_gen2.c} | 223 ---------------= ------ .../platform/qcom/iris/iris_platform_common.h | 4 + .../platform/qcom/iris/iris_platform_sm8250.h | 29 +++ .../platform/qcom/iris/iris_platform_sm8550.h | 31 +++ .../media/platform/qcom/iris/iris_platform_vpu2.c | 126 ++++++++++++ .../media/platform/qcom/iris/iris_platform_vpu3x.c | 214 +++++++++++++++++= +++ 8 files changed, 408 insertions(+), 361 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 2fde45f81727..48e415cbc439 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -4,14 +4,16 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_ctrls.o \ iris_firmware.o \ iris_hfi_common.o \ + iris_hfi_gen1.o \ iris_hfi_gen1_command.o \ iris_hfi_gen1_response.o \ + iris_hfi_gen2.o \ iris_hfi_gen2_command.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_gen1.o \ - iris_platform_gen2.o \ + iris_platform_vpu2.o \ + iris_platform_vpu3x.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_hfi_gen1.c similarity index 67% rename from drivers/media/platform/qcom/iris/iris_platform_gen1.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen1.c index b2d18459a811..60f51a1ba941 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -3,38 +3,16 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_platform_common.h" -#include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" -#include "iris_instance.h" - -#include "iris_platform_sc7280.h" =20 #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 -#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 -static struct iris_fmt platform_fmts_sm8250_dec[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, @@ -248,56 +226,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8250_enc[] =3D { }, }; =20 -static struct platform_inst_caps platform_inst_cap_sm8250 =3D { - .min_frame_width =3D 128, - .max_frame_width =3D 8192, - .min_frame_height =3D 128, - .max_frame_height =3D 8192, - .max_mbpf =3D 138240, - .mb_cycles_vsp =3D 25, - .mb_cycles_vpp =3D 200, - .max_frame_rate =3D MAXIMUM_FPS, - .max_operating_rate =3D MAXIMUM_FPS, -}; - -static const struct icc_info sm8250_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8250_clk_reset_table[] =3D { "bus", "core" }; - -static const struct bw_info sm8250_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 2403000 }, - { ((4096 * 2160) / 256) * 30, 1224000 }, - { ((1920 * 1080) / 256) * 60, 812000 }, - { ((1920 * 1080) / 256) * 30, 416000 }, -}; - -static const char * const sm8250_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; - -static const struct platform_clk_data sm8250_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8250_opp_clk_table[] =3D { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8250[] =3D { - { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, - }, -}; - static const u32 sm8250_vdec_input_config_param_default[] =3D { HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -356,67 +284,3 @@ const struct iris_firmware_data iris_hfi_gen1_data =3D= { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; - -const struct iris_platform_data sm8250_data =3D { - .firmware_data =3D &iris_hfi_gen1_data, - .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu2_ops, - .icc_tbl =3D sm8250_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), - .clk_rst_tbl =3D sm8250_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8250_clk_reset_table), - .bw_tbl_dec =3D sm8250_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl =3D sm8250_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl =3D sm8250_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl =3D sm8250_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), - .opp_clk_tbl =3D sm8250_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu-1.0/venus.mbn", - .inst_iris_fmts =3D platform_fmts_sm8250_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps =3D &platform_inst_cap_sm8250, - .tz_cp_config_data =3D tz_cp_config_sm8250, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sc7280_data =3D { - .firmware_data =3D &iris_hfi_gen1_data, - .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu2_ops, - .icc_tbl =3D sm8250_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), - .bw_tbl_dec =3D sc7280_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl =3D sm8250_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl =3D sc7280_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl =3D sc7280_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), - .opp_clk_tbl =3D sc7280_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu20_p1.mbn", - .inst_iris_fmts =3D platform_fmts_sm8250_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps =3D &platform_inst_cap_sm8250, - .tz_cp_config_data =3D tz_cp_config_sm8250, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 1, - .no_aon =3D true, - .max_session_count =3D 16, - .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, - /* max spec for SC7280 is 4096x2176@60fps */ - .max_core_mbps =3D 4096 * 2176 / 256 * 60, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_hfi_gen2.c similarity index 76% rename from drivers/media/platform/qcom/iris/iris_platform_gen2.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen2.c index 1a54a9a96285..071009a9ce4c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -4,40 +4,14 @@ * Copyright (c) 2025 Linaro Ltd */ =20 -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" =20 -#include "iris_platform_qcs8300.h" -#include "iris_platform_sm8650.h" -#include "iris_platform_sm8750.h" - -#define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 -static struct iris_fmt platform_fmts_sm8550_dec[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_AV1] =3D { - .pixfmt =3D V4L2_PIX_FMT_AV1, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, @@ -742,58 +716,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8550_enc[] =3D { }, }; =20 -static struct platform_inst_caps platform_inst_cap_sm8550 =3D { - .min_frame_width =3D 96, - .max_frame_width =3D 8192, - .min_frame_height =3D 96, - .max_frame_height =3D 8192, - .max_mbpf =3D (8192 * 4352) / 256, - .mb_cycles_vpp =3D 200, - .mb_cycles_fw =3D 489583, - .mb_cycles_fw_vpp =3D 66234, - .num_comv =3D 0, - .max_frame_rate =3D MAXIMUM_FPS, - .max_operating_rate =3D MAXIMUM_FPS, -}; - -static const struct icc_info sm8550_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8550_clk_reset_table[] =3D { "bus" }; - -static const struct bw_info sm8550_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 1608000 }, - { ((4096 * 2160) / 256) * 30, 826000 }, - { ((1920 * 1080) / 256) * 60, 567000 }, - { ((1920 * 1080) / 256) * 30, 294000 }, -}; - -static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; - -static const struct platform_clk_data sm8550_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8550_opp_clk_table[] =3D { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8550[] =3D { - { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, - }, -}; - static const u32 sm8550_vdec_input_config_params_default[] =3D { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -969,148 +891,3 @@ const struct iris_firmware_data iris_hfi_gen2_data = =3D { .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; - -const struct iris_platform_data sm8550_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .get_vpu_buffer_size =3D iris_vpu33_buf_size, - .vpu_ops =3D &iris_vpu33_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8650_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl =3D sm8650_controller_reset_table, - .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sm8750_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .get_vpu_buffer_size =3D iris_vpu33_buf_size, - .vpu_ops =3D &iris_vpu35_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8750_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8750_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu35_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_qcs8300, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 2, - .max_session_count =3D 16, - .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, - .max_core_mbps =3D (((3840 * 2176) / 256) * 120), -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 401069bd7396..b209cdb6c462 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -40,6 +40,10 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 +extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_firmware_data iris_hfi_gen2_vpu33_data; + extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.h new file mode 100644 index 000000000000..50306043eb8e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_SM8250_H__ +#define __IRIS_PLATFORM_SM8250_H__ + +static const struct bw_info sm8250_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 2403000 }, + { ((4096 * 2160) / 256) * 30, 1224000 }, + { ((1920 * 1080) / 256) * 60, 812000 }, + { ((1920 * 1080) / 256) * 30, 416000 }, +}; + +static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; + +static const struct platform_clk_data sm8250_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8250_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.h new file mode 100644 index 000000000000..a9d9709c2e35 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_SM8550_H__ +#define __IRIS_PLATFORM_SM8550_H__ + +static const char * const sm8550_clk_reset_table[] =3D { "bus" }; + +static const struct platform_clk_data sm8550_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8550 =3D { + .min_frame_width =3D 96, + .max_frame_width =3D 8192, + .min_frame_height =3D 96, + .max_frame_height =3D 8192, + .max_mbpf =3D (8192 * 4352) / 256, + .mb_cycles_vpp =3D 200, + .mb_cycles_fw =3D 489583, + .mb_cycles_fw_vpp =3D 66234, + .num_comv =3D 0, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c new file mode 100644 index 000000000000..b3f5fddd43c2 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_platform_common.h" +#include "iris_resources.h" +#include "iris_hfi_gen1.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" +#include "iris_instance.h" + +#include "iris_platform_sc7280.h" +#include "iris_platform_sm8250.h" + +static struct iris_fmt iris_fmts_vpu2_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static struct platform_inst_caps platform_inst_cap_vpu2 =3D { + .min_frame_width =3D 128, + .max_frame_width =3D 8192, + .min_frame_height =3D 128, + .max_frame_height =3D 8192, + .max_mbpf =3D 138240, + .mb_cycles_vsp =3D 25, + .mb_cycles_vpp =3D 200, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + +static const struct icc_info iris_icc_info_vpu2[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const iris_clk_reset_table_vpu2[] =3D { "bus", "core" = }; + +static const char * const iris_pmdomain_table_vpu2[] =3D { "venus", "vcode= c0" }; + +static const struct tz_cp_config tz_cp_config_vpu2[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +const struct iris_platform_data sc7280_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu2_ops, + .icc_tbl =3D iris_icc_info_vpu2, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), + .bw_tbl_dec =3D sc7280_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl =3D iris_pmdomain_table_vpu2, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu2), + .opp_pd_tbl =3D sc7280_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl =3D sc7280_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl =3D sc7280_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu20_p1.mbn", + .inst_iris_fmts =3D iris_fmts_vpu2_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu2_dec), + .inst_caps =3D &platform_inst_cap_vpu2, + .tz_cp_config_data =3D tz_cp_config_vpu2, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 1, + .no_aon =3D true, + .max_session_count =3D 16, + .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps =3D 4096 * 2176 / 256 * 60, +}; + +const struct iris_platform_data sm8250_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu2_ops, + .icc_tbl =3D iris_icc_info_vpu2, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), + .clk_rst_tbl =3D iris_clk_reset_table_vpu2, + .clk_rst_tbl_size =3D ARRAY_SIZE(iris_clk_reset_table_vpu2), + .bw_tbl_dec =3D sm8250_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), + .pmdomain_tbl =3D iris_pmdomain_table_vpu2, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu2), + .opp_pd_tbl =3D sm8250_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), + .clk_tbl =3D sm8250_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl =3D sm8250_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu-1.0/venus.mbn", + .inst_iris_fmts =3D iris_fmts_vpu2_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu2_dec), + .inst_caps =3D &platform_inst_cap_vpu2, + .tz_cp_config_data =3D tz_cp_config_vpu2, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu2), + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c new file mode 100644 index 000000000000..aeb4cabc1160 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Linaro Ltd + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#include "iris_platform_qcs8300.h" +#include "iris_platform_sm8550.h" +#include "iris_platform_sm8650.h" +#include "iris_platform_sm8750.h" + +#define VIDEO_ARCH_LX 1 + +static struct iris_fmt iris_fmts_vpu3x_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] =3D { + .pixfmt =3D V4L2_PIX_FMT_AV1, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct icc_info iris_icc_info_vpu3x[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const struct bw_info iris_bw_table_dec_vpu3x[] =3D { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const iris_pmdomain_table_vpu3x[] =3D { "venus", "vcod= ec0" }; + +static const char * const iris_opp_pd_table_vpu3x[] =3D { "mxc", "mmcx" }; + +static const char * const iris_opp_clk_table_vpu3x[] =3D { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_vpu3[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D iris_icc_info_vpu3x, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", + .inst_iris_fmts =3D iris_fmts_vpu3x_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps =3D &platform_inst_cap_qcs8300, + .tz_cp_config_data =3D tz_cp_config_vpu3, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 2, + .max_session_count =3D 16, + .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, + .max_core_mbps =3D (((3840 * 2176) / 256) * 120), +}; + +const struct iris_platform_data sm8550_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D iris_icc_info_vpu3x, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts =3D iris_fmts_vpu3x_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_vpu3, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .get_vpu_buffer_size =3D iris_vpu33_buf_size, + .vpu_ops =3D &iris_vpu33_ops, + .icc_tbl =3D iris_icc_info_vpu3x, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts =3D iris_fmts_vpu3x_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_vpu3, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +const struct iris_platform_data sm8750_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .get_vpu_buffer_size =3D iris_vpu33_buf_size, + .vpu_ops =3D &iris_vpu35_ops, + .icc_tbl =3D iris_icc_info_vpu3x, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl =3D sm8750_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), + .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, + .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .clk_tbl =3D sm8750_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu35_p4.mbn", + .inst_iris_fmts =3D iris_fmts_vpu3x_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_vpu3, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_vpu3), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; --=20 2.47.3