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Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 6 +- .../iris/{iris_platform_gen1.c =3D> iris_hfi_gen1.c} | 134 ------------- .../iris/{iris_platform_gen2.c =3D> iris_hfi_gen2.c} | 219 ---------------= ------ .../platform/qcom/iris/iris_platform_common.h | 4 + .../platform/qcom/iris/iris_platform_sm8250.h | 29 +++ .../platform/qcom/iris/iris_platform_sm8550.h | 31 +++ .../media/platform/qcom/iris/iris_platform_vpu2.c | 124 ++++++++++++ .../media/platform/qcom/iris/iris_platform_vpu3.c | 210 +++++++++++++++++= +++ 8 files changed, 402 insertions(+), 355 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 2fde45f81727..67a12f42b3a6 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -4,14 +4,16 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_ctrls.o \ iris_firmware.o \ iris_hfi_common.o \ + iris_hfi_gen1.o \ iris_hfi_gen1_command.o \ iris_hfi_gen1_response.o \ + iris_hfi_gen2.o \ iris_hfi_gen2_command.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_gen1.o \ - iris_platform_gen2.o \ + iris_platform_vpu2.o \ + iris_platform_vpu3.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_hfi_gen1.c similarity index 67% rename from drivers/media/platform/qcom/iris/iris_platform_gen1.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen1.c index 27f2ef04cffe..18c97fa8a492 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -3,38 +3,16 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_platform_common.h" -#include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" -#include "iris_instance.h" - -#include "iris_platform_sc7280.h" =20 #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 -#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 -static struct iris_fmt platform_fmts_sm8250_dec[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, @@ -248,56 +226,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8250_enc[] =3D { }, }; =20 -static struct platform_inst_caps platform_inst_cap_sm8250 =3D { - .min_frame_width =3D 128, - .max_frame_width =3D 8192, - .min_frame_height =3D 128, - .max_frame_height =3D 8192, - .max_mbpf =3D 138240, - .mb_cycles_vsp =3D 25, - .mb_cycles_vpp =3D 200, - .max_frame_rate =3D MAXIMUM_FPS, - .max_operating_rate =3D MAXIMUM_FPS, -}; - -static const struct icc_info sm8250_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8250_clk_reset_table[] =3D { "bus", "core" }; - -static const struct bw_info sm8250_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 2403000 }, - { ((4096 * 2160) / 256) * 30, 1224000 }, - { ((1920 * 1080) / 256) * 60, 812000 }, - { ((1920 * 1080) / 256) * 30, 416000 }, -}; - -static const char * const sm8250_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; - -static const struct platform_clk_data sm8250_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8250_opp_clk_table[] =3D { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8250[] =3D { - { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, - }, -}; - static const u32 sm8250_vdec_input_config_param_default[] =3D { HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -357,65 +285,3 @@ const struct iris_firmware_data iris_hfi_gen1_data =3D= { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; - -const struct iris_platform_data sm8250_data =3D { - .firmware_data =3D &iris_hfi_gen1_data, - .vpu_ops =3D &iris_vpu2_ops, - .icc_tbl =3D sm8250_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), - .clk_rst_tbl =3D sm8250_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8250_clk_reset_table), - .bw_tbl_dec =3D sm8250_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl =3D sm8250_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl =3D sm8250_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl =3D sm8250_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), - .opp_clk_tbl =3D sm8250_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu-1.0/venus.mbn", - .inst_iris_fmts =3D platform_fmts_sm8250_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps =3D &platform_inst_cap_sm8250, - .tz_cp_config_data =3D tz_cp_config_sm8250, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sc7280_data =3D { - .firmware_data =3D &iris_hfi_gen1_data, - .vpu_ops =3D &iris_vpu2_ops, - .icc_tbl =3D sm8250_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), - .bw_tbl_dec =3D sc7280_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl =3D sm8250_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl =3D sc7280_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl =3D sc7280_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), - .opp_clk_tbl =3D sc7280_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu20_p1.mbn", - .inst_iris_fmts =3D platform_fmts_sm8250_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps =3D &platform_inst_cap_sm8250, - .tz_cp_config_data =3D tz_cp_config_sm8250, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 1, - .no_aon =3D true, - .max_session_count =3D 16, - .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, - /* max spec for SC7280 is 4096x2176@60fps */ - .max_core_mbps =3D 4096 * 2176 / 256 * 60, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_hfi_gen2.c similarity index 78% rename from drivers/media/platform/qcom/iris/iris_platform_gen2.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen2.c index a83f6910f8b7..9897864a0b3b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -4,40 +4,14 @@ * Copyright (c) 2025 Linaro Ltd */ =20 -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" =20 -#include "iris_platform_qcs8300.h" -#include "iris_platform_sm8650.h" -#include "iris_platform_sm8750.h" - -#define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 -static struct iris_fmt platform_fmts_sm8550_dec[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_AV1] =3D { - .pixfmt =3D V4L2_PIX_FMT_AV1, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, @@ -742,58 +716,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8550_enc[] =3D { }, }; =20 -static struct platform_inst_caps platform_inst_cap_sm8550 =3D { - .min_frame_width =3D 96, - .max_frame_width =3D 8192, - .min_frame_height =3D 96, - .max_frame_height =3D 8192, - .max_mbpf =3D (8192 * 4352) / 256, - .mb_cycles_vpp =3D 200, - .mb_cycles_fw =3D 489583, - .mb_cycles_fw_vpp =3D 66234, - .num_comv =3D 0, - .max_frame_rate =3D MAXIMUM_FPS, - .max_operating_rate =3D MAXIMUM_FPS, -}; - -static const struct icc_info sm8550_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8550_clk_reset_table[] =3D { "bus" }; - -static const struct bw_info sm8550_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 1608000 }, - { ((4096 * 2160) / 256) * 30, 826000 }, - { ((1920 * 1080) / 256) * 60, 567000 }, - { ((1920 * 1080) / 256) * 30, 294000 }, -}; - -static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; - -static const struct platform_clk_data sm8550_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8550_opp_clk_table[] =3D { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8550[] =3D { - { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, - }, -}; - static const u32 sm8550_vdec_input_config_params_default[] =3D { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -1035,144 +957,3 @@ const struct iris_firmware_data iris_hfi_gen2_vpu33_= data =3D { .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; - -const struct iris_platform_data sm8550_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data =3D { - .firmware_data =3D &iris_hfi_gen2_vpu33_data, - .vpu_ops =3D &iris_vpu33_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8650_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl =3D sm8650_controller_reset_table, - .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sm8750_data =3D { - .firmware_data =3D &iris_hfi_gen2_vpu33_data, - .vpu_ops =3D &iris_vpu35_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8750_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8750_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu35_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_qcs8300, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 2, - .max_session_count =3D 16, - .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, - .max_core_mbps =3D (((3840 * 2176) / 256) * 120), -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 1a870fec4f31..5be028af5ec6 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -40,6 +40,10 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 +extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_firmware_data iris_hfi_gen2_vpu33_data; + extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.h new file mode 100644 index 000000000000..50306043eb8e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_SM8250_H__ +#define __IRIS_PLATFORM_SM8250_H__ + +static const struct bw_info sm8250_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 2403000 }, + { ((4096 * 2160) / 256) * 30, 1224000 }, + { ((1920 * 1080) / 256) * 60, 812000 }, + { ((1920 * 1080) / 256) * 30, 416000 }, +}; + +static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; + +static const struct platform_clk_data sm8250_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8250_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.h new file mode 100644 index 000000000000..a9d9709c2e35 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_SM8550_H__ +#define __IRIS_PLATFORM_SM8550_H__ + +static const char * const sm8550_clk_reset_table[] =3D { "bus" }; + +static const struct platform_clk_data sm8550_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8550 =3D { + .min_frame_width =3D 96, + .max_frame_width =3D 8192, + .min_frame_height =3D 96, + .max_frame_height =3D 8192, + .max_mbpf =3D (8192 * 4352) / 256, + .mb_cycles_vpp =3D 200, + .mb_cycles_fw =3D 489583, + .mb_cycles_fw_vpp =3D 66234, + .num_comv =3D 0, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c new file mode 100644 index 000000000000..74c8f38e849b --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_platform_common.h" +#include "iris_resources.h" +#include "iris_hfi_gen1.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" +#include "iris_instance.h" + +#include "iris_platform_sc7280.h" +#include "iris_platform_sm8250.h" + +static struct iris_fmt platform_fmts_sm8250_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8250 =3D { + .min_frame_width =3D 128, + .max_frame_width =3D 8192, + .min_frame_height =3D 128, + .max_frame_height =3D 8192, + .max_mbpf =3D 138240, + .mb_cycles_vsp =3D 25, + .mb_cycles_vpp =3D 200, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + +static const struct icc_info sm8250_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const sm8250_clk_reset_table[] =3D { "bus", "core" }; + +static const char * const sm8250_pmdomain_table[] =3D { "venus", "vcodec0"= }; + +static const struct tz_cp_config tz_cp_config_sm8250[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +const struct iris_platform_data sc7280_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, + .vpu_ops =3D &iris_vpu2_ops, + .icc_tbl =3D sm8250_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), + .bw_tbl_dec =3D sc7280_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl =3D sm8250_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl =3D sc7280_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl =3D sc7280_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl =3D sc7280_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu20_p1.mbn", + .inst_iris_fmts =3D platform_fmts_sm8250_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), + .inst_caps =3D &platform_inst_cap_sm8250, + .tz_cp_config_data =3D tz_cp_config_sm8250, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 1, + .no_aon =3D true, + .max_session_count =3D 16, + .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps =3D 4096 * 2176 / 256 * 60, +}; + +const struct iris_platform_data sm8250_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, + .vpu_ops =3D &iris_vpu2_ops, + .icc_tbl =3D sm8250_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), + .clk_rst_tbl =3D sm8250_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8250_clk_reset_table), + .bw_tbl_dec =3D sm8250_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), + .pmdomain_tbl =3D sm8250_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl =3D sm8250_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), + .clk_tbl =3D sm8250_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl =3D sm8250_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu-1.0/venus.mbn", + .inst_iris_fmts =3D platform_fmts_sm8250_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), + .inst_caps =3D &platform_inst_cap_sm8250, + .tz_cp_config_data =3D tz_cp_config_sm8250, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu3.c new file mode 100644 index 000000000000..2c0e5be72920 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Linaro Ltd + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#include "iris_platform_qcs8300.h" +#include "iris_platform_sm8550.h" +#include "iris_platform_sm8650.h" +#include "iris_platform_sm8750.h" + +#define VIDEO_ARCH_LX 1 + +static struct iris_fmt platform_fmts_sm8550_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] =3D { + .pixfmt =3D V4L2_PIX_FMT_AV1, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct icc_info sm8550_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const struct bw_info sm8550_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; + +static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; + +static const char * const sm8550_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_sm8550[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_qcs8300, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 2, + .max_session_count =3D 16, + .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, + .max_core_mbps =3D (((3840 * 2176) / 256) * 120), +}; + +const struct iris_platform_data sm8550_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .vpu_ops =3D &iris_vpu33_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +const struct iris_platform_data sm8750_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .vpu_ops =3D &iris_vpu35_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8750_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8750_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu35_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; --=20 2.47.3