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Drop it from the platform data and use the constant instead. Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_firmware.c | 11 ++++++----- drivers/media/platform/qcom/iris/iris_platform_common.h | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen1.c | 2 -- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 4 ---- 4 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 5f408024e967..bc6c5c3e00c3 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -12,11 +12,12 @@ #include "iris_core.h" #include "iris_firmware.h" =20 +#define IRIS_PAS_ID 9 + #define MAX_FIRMWARE_NAME_SIZE 128 =20 static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) { - u32 pas_id =3D core->iris_platform_data->pas_id; const struct firmware *firmware =3D NULL; struct device *dev =3D core->dev; struct resource res; @@ -53,7 +54,7 @@ static int iris_load_fw_to_memory(struct iris_core *core,= const char *fw_name) } =20 ret =3D qcom_mdt_load(dev, firmware, fw_name, - pas_id, mem_virt, mem_phys, res_size, NULL); + IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); =20 memunmap(mem_virt); err_release_fw: @@ -79,7 +80,7 @@ int iris_fw_load(struct iris_core *core) return -ENOMEM; } =20 - ret =3D qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); + ret =3D qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); if (ret) { dev_err(core->dev, "auth and reset failed: %d\n", ret); return ret; @@ -93,7 +94,7 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + qcom_scm_pas_shutdown(IRIS_PAS_ID); return ret; } } @@ -103,7 +104,7 @@ int iris_fw_load(struct iris_core *core) =20 int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + return qcom_scm_pas_shutdown(IRIS_PAS_ID); } =20 int iris_set_hw_state(struct iris_core *core, bool resume) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f42e1798747c..e4eefc646c7f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -12,7 +12,6 @@ struct iris_core; struct iris_inst; =20 -#define IRIS_PAS_ID 9 #define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */ #define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* mil= liseconds */ =20 @@ -226,7 +225,6 @@ struct iris_platform_data { unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; - u32 pas_id; struct iris_fmt *inst_iris_fmts; u32 inst_iris_fmts_size; struct platform_inst_caps *inst_caps; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index aa71f7f53ee3..07ed572e895b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -360,7 +360,6 @@ const struct iris_platform_data sm8250_data =3D { /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu-1.0/venus.mbn", - .pas_id =3D IRIS_PAS_ID, .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, @@ -413,7 +412,6 @@ const struct iris_platform_data sc7280_data =3D { /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu20_p1.mbn", - .pas_id =3D IRIS_PAS_ID, .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index a526b50a1cd3..1f23ddb972f0 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -934,7 +934,6 @@ const struct iris_platform_data sm8550_data =3D { /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .pas_id =3D IRIS_PAS_ID, .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, @@ -1038,7 +1037,6 @@ const struct iris_platform_data sm8650_data =3D { /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu33_p4.mbn", - .pas_id =3D IRIS_PAS_ID, .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, @@ -1133,7 +1131,6 @@ const struct iris_platform_data sm8750_data =3D { /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu35_p4.mbn", - .pas_id =3D IRIS_PAS_ID, .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, @@ -1232,7 +1229,6 @@ const struct iris_platform_data qcs8300_data =3D { /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", - .pas_id =3D IRIS_PAS_ID, .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_qcs8300, --=20 2.47.3 From nobody Tue Apr 7 12:54:04 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45717368947 for ; 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Extract it to a iris_vpu_common.c and call it directly from iris_vpu_power_on(). Later, if any of the devices requires special handling, it can be sorted out separately. Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_platform_common.h | 1 - drivers/media/platform/qcom/iris/iris_platform_gen1.c | 7 ------- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 9 --------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 7 ++++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 5 files changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index e4eefc646c7f..d7106902698c 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -207,7 +207,6 @@ struct iris_platform_data { struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); const struct vpu_ops *vpu_ops; - void (*set_preset_registers)(struct iris_core *core); const struct icc_info *icc_tbl; unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 07ed572e895b..ed07d1b00e43 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -260,11 +260,6 @@ static struct platform_inst_caps platform_inst_cap_sm8= 250 =3D { .max_operating_rate =3D MAXIMUM_FPS, }; =20 -static void iris_set_sm8250_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - static const struct icc_info sm8250_icc_table[] =3D { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -343,7 +338,6 @@ const struct iris_platform_data sm8250_data =3D { .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, - .set_preset_registers =3D iris_set_sm8250_preset_registers, .icc_tbl =3D sm8250_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), .clk_rst_tbl =3D sm8250_clk_reset_table, @@ -397,7 +391,6 @@ const struct iris_platform_data sc7280_data =3D { .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, - .set_preset_registers =3D iris_set_sm8250_preset_registers, .icc_tbl =3D sm8250_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), .bw_tbl_dec =3D sc7280_bw_table_dec, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 1f23ddb972f0..c84d4399f84d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -756,11 +756,6 @@ static struct platform_inst_caps platform_inst_cap_sm8= 550 =3D { .max_operating_rate =3D MAXIMUM_FPS, }; =20 -static void iris_set_sm8550_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - static const struct icc_info sm8550_icc_table[] =3D { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -917,7 +912,6 @@ const struct iris_platform_data sm8550_data =3D { .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, - .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl =3D sm8550_clk_reset_table, @@ -1018,7 +1012,6 @@ const struct iris_platform_data sm8650_data =3D { .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu33_ops, - .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl =3D sm8650_clk_reset_table, @@ -1114,7 +1107,6 @@ const struct iris_platform_data sm8750_data =3D { .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu35_ops, - .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl =3D sm8750_clk_reset_table, @@ -1212,7 +1204,6 @@ const struct iris_platform_data qcs8300_data =3D { .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, - .set_preset_registers =3D iris_set_sm8550_preset_registers, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), .clk_rst_tbl =3D sm8550_clk_reset_table, diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 548e5f1727fd..faabf53126f3 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -468,7 +468,7 @@ int iris_vpu_power_on(struct iris_core *core) =20 iris_opp_set_rate(core->dev, freq); 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Reviewed-by: Dikshita Agarwal Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c | 16 ++++++++----= ---- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 30bfd90d423b..e4f25b7f5d04 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1205,7 +1205,7 @@ static u32 iris_hfi_gen2_buf_type_from_driver(u32 dom= ain, enum iris_buffer_type } } =20 -static int iris_set_num_comv(struct iris_inst *inst) +static int iris_hfi_gen2_set_num_comv(struct iris_inst *inst) { struct platform_inst_caps *caps; struct iris_core *core =3D inst->core; @@ -1220,12 +1220,12 @@ static int iris_set_num_comv(struct iris_inst *inst) num_comv =3D (inst->codec =3D=3D V4L2_PIX_FMT_AV1) ? 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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a1563775a2sm1347475e87.89.2026.03.13.00.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 00:52:42 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 13 Mar 2026 09:52:36 +0200 Subject: [PATCH v5 4/8] media: qcom: iris: split HFI session ops from core ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-iris-platform-data-v5-4-180484af4490@oss.qualcomm.com> References: <20260313-iris-platform-data-v5-0-180484af4490@oss.qualcomm.com> In-Reply-To: <20260313-iris-platform-data-v5-0-180484af4490@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=23729; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=oq8rpHKCSOKqM9VKEq685jP8JJci+C1FsX62wc7Er8k=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBps8JCns68V715+lDTnphBS4d5rgm01a4YCbO+x YSPtqJujnqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCabPCQgAKCRCLPIo+Aiko 1T+8B/0Y6Yb1qRCOUhJIdYMoPZAYrnAXLkWG/IDh/q3wlS6BXXWbigqRrMR/tJwvM0ccvNqlAKj hiGwgOf2Iz8CSyc3eKXuHmtQOiVSeylJz+y8xx1wU2WviJwj8weEHJ8zC3/AsyfKYpMBJKgsOA5 tIHP+D4X9eOeW4/dOJVXU2fkxBKE4c3RqV/nGVVEUAtQIMnp/bvdAqNOfmwgJvU3IwfnICqntqa PdPukf3tKWEsU+C9MENSkoG9+r5HYipR1UvLUKFuMOokjjPcO3LS7G9SXRffFC76fDy67uvCmsi 8qao8nrwfDXQcAbl8ry6/BGAPkx2ohug7S4TrBmXhp4qJ6R2 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: Cgvo_UsDps7HaizcjEH6c_yErPXUbCUu X-Proofpoint-GUID: Cgvo_UsDps7HaizcjEH6c_yErPXUbCUu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA2MSBTYWx0ZWRfX72371HdaciEp MiZEHr6isKF8K05+ctZ3/4G4BFBoCjyv8kJilYAghw0gpbLf0xammKP39bEH/Q5WjAeGf5uKI24 xN8JA5bzBfeFqGHaV3fHD46mej0mAyeG4syha/JatUiixz7QY71CrZp46hudC+l8RIbqZGQ1yBc DyzaGdw074OLyTKX5HK42S1DRsRPi1/HifK/o8aKEJWiNSkQYGQQ0CAppaEbaHrtDYf0pvy2E0y 1YyGv/0bdDGTkr7dlf0tQv5XFaSfCBS/Q1voUCAvlSw4+aFApxfNsISEMoFKk0CGA9xU6m2VEsY KaE45LQMO3TiipNOmLwL0C/CNy38NYfIMr85GMQ61xiRDf0R7Osfz6WgdLbZlXfaLA0ct+7jMqW +SwOcbvahfOoCadgQphi2HsBqo+haRdsrn+7JyGRtULqa4ogZ/JUEfeqdpi0Yz8XA6qOrZqwA/q rwNwrTd93Xxz8gg/WDg== X-Authority-Analysis: v=2.4 cv=S9nUAYsP c=1 sm=1 tr=0 ts=69b3c24d cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=GJ9kf5zHVpckMw0GqqUA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130061 Calling HFI instance-specific ops should not require double indirection through the core ops. Split instance-specific ops to a separate struct, keep a pointer to it in struct iris_inst and set it directly in the get_instance function. Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_buffer.c | 4 +- drivers/media/platform/qcom/iris/iris_common.c | 8 ++-- drivers/media/platform/qcom/iris/iris_ctrls.c | 46 +++++++++++-------= ---- drivers/media/platform/qcom/iris/iris_hfi_common.h | 3 ++ .../platform/qcom/iris/iris_hfi_gen1_command.c | 23 ++++++++--- .../platform/qcom/iris/iris_hfi_gen2_command.c | 17 +++++--- drivers/media/platform/qcom/iris/iris_instance.h | 4 ++ drivers/media/platform/qcom/iris/iris_vb2.c | 2 +- drivers/media/platform/qcom/iris/iris_vdec.c | 6 +-- drivers/media/platform/qcom/iris/iris_venc.c | 4 +- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 11 files changed, 72 insertions(+), 47 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 9151f43bc6b9..f55b7c608116 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -404,7 +404,7 @@ int iris_create_internal_buffers(struct iris_inst *inst= , u32 plane) =20 int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; int ret; =20 ret =3D hfi_ops->session_queue_buf(inst, buf); @@ -572,7 +572,7 @@ int iris_destroy_dequeued_internal_buffers(struct iris_= inst *inst, u32 plane) static int iris_release_internal_buffers(struct iris_inst *inst, enum iris_buffer_type buffer_type) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; struct iris_buffer *buffer, *next; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media= /platform/qcom/iris/iris_common.c index 7f1c7fe144f7..25836561bcf3 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -48,7 +48,7 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct = vb2_v4l2_buffer *vbuf) =20 int iris_process_streamon_input(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; enum iris_inst_sub_state set_sub_state =3D 0; int ret; =20 @@ -90,7 +90,7 @@ int iris_process_streamon_input(struct iris_inst *inst) =20 int iris_process_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state =3D 0; bool drain_active, drc_active, first_ipsc; int ret =3D 0; @@ -189,7 +189,7 @@ static void iris_flush_deferred_buffers(struct iris_ins= t *inst, =20 static void iris_kill_session(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; =20 if (!inst->session_id) return; @@ -200,7 +200,7 @@ static void iris_kill_session(struct iris_inst *inst) =20 int iris_session_streamoff(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; enum iris_buffer_type buffer_type; int ret; =20 diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 3cec957580f5..5a24aa869b2d 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -399,7 +399,7 @@ static u32 iris_get_port_info(struct iris_inst *inst, =20 int iris_set_u32_enum(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_value =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 @@ -412,7 +412,7 @@ int iris_set_u32_enum(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap =20 int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type ca= p_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_value =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 @@ -425,7 +425,7 @@ int iris_set_u32(struct iris_inst *inst, enum platform_= inst_fw_cap_type cap_id) =20 int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type = cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; struct v4l2_format *inp_f =3D inst->fmt_src; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; u32 height =3D inp_f->fmt.pix_mp.height; @@ -446,7 +446,7 @@ int iris_set_stage(struct iris_inst *inst, enum platfor= m_inst_fw_cap_type cap_id =20 int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 work_route =3D inst->fw_caps[PIPE].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 @@ -459,7 +459,7 @@ int iris_set_pipe(struct iris_inst *inst, enum platform= _inst_fw_cap_type cap_id) =20 int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_id, hfi_value; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { @@ -479,7 +479,7 @@ int iris_set_profile(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap_ =20 int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type = cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_id, hfi_value; =20 if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { @@ -499,7 +499,7 @@ int iris_set_level(struct iris_inst *inst, enum platfor= m_inst_fw_cap_type cap_id =20 int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst= _fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; struct hfi_profile_level pl; =20 @@ -520,7 +520,7 @@ int iris_set_profile_level_gen1(struct iris_inst *inst,= enum platform_inst_fw_ca =20 int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_f= w_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 header_mode =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -539,7 +539,7 @@ int iris_set_header_mode_gen1(struct iris_inst *inst, e= num platform_inst_fw_cap_ =20 int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_f= w_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 prepend_sps_pps =3D inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; u32 header_mode =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; @@ -561,7 +561,7 @@ int iris_set_header_mode_gen2(struct iris_inst *inst, e= num platform_inst_fw_cap_ =20 int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 entropy_mode =3D inst->fw_caps[ENTROPY_MODE].value; u32 bitrate =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; @@ -586,7 +586,7 @@ int iris_set_bitrate(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap_ =20 int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_ca= p_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 rc_mode =3D inst->fw_caps[BITRATE_MODE].value; u32 peak_bitrate =3D inst->fw_caps[cap_id].value; u32 bitrate =3D inst->fw_caps[BITRATE].value; @@ -613,7 +613,7 @@ int iris_set_peak_bitrate(struct iris_inst *inst, enum = platform_inst_fw_cap_type =20 int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; u32 frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip =3D inst->fw_caps[FRAME_SKIP_MODE].value; @@ -640,7 +640,7 @@ int iris_set_bitrate_mode_gen1(struct iris_inst *inst, = enum platform_inst_fw_cap =20 int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; u32 frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; u32 frame_skip =3D inst->fw_caps[FRAME_SKIP_MODE].value; @@ -667,7 +667,7 @@ int iris_set_bitrate_mode_gen2(struct iris_inst *inst, = enum platform_inst_fw_cap =20 int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 entropy_mode =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; u32 hfi_val; @@ -687,7 +687,7 @@ int iris_set_entropy_mode_gen1(struct iris_inst *inst, = enum platform_inst_fw_cap =20 int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 entropy_mode =3D inst->fw_caps[cap_id].value; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; u32 profile; @@ -712,7 +712,7 @@ int iris_set_entropy_mode_gen2(struct iris_inst *inst, = enum platform_inst_fw_cap =20 int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0; u32 i_frame_qp =3D 0, p_frame_qp =3D 0, b_frame_qp =3D 0; u32 min_qp_enable =3D 0, client_qp_enable =3D 0; @@ -776,7 +776,7 @@ int iris_set_min_qp(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_i =20 int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0; u32 max_qp_enable =3D 0, client_qp_enable; u32 i_frame_qp, p_frame_qp, b_frame_qp; @@ -841,7 +841,7 @@ int iris_set_max_qp(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_i =20 int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0, client_qp_en= able; u32 i_frame_qp, p_frame_qp, b_frame_qp; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; @@ -902,7 +902,7 @@ int iris_set_frame_qp(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap =20 int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; struct hfi_quantization_range_v2 range; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; =20 @@ -923,7 +923,7 @@ int iris_set_qp_range(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap =20 int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; u32 hfi_val; =20 @@ -953,7 +953,7 @@ int iris_set_rotation(struct iris_inst *inst, enum plat= form_inst_fw_cap_type cap =20 int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; u32 hfi_val =3D HFI_DISABLE_FLIP; =20 @@ -972,7 +972,7 @@ int iris_set_flip(struct iris_inst *inst, enum platform= _inst_fw_cap_type cap_id) =20 int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_t= ype cap_id) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; struct vb2_queue *q =3D v4l2_m2m_get_dst_vq(inst->m2m_ctx); u32 ir_period =3D inst->fw_caps[cap_id].value; u32 ir_type =3D 0; @@ -998,7 +998,7 @@ int iris_set_ir_period(struct iris_inst *inst, enum pla= tform_inst_fw_cap_type ca =20 int iris_set_properties(struct iris_inst *inst, u32 plane) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; struct platform_inst_fw_cap *cap; int ret; u32 i; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index 3edb5ae582b4..18684ada78b2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -110,6 +110,9 @@ struct iris_hfi_command_ops { int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); +}; + +struct iris_hfi_session_ops { int (*session_set_config_params)(struct iris_inst *inst, u32 plane); int (*session_set_property)(struct iris_inst *inst, u32 packet_type, u32 flag, u32 plane, u32 payload_type, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index e42d17653c2c..a28b0c7ebbad 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1063,11 +1063,7 @@ static int iris_hfi_gen1_session_set_config_params(s= truct iris_inst *inst, u32 p return 0; } =20 -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops =3D { - .sys_init =3D iris_hfi_gen1_sys_init, - .sys_image_version =3D iris_hfi_gen1_sys_image_version, - .sys_interframe_powercollapse =3D iris_hfi_gen1_sys_interframe_powercolla= pse, - .sys_pc_prep =3D iris_hfi_gen1_sys_pc_prep, +static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops =3D { .session_open =3D iris_hfi_gen1_session_open, .session_set_config_params =3D iris_hfi_gen1_session_set_config_params, .session_set_property =3D iris_hfi_gen1_session_set_property, @@ -1080,6 +1076,13 @@ static const struct iris_hfi_command_ops iris_hfi_ge= n1_command_ops =3D { .session_close =3D iris_hfi_gen1_session_close, }; =20 +static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops =3D { + .sys_init =3D iris_hfi_gen1_sys_init, + .sys_image_version =3D iris_hfi_gen1_sys_image_version, + .sys_interframe_powercollapse =3D iris_hfi_gen1_sys_interframe_powercolla= pse, + .sys_pc_prep =3D iris_hfi_gen1_sys_pc_prep, +}; + void iris_hfi_gen1_command_ops_init(struct iris_core *core) { core->hfi_ops =3D &iris_hfi_gen1_command_ops; @@ -1087,5 +1090,13 @@ void iris_hfi_gen1_command_ops_init(struct iris_core= *core) =20 struct iris_inst *iris_hfi_gen1_get_instance(void) { - return kzalloc_obj(struct iris_inst); + struct iris_inst *out; + + out =3D kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops =3D &iris_hfi_gen1_session_ops; + + return out; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index e4f25b7f5d04..ffb70fd9499c 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1300,11 +1300,7 @@ static int iris_hfi_gen2_session_release_buffer(stru= ct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } =20 -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops =3D { - .sys_init =3D iris_hfi_gen2_sys_init, - .sys_image_version =3D iris_hfi_gen2_sys_image_version, - .sys_interframe_powercollapse =3D iris_hfi_gen2_sys_interframe_powercolla= pse, - .sys_pc_prep =3D iris_hfi_gen2_sys_pc_prep, +static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops =3D { .session_open =3D iris_hfi_gen2_session_open, .session_set_config_params =3D iris_hfi_gen2_session_set_config_params, .session_set_property =3D iris_hfi_gen2_session_set_property, @@ -1319,6 +1315,13 @@ static const struct iris_hfi_command_ops iris_hfi_ge= n2_command_ops =3D { .session_close =3D iris_hfi_gen2_session_close, }; =20 +static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops =3D { + .sys_init =3D iris_hfi_gen2_sys_init, + .sys_image_version =3D iris_hfi_gen2_sys_image_version, + .sys_interframe_powercollapse =3D iris_hfi_gen2_sys_interframe_powercolla= pse, + .sys_pc_prep =3D iris_hfi_gen2_sys_pc_prep, +}; + void iris_hfi_gen2_command_ops_init(struct iris_core *core) { core->hfi_ops =3D &iris_hfi_gen2_command_ops; @@ -1330,6 +1333,10 @@ struct iris_inst *iris_hfi_gen2_get_instance(void) =20 /* The allocation is intentionally larger than struct iris_inst. */ out =3D kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops =3D &iris_hfi_gen2_session_ops; =20 return &out->inst; } diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 16965150f427..352af99699dd 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -15,6 +15,8 @@ #define DEFAULT_WIDTH 320 #define DEFAULT_HEIGHT 240 =20 +struct iris_hfi_session_ops; + enum iris_fmt_type_out { IRIS_FMT_H264, IRIS_FMT_HEVC, @@ -38,6 +40,7 @@ struct iris_fmt { * @list: used for attach an instance to the core * @core: pointer to core structure * @session_id: id of current video session + * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls * @lock: lock to seralise forward and reverse threads * @fh: reference of v4l2 file handler @@ -80,6 +83,7 @@ struct iris_inst { struct list_head list; struct iris_core *core; u32 session_id; + const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ struct mutex lock; /* lock to serialize forward and reverse threads */ struct v4l2_fh fh; diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index bf0b8400996e..a2ea2d67f60d 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -129,7 +129,7 @@ int iris_vb2_queue_setup(struct vb2_queue *q, if (!inst->once_per_session_set) { inst->once_per_session_set =3D true; =20 - ret =3D core->hfi_ops->session_open(inst); + ret =3D inst->hfi_session_ops->session_open(inst); if (ret) { ret =3D -EINVAL; dev_err(core->dev, "session open failed\n"); diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 719217399a30..ccda3b9fb845 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -374,7 +374,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) =20 int iris_vdec_streamon_output(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; int ret; =20 ret =3D hfi_ops->session_set_config_params(inst, V4L2_BUF_TYPE_VIDEO_CAPT= URE_MPLANE); @@ -434,7 +434,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v= 4l2_buffer *vbuf) =20 int iris_vdec_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state =3D 0; struct vb2_queue *dst_vq; int ret; @@ -497,7 +497,7 @@ int iris_vdec_start_cmd(struct iris_inst *inst) =20 int iris_vdec_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; int ret; =20 ret =3D hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index aa27b22704eb..aeed756ee9ca 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -581,7 +581,7 @@ int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v= 4l2_buffer *vbuf) =20 int iris_venc_start_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; enum iris_inst_sub_state clear_sub_state =3D 0; struct vb2_queue *dst_vq; int ret; @@ -623,7 +623,7 @@ int iris_venc_start_cmd(struct iris_inst *inst) =20 int iris_venc_stop_cmd(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; int ret; =20 ret =3D hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index bd38d84c9cc7..7e03d63578e1 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -224,7 +224,7 @@ int iris_open(struct file *filp) =20 static void iris_session_close(struct iris_inst *inst) { - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; 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Merge both of them into the new iris_hfi_ops structure. Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_core.h | 6 ++---- drivers/media/platform/qcom/iris/iris_hfi_common.c | 6 +++--- drivers/media/platform/qcom/iris/iris_hfi_common.h | 8 +++----- drivers/media/platform/qcom/iris/iris_hfi_gen1.h | 4 ++-- drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c | 8 +++++--- drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c | 11 +---------- drivers/media/platform/qcom/iris/iris_hfi_gen2.h | 4 ++-- drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c | 8 +++++--- drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c | 11 +---------- drivers/media/platform/qcom/iris/iris_platform_common.h | 3 +-- drivers/media/platform/qcom/iris/iris_platform_gen1.c | 6 ++---- drivers/media/platform/qcom/iris/iris_platform_gen2.c | 12 ++++-------- drivers/media/platform/qcom/iris/iris_probe.c | 3 +-- drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +- 14 files changed, 33 insertions(+), 59 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index d10a03aa5685..1592681640ab 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -68,8 +68,7 @@ struct qcom_ubwc_cfg_data; * @header_id: id of packet header * @packet_id: id of packet * @power: a structure for clock and bw information - * @hfi_ops: iris hfi command ops - * @hfi_response_ops: iris hfi response ops + * @hfi_sys_ops: iris HFI system ops * @core_init_done: structure of signal completion for system response * @intr_status: interrupt status * @sys_error_handler: a delayed work for handling system fatal error @@ -112,8 +111,7 @@ struct iris_core { u32 header_id; u32 packet_id; struct iris_core_power power; - const struct iris_hfi_command_ops *hfi_ops; - const struct iris_hfi_response_ops *hfi_response_ops; + const struct iris_hfi_sys_ops *hfi_sys_ops; struct completion core_init_done; u32 intr_status; struct delayed_work sys_error_handler; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.c index 92112eb16c11..ad8e4ecb8605 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c @@ -76,7 +76,7 @@ u32 iris_hfi_get_v4l2_matrix_coefficients(u32 hfi_coeffic= ients) =20 int iris_hfi_core_init(struct iris_core *core) { - const struct iris_hfi_command_ops *hfi_ops =3D core->hfi_ops; + const struct iris_hfi_sys_ops *hfi_ops =3D core->hfi_sys_ops; int ret; =20 ret =3D hfi_ops->sys_init(core); @@ -109,7 +109,7 @@ irqreturn_t iris_hfi_isr_handler(int irq, void *data) iris_vpu_clear_interrupt(core); mutex_unlock(&core->lock); =20 - core->hfi_response_ops->hfi_response_handler(core); + core->hfi_sys_ops->sys_hfi_response_handler(core); =20 if (!iris_vpu_watchdog(core, core->intr_status)) enable_irq(irq); @@ -144,7 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core) =20 int iris_hfi_pm_resume(struct iris_core *core) { - const struct iris_hfi_command_ops *ops =3D core->hfi_ops; + const struct iris_hfi_sys_ops *ops =3D core->hfi_sys_ops; int ret; =20 ret =3D iris_vpu_power_on(core); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index 18684ada78b2..9aa84a1d8f95 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -105,11 +105,13 @@ struct iris_hfi_prop_type_handle { int (*handle)(struct iris_inst *inst, u32 plane); }; =20 -struct iris_hfi_command_ops { +struct iris_hfi_sys_ops { int (*sys_init)(struct iris_core *core); int (*sys_image_version)(struct iris_core *core); int (*sys_interframe_powercollapse)(struct iris_core *core); int (*sys_pc_prep)(struct iris_core *core); + + void (*sys_hfi_response_handler)(struct iris_core *core); }; =20 struct iris_hfi_session_ops { @@ -129,10 +131,6 @@ struct iris_hfi_session_ops { int (*session_close)(struct iris_inst *inst); }; =20 -struct iris_hfi_response_ops { - void (*hfi_response_handler)(struct iris_core *core); -}; - struct hfi_subscription_params { u32 bitstream_resolution; u32 crop_offsets[2]; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen1.h index 19b8e9054a75..38e9d262d7df 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -9,8 +9,8 @@ struct iris_core; struct iris_inst; =20 -void iris_hfi_gen1_command_ops_init(struct iris_core *core); -void iris_hfi_gen1_response_ops_init(struct iris_core *core); +void iris_hfi_gen1_sys_ops_init(struct iris_core *core); +void iris_hfi_gen1_response_handler(struct iris_core *core); struct iris_inst *iris_hfi_gen1_get_instance(void); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index a28b0c7ebbad..26b7feb05d15 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,16 +1076,18 @@ static const struct iris_hfi_session_ops iris_hfi_g= en1_session_ops =3D { .session_close =3D iris_hfi_gen1_session_close, }; =20 -static const struct iris_hfi_command_ops iris_hfi_gen1_command_ops =3D { +static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops =3D { .sys_init =3D iris_hfi_gen1_sys_init, .sys_image_version =3D iris_hfi_gen1_sys_image_version, .sys_interframe_powercollapse =3D iris_hfi_gen1_sys_interframe_powercolla= pse, .sys_pc_prep =3D iris_hfi_gen1_sys_pc_prep, + + .sys_hfi_response_handler =3D iris_hfi_gen1_response_handler, }; =20 -void iris_hfi_gen1_command_ops_init(struct iris_core *core) +void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { - core->hfi_ops =3D &iris_hfi_gen1_command_ops; + core->hfi_sys_ops =3D &iris_hfi_gen1_sys_ops; } =20 struct iris_inst *iris_hfi_gen1_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 8e864c239e29..bfd7495bf44f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -688,7 +688,7 @@ static void iris_hfi_gen1_flush_debug_queue(struct iris= _core *core, u8 *packet) } } =20 -static void iris_hfi_gen1_response_handler(struct iris_core *core) +void iris_hfi_gen1_response_handler(struct iris_core *core) { memset(core->response_packet, 0, sizeof(struct hfi_pkt_hdr)); while (!iris_hfi_queue_msg_read(core, core->response_packet)) { @@ -698,12 +698,3 @@ static void iris_hfi_gen1_response_handler(struct iris= _core *core) =20 iris_hfi_gen1_flush_debug_queue(core, core->response_packet); } - -static const struct iris_hfi_response_ops iris_hfi_gen1_response_ops =3D { - .hfi_response_handler =3D iris_hfi_gen1_response_handler, -}; - -void iris_hfi_gen1_response_ops_init(struct iris_core *core) -{ - core->hfi_response_ops =3D &iris_hfi_gen1_response_ops; -} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen2.h index b9d3749a10ef..6cc6d9890c12 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -34,8 +34,8 @@ struct iris_inst_hfi_gen2 { struct hfi_subscription_params dst_subcr_params; }; =20 -void iris_hfi_gen2_command_ops_init(struct iris_core *core); -void iris_hfi_gen2_response_ops_init(struct iris_core *core); +void iris_hfi_gen2_sys_ops_init(struct iris_core *core); +void iris_hfi_gen2_response_handler(struct iris_core *core); struct iris_inst *iris_hfi_gen2_get_instance(void); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index ffb70fd9499c..0c98d680bf09 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1315,16 +1315,18 @@ static const struct iris_hfi_session_ops iris_hfi_g= en2_session_ops =3D { .session_close =3D iris_hfi_gen2_session_close, }; =20 -static const struct iris_hfi_command_ops iris_hfi_gen2_command_ops =3D { +static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops =3D { .sys_init =3D iris_hfi_gen2_sys_init, .sys_image_version =3D iris_hfi_gen2_sys_image_version, .sys_interframe_powercollapse =3D iris_hfi_gen2_sys_interframe_powercolla= pse, .sys_pc_prep =3D iris_hfi_gen2_sys_pc_prep, + + .sys_hfi_response_handler =3D iris_hfi_gen2_response_handler, }; =20 -void iris_hfi_gen2_command_ops_init(struct iris_core *core) +void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { - core->hfi_ops =3D &iris_hfi_gen2_command_ops; + core->hfi_sys_ops =3D &iris_hfi_gen2_sys_ops; } =20 struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 8e19f61bbbf9..c350d231265e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -977,7 +977,7 @@ static void iris_hfi_gen2_flush_debug_queue(struct iris= _core *core, u8 *packet) } } =20 -static void iris_hfi_gen2_response_handler(struct iris_core *core) +void iris_hfi_gen2_response_handler(struct iris_core *core) { if (iris_vpu_watchdog(core, core->intr_status)) { struct iris_hfi_packet pkt =3D {.type =3D HFI_SYS_ERROR_WD_TIMEOUT}; @@ -997,12 +997,3 @@ static void iris_hfi_gen2_response_handler(struct iris= _core *core) =20 iris_hfi_gen2_flush_debug_queue(core, core->response_packet); } - -static const struct iris_hfi_response_ops iris_hfi_gen2_response_ops =3D { - .hfi_response_handler =3D iris_hfi_gen2_response_handler, -}; - -void iris_hfi_gen2_response_ops_init(struct iris_core *core) -{ - core->hfi_response_ops =3D &iris_hfi_gen2_response_ops; -} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index d7106902698c..6b76a9046f9a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -202,8 +202,7 @@ enum platform_pm_domain_type { }; =20 struct iris_platform_data { - void (*init_hfi_command_ops)(struct iris_core *core); - void (*init_hfi_response_ops)(struct iris_core *core); + void (*init_hfi_ops)(struct iris_core *core); struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); const struct vpu_ops *vpu_ops; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index ed07d1b00e43..dc74da04771b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -334,8 +334,7 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { =20 const struct iris_platform_data sm8250_data =3D { .get_instance =3D iris_hfi_gen1_get_instance, - .init_hfi_command_ops =3D &iris_hfi_gen1_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, + .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, @@ -387,8 +386,7 @@ const struct iris_platform_data sm8250_data =3D { =20 const struct iris_platform_data sc7280_data =3D { .get_instance =3D iris_hfi_gen1_get_instance, - .init_hfi_command_ops =3D &iris_hfi_gen1_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen1_response_ops_init, + .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index c84d4399f84d..19e99e1c2aff 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -908,8 +908,7 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { =20 const struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, - .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D sm8550_icc_table, @@ -1008,8 +1007,7 @@ const struct iris_platform_data sm8550_data =3D { */ const struct iris_platform_data sm8650_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, - .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu33_ops, .icc_tbl =3D sm8550_icc_table, @@ -1103,8 +1101,7 @@ const struct iris_platform_data sm8650_data =3D { =20 const struct iris_platform_data sm8750_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, - .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu35_ops, .icc_tbl =3D sm8550_icc_table, @@ -1200,8 +1197,7 @@ const struct iris_platform_data sm8750_data =3D { */ const struct iris_platform_data qcs8300_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, - .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D sm8550_icc_table, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index baa13cc5c209..fa561f6a736c 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -264,8 +264,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); 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Move it into the new iris_hfi_sys_ops structure, merging all core callbacks into a single vtable. Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_hfi_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_hfi_gen1.h | 2 -- .../platform/qcom/iris/iris_hfi_gen1_command.c | 28 ++++++++++--------= -- drivers/media/platform/qcom/iris/iris_hfi_gen2.h | 1 - .../platform/qcom/iris/iris_hfi_gen2_command.c | 30 ++++++++++++------= ---- .../platform/qcom/iris/iris_platform_common.h | 1 - .../media/platform/qcom/iris/iris_platform_gen1.c | 2 -- .../media/platform/qcom/iris/iris_platform_gen2.c | 4 --- drivers/media/platform/qcom/iris/iris_vidc.c | 2 +- 9 files changed, 34 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index 9aa84a1d8f95..a27447eb2519 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -112,6 +112,8 @@ struct iris_hfi_sys_ops { int (*sys_pc_prep)(struct iris_core *core); =20 void (*sys_hfi_response_handler)(struct iris_core *core); + + struct iris_inst *(*sys_get_instance)(void); }; =20 struct iris_hfi_session_ops { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen1.h index 38e9d262d7df..c37adf65055a 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.h @@ -7,10 +7,8 @@ #define __IRIS_HFI_GEN1_H__ =20 struct iris_core; -struct iris_inst; =20 void iris_hfi_gen1_sys_ops_init(struct iris_core *core); void iris_hfi_gen1_response_handler(struct iris_core *core); -struct iris_inst *iris_hfi_gen1_get_instance(void); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 26b7feb05d15..0017ade4adbd 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1076,6 +1076,19 @@ static const struct iris_hfi_session_ops iris_hfi_ge= n1_session_ops =3D { .session_close =3D iris_hfi_gen1_session_close, }; =20 +static struct iris_inst *iris_hfi_gen1_get_instance(void) +{ + struct iris_inst *out; + + out =3D kzalloc_obj(*out); + if (!out) + return NULL; + + out->hfi_session_ops =3D &iris_hfi_gen1_session_ops; + + return out; +} + static const struct iris_hfi_sys_ops iris_hfi_gen1_sys_ops =3D { .sys_init =3D iris_hfi_gen1_sys_init, .sys_image_version =3D iris_hfi_gen1_sys_image_version, @@ -1083,22 +1096,11 @@ static const struct iris_hfi_sys_ops iris_hfi_gen1_= sys_ops =3D { .sys_pc_prep =3D iris_hfi_gen1_sys_pc_prep, =20 .sys_hfi_response_handler =3D iris_hfi_gen1_response_handler, + + .sys_get_instance =3D iris_hfi_gen1_get_instance, }; =20 void iris_hfi_gen1_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops =3D &iris_hfi_gen1_sys_ops; } - -struct iris_inst *iris_hfi_gen1_get_instance(void) -{ - struct iris_inst *out; - - out =3D kzalloc_obj(*out); - if (!out) - return NULL; - - out->hfi_session_ops =3D &iris_hfi_gen1_session_ops; - - return out; -} diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h b/drivers/med= ia/platform/qcom/iris/iris_hfi_gen2.h index 6cc6d9890c12..21ab58e0aa84 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.h @@ -36,6 +36,5 @@ struct iris_inst_hfi_gen2 { =20 void iris_hfi_gen2_sys_ops_init(struct iris_core *core); void iris_hfi_gen2_response_handler(struct iris_core *core); -struct iris_inst *iris_hfi_gen2_get_instance(void); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 0c98d680bf09..639b75fca1ab 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1315,6 +1315,20 @@ static const struct iris_hfi_session_ops iris_hfi_ge= n2_session_ops =3D { .session_close =3D iris_hfi_gen2_session_close, }; =20 +static struct iris_inst *iris_hfi_gen2_get_instance(void) +{ + struct iris_inst_hfi_gen2 *out; + + /* The allocation is intentionally larger than struct iris_inst. */ + out =3D kzalloc_obj(*out); + if (!out) + return NULL; + + out->inst.hfi_session_ops =3D &iris_hfi_gen2_session_ops; + + return &out->inst; +} + static const struct iris_hfi_sys_ops iris_hfi_gen2_sys_ops =3D { .sys_init =3D iris_hfi_gen2_sys_init, .sys_image_version =3D iris_hfi_gen2_sys_image_version, @@ -1322,23 +1336,11 @@ static const struct iris_hfi_sys_ops iris_hfi_gen2_= sys_ops =3D { .sys_pc_prep =3D iris_hfi_gen2_sys_pc_prep, =20 .sys_hfi_response_handler =3D iris_hfi_gen2_response_handler, + + .sys_get_instance =3D iris_hfi_gen2_get_instance, }; =20 void iris_hfi_gen2_sys_ops_init(struct iris_core *core) { core->hfi_sys_ops =3D &iris_hfi_gen2_sys_ops; } - -struct iris_inst *iris_hfi_gen2_get_instance(void) -{ - struct iris_inst_hfi_gen2 *out; - - /* The allocation is intentionally larger than struct iris_inst. */ - out =3D kzalloc_obj(*out); - if (!out) - return NULL; - - out->inst.hfi_session_ops =3D &iris_hfi_gen2_session_ops; - - return &out->inst; -} diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 6b76a9046f9a..d1daef2d874b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -203,7 +203,6 @@ enum platform_pm_domain_type { =20 struct iris_platform_data { void (*init_hfi_ops)(struct iris_core *core); - struct iris_inst *(*get_instance)(void); u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); const struct vpu_ops *vpu_ops; const struct icc_info *icc_tbl; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index dc74da04771b..9925a893b404 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -333,7 +333,6 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { }; =20 const struct iris_platform_data sm8250_data =3D { - .get_instance =3D iris_hfi_gen1_get_instance, .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, @@ -385,7 +384,6 @@ const struct iris_platform_data sm8250_data =3D { }; =20 const struct iris_platform_data sc7280_data =3D { - .get_instance =3D iris_hfi_gen1_get_instance, .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 19e99e1c2aff..10a972f96cbe 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -907,7 +907,6 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { }; =20 const struct iris_platform_data sm8550_data =3D { - .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, @@ -1006,7 +1005,6 @@ const struct iris_platform_data sm8550_data =3D { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data =3D { - .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu33_ops, @@ -1100,7 +1098,6 @@ const struct iris_platform_data sm8650_data =3D { }; =20 const struct iris_platform_data sm8750_data =3D { - .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu35_ops, @@ -1196,7 +1193,6 @@ const struct iris_platform_data sm8750_data =3D { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { - .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 7e03d63578e1..ecd8a20fedbf 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -156,7 +156,7 @@ int iris_open(struct file *filp) =20 pm_runtime_put_sync(core->dev); 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For example, SM8450 uses Gen2 firmware, so currently its platform data should be placed next to the other gen2 platforms, although it has the VPU2.0 core, similar to the one found on SM8250 and SC7280 and so the hardware-specific platform data is also close to those devices. Split firmware data to a separate struct, separating hardware-related data from the firmware interfaces. Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_buffer.c | 84 +++---- drivers/media/platform/qcom/iris/iris_core.h | 2 + drivers/media/platform/qcom/iris/iris_ctrls.c | 8 +- .../platform/qcom/iris/iris_hfi_gen1_command.c | 10 +- .../platform/qcom/iris/iris_hfi_gen2_command.c | 66 ++--- .../platform/qcom/iris/iris_platform_common.h | 79 +++--- .../media/platform/qcom/iris/iris_platform_gen1.c | 68 +++--- .../media/platform/qcom/iris/iris_platform_gen2.c | 268 +++++++----------= ---- drivers/media/platform/qcom/iris/iris_probe.c | 3 +- drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- 10 files changed, 247 insertions(+), 351 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index f55b7c608116..22596fc6d02f 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -295,37 +295,37 @@ static void iris_fill_internal_buf_info(struct iris_i= nst *inst, { struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; =20 - buffers->size =3D inst->core->iris_platform_data->get_vpu_buffer_size(ins= t, buffer_type); + buffers->size =3D inst->core->iris_firmware_data->get_vpu_buffer_size(ins= t, buffer_type); buffers->min_count =3D iris_vpu_buf_count(inst, buffer_type); } =20 void iris_get_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } @@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst= *inst, =20 int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; u32 internal_buffer_count, i, j; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *in= st, u32 plane) =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_in= st *inst, enum iris_buffe =20 int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buffer, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *ins= t, u32 plane) =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst= , struct iris_buffer *buf =20 static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane= , bool force) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_= inst *inst, u32 plane, bool =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - len =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + len =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - len =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + len =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - len =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + len =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - len =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + len =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -593,17 +593,17 @@ static int iris_release_internal_buffers(struct iris_= inst *inst, =20 static int iris_release_input_internal_buffers(struct iris_inst *inst) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; int ret; =20 if (inst->domain =3D=3D DECODER) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } =20 for (i =3D 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 1592681640ab..e0ca245c8c63 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -54,6 +54,7 @@ struct qcom_ubwc_cfg_data; * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data + * @iris_firmware_data: a pointer to the firmware (or HFI) specific data * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory @@ -97,6 +98,7 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; + const struct iris_firmware_data *iris_firmware_data; const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 5a24aa869b2d..ef7adac3764d 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core) const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; =20 - caps =3D core->iris_platform_data->inst_fw_caps_dec; - num_cap =3D core->iris_platform_data->inst_fw_caps_dec_size; + caps =3D core->iris_firmware_data->inst_fw_caps_dec; + num_cap =3D core->iris_firmware_data->inst_fw_caps_dec_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; @@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core) } } =20 - caps =3D core->iris_platform_data->inst_fw_caps_enc; - num_cap =3D core->iris_platform_data->inst_fw_caps_enc_size; + caps =3D core->iris_firmware_data->inst_fw_caps_enc; + num_cap =3D core->iris_firmware_data->inst_fw_caps_enc_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 0017ade4adbd..fd491ad75d00 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -918,7 +918,7 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *= inst, u32 plane) =20 if (iris_split_mode_enabled(inst)) { bufsz.type =3D HFI_BUFFER_OUTPUT; - bufsz.size =3D inst->core->iris_platform_data->get_vpu_buffer_size(inst,= BUF_DPB); + bufsz.size =3D inst->core->iris_firmware_data->get_vpu_buffer_size(inst,= BUF_DPB); =20 ret =3D hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz)); if (ret) @@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p }; =20 if (inst->domain =3D=3D DECODER) { - config_params =3D core->iris_platform_data->dec_input_config_params_defa= ult; - config_params_size =3D core->iris_platform_data->dec_input_config_params= _default_size; + config_params =3D core->iris_firmware_data->dec_input_config_params_defa= ult; + config_params_size =3D core->iris_firmware_data->dec_input_config_params= _default_size; if (V4L2_TYPE_IS_OUTPUT(plane)) { handler =3D vdec_prop_type_handle_inp_arr; handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_inp_arr); @@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_out_arr); } } else { - config_params =3D core->iris_platform_data->enc_input_config_params; - config_params_size =3D core->iris_platform_data->enc_input_config_params= _size; + config_params =3D core->iris_firmware_data->enc_input_config_params; + config_params_size =3D core->iris_firmware_data->enc_input_config_params= _size; handler =3D venc_prop_type_handle_inp_arr; handler_size =3D ARRAY_SIZE(venc_prop_type_handle_inp_arr); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 639b75fca1ab..c90b22a75bc5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -601,7 +601,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_in= st *inst, u32 plane) =20 static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { - const struct iris_platform_data *pdata =3D inst->core->iris_platform_data; + const struct iris_firmware_data *fdata =3D inst->core->iris_firmware_data; u32 config_params_size =3D 0, i, j; const u32 *config_params =3D NULL; int ret; @@ -630,31 +630,31 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - config_params =3D pdata->dec_input_config_params_default; - config_params_size =3D pdata->dec_input_config_params_default_size; + config_params =3D fdata->dec_input_config_params_default; + config_params_size =3D fdata->dec_input_config_params_default_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { - config_params =3D pdata->dec_input_config_params_hevc; - config_params_size =3D pdata->dec_input_config_params_hevc_size; + config_params =3D fdata->dec_input_config_params_hevc; + config_params_size =3D fdata->dec_input_config_params_hevc_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) { - config_params =3D pdata->dec_input_config_params_vp9; - config_params_size =3D pdata->dec_input_config_params_vp9_size; + config_params =3D fdata->dec_input_config_params_vp9; + config_params_size =3D fdata->dec_input_config_params_vp9_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { - config_params =3D pdata->dec_input_config_params_av1; - config_params_size =3D pdata->dec_input_config_params_av1_size; + config_params =3D fdata->dec_input_config_params_av1; + config_params_size =3D fdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params =3D pdata->dec_output_config_params; - config_params_size =3D pdata->dec_output_config_params_size; + config_params =3D fdata->dec_output_config_params; + config_params_size =3D fdata->dec_output_config_params_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params =3D pdata->enc_input_config_params; - config_params_size =3D pdata->enc_input_config_params_size; + config_params =3D fdata->enc_input_config_params; + config_params_size =3D fdata->enc_input_config_params_size; } else { - config_params =3D pdata->enc_output_config_params; - config_params_size =3D pdata->enc_output_config_params_size; + config_params =3D fdata->enc_output_config_params; + config_params_size =3D fdata->enc_output_config_params_size; } } =20 @@ -849,24 +849,24 @@ static int iris_hfi_gen2_subscribe_change_param(struc= t iris_inst *inst, u32 plan =20 switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param =3D core->iris_platform_data->dec_input_config_params_defau= lt; + change_param =3D core->iris_firmware_data->dec_input_config_params_defau= lt; change_param_size =3D - core->iris_platform_data->dec_input_config_params_default_size; + core->iris_firmware_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param =3D core->iris_platform_data->dec_input_config_params_hevc; + change_param =3D core->iris_firmware_data->dec_input_config_params_hevc; change_param_size =3D - core->iris_platform_data->dec_input_config_params_hevc_size; + core->iris_firmware_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param =3D core->iris_platform_data->dec_input_config_params_vp9; + change_param =3D core->iris_firmware_data->dec_input_config_params_vp9; change_param_size =3D - core->iris_platform_data->dec_input_config_params_vp9_size; + core->iris_firmware_data->dec_input_config_params_vp9_size; break; case V4L2_PIX_FMT_AV1: - change_param =3D core->iris_platform_data->dec_input_config_params_av1; + change_param =3D core->iris_firmware_data->dec_input_config_params_av1; change_param_size =3D - core->iris_platform_data->dec_input_config_params_av1_size; + core->iris_firmware_data->dec_input_config_params_av1_size; break; } =20 @@ -996,29 +996,29 @@ static int iris_hfi_gen2_subscribe_property(struct ir= is_inst *inst, u32 plane) return 0; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { - subscribe_prop_size =3D core->iris_platform_data->dec_input_prop_size; - subcribe_prop =3D core->iris_platform_data->dec_input_prop; + subscribe_prop_size =3D core->iris_firmware_data->dec_input_prop_size; + subcribe_prop =3D core->iris_firmware_data->dec_input_prop; } else { switch (inst->codec) { case V4L2_PIX_FMT_H264: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_avc; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_avc; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_avc_size; + core->iris_firmware_data->dec_output_prop_avc_size; break; case V4L2_PIX_FMT_HEVC: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_hevc; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_hevc; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_hevc_size; + core->iris_firmware_data->dec_output_prop_hevc_size; break; case V4L2_PIX_FMT_VP9: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_vp9; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_vp9; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_vp9_size; + core->iris_firmware_data->dec_output_prop_vp9_size; break; case V4L2_PIX_FMT_AV1: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_av1; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_av1; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_av1_size; + core->iris_firmware_data->dec_output_prop_av1_size; break; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index d1daef2d874b..1a870fec4f31 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -201,45 +201,16 @@ enum platform_pm_domain_type { IRIS_APV_HW_POWER_DOMAIN, }; =20 -struct iris_platform_data { +struct iris_firmware_data { void (*init_hfi_ops)(struct iris_core *core); + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); - const struct vpu_ops *vpu_ops; - const struct icc_info *icc_tbl; - unsigned int icc_tbl_size; - const struct bw_info *bw_tbl_dec; - unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; - const char * const *opp_pd_tbl; - unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; - const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; - const char * const *clk_rst_tbl; - unsigned int clk_rst_tbl_size; - const char * const *controller_rst_tbl; - unsigned int controller_rst_tbl_size; - u64 dma_mask; - const char *fwname; - struct iris_fmt *inst_iris_fmts; - u32 inst_iris_fmts_size; - struct platform_inst_caps *inst_caps; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - const struct tz_cp_config *tz_cp_config_data; - u32 tz_cp_config_data_size; - u32 core_arch; - u32 hw_response_timeout; - u32 num_vpp_pipe; - bool no_aon; - u32 max_session_count; - /* max number of macroblocks per frame supported */ - u32 max_core_mbpf; - /* max number of macroblocks per second supported */ - u32 max_core_mbps; + const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -254,6 +225,7 @@ struct iris_platform_data { unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; unsigned int enc_output_config_params_size; + const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; @@ -264,6 +236,7 @@ struct iris_platform_data { unsigned int dec_output_prop_vp9_size; const u32 *dec_output_prop_av1; unsigned int dec_output_prop_av1_size; + const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; @@ -274,4 +247,44 @@ struct iris_platform_data { unsigned int enc_op_int_buf_tbl_size; }; =20 +struct iris_platform_data { + /* + * XXX: remove firmware_data pointer once we have platforms supporting + * both firmware kinds. + */ + const struct iris_firmware_data *firmware_data; + const struct vpu_ops *vpu_ops; + const struct icc_info *icc_tbl; + unsigned int icc_tbl_size; + const struct bw_info *bw_tbl_dec; + unsigned int bw_tbl_dec_size; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; + const char * const *opp_pd_tbl; + unsigned int opp_pd_tbl_size; + const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; + unsigned int clk_tbl_size; + const char * const *clk_rst_tbl; + unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; + u64 dma_mask; + const char *fwname; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; + struct platform_inst_caps *inst_caps; + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; + u32 core_arch; + u32 hw_response_timeout; + u32 num_vpp_pipe; + bool no_aon; + u32 max_session_count; + /* max number of macroblocks per frame supported */ + u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 9925a893b404..27f2ef04cffe 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -332,9 +332,34 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -const struct iris_platform_data sm8250_data =3D { +const struct iris_firmware_data iris_hfi_gen1_data =3D { .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, + + .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), + + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; + +const struct iris_platform_data sm8250_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), @@ -355,10 +380,6 @@ const struct iris_platform_data sm8250_data =3D { .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D tz_cp_config_sm8250, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, @@ -366,26 +387,10 @@ const struct iris_platform_data sm8250_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params =3D sm8250_venc_input_config_param, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; =20 const struct iris_platform_data sc7280_data =3D { - .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu_buf_size, + .firmware_data =3D &iris_hfi_gen1_data, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), @@ -404,10 +409,6 @@ const struct iris_platform_data sc7280_data =3D { .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D tz_cp_config_sm8250, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, @@ -417,19 +418,4 @@ const struct iris_platform_data sc7280_data =3D { .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ .max_core_mbps =3D 4096 * 2176 / 256 * 60, - .dec_input_config_params_default =3D - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params =3D sm8250_venc_input_config_param, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 10a972f96cbe..a83f6910f8b7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -906,41 +906,15 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -const struct iris_platform_data sm8550_data =3D { +const struct iris_firmware_data iris_hfi_gen2_data =3D { .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size =3D @@ -997,50 +971,15 @@ const struct iris_platform_data sm8550_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data =3D { +const struct iris_firmware_data iris_hfi_gen2_vpu33_data =3D { .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, - .vpu_ops =3D &iris_vpu33_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8650_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl =3D sm8650_controller_reset_table, - .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size =3D @@ -1097,9 +1036,81 @@ const struct iris_platform_data sm8650_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 +const struct iris_platform_data sm8550_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .vpu_ops =3D &iris_vpu33_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + const struct iris_platform_data sm8750_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu33_buf_size, + .firmware_data =3D &iris_hfi_gen2_vpu33_data, .vpu_ops =3D &iris_vpu35_ops, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), @@ -1120,10 +1131,6 @@ const struct iris_platform_data sm8750_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, @@ -1132,60 +1139,6 @@ const struct iris_platform_data sm8750_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 /* @@ -1193,8 +1146,7 @@ const struct iris_platform_data sm8750_data =3D { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu_buf_size, + .firmware_data =3D &iris_hfi_gen2_data, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), @@ -1215,10 +1167,6 @@ const struct iris_platform_data qcs8300_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_qcs8300, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, @@ -1227,58 +1175,4 @@ const struct iris_platform_data qcs8300_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index fa561f6a736c..dd87504c2e67 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -251,6 +251,7 @@ static int iris_probe(struct platform_device *pdev) return core->irq; =20 core->iris_platform_data =3D of_device_get_match_data(core->dev); + core->iris_firmware_data =3D core->iris_platform_data->firmware_data; =20 core->ubwc_cfg =3D qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) @@ -264,7 +265,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); =20 iris_init_ops(core); - core->iris_platform_data->init_hfi_ops(core); + core->iris_firmware_data->init_hfi_ops(core); =20 ret =3D iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index ecd8a20fedbf..807c9a20b6ba 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -243,7 +243,7 @@ static void iris_session_close(struct iris_inst *inst) =20 static void iris_check_num_queued_internal_buffers(struct iris_inst *inst,= u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; 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Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/Makefile | 6 +- .../iris/{iris_platform_gen1.c =3D> iris_hfi_gen1.c} | 134 ------------- .../iris/{iris_platform_gen2.c =3D> iris_hfi_gen2.c} | 219 ---------------= ------ .../platform/qcom/iris/iris_platform_common.h | 4 + .../platform/qcom/iris/iris_platform_sm8250.h | 29 +++ .../platform/qcom/iris/iris_platform_sm8550.h | 31 +++ .../media/platform/qcom/iris/iris_platform_vpu2.c | 124 ++++++++++++ .../media/platform/qcom/iris/iris_platform_vpu3.c | 210 +++++++++++++++++= +++ 8 files changed, 402 insertions(+), 355 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 2fde45f81727..67a12f42b3a6 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -4,14 +4,16 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_ctrls.o \ iris_firmware.o \ iris_hfi_common.o \ + iris_hfi_gen1.o \ iris_hfi_gen1_command.o \ iris_hfi_gen1_response.o \ + iris_hfi_gen2.o \ iris_hfi_gen2_command.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_gen1.o \ - iris_platform_gen2.o \ + iris_platform_vpu2.o \ + iris_platform_vpu3.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_hfi_gen1.c similarity index 67% rename from drivers/media/platform/qcom/iris/iris_platform_gen1.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen1.c index 27f2ef04cffe..18c97fa8a492 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c @@ -3,38 +3,16 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_platform_common.h" -#include "iris_resources.h" #include "iris_hfi_gen1.h" #include "iris_hfi_gen1_defines.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" -#include "iris_instance.h" - -#include "iris_platform_sc7280.h" =20 #define BITRATE_MIN 32000 #define BITRATE_MAX 160000000 -#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) #define BITRATE_STEP 100 =20 -static struct iris_fmt platform_fmts_sm8250_dec[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, @@ -248,56 +226,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8250_enc[] =3D { }, }; =20 -static struct platform_inst_caps platform_inst_cap_sm8250 =3D { - .min_frame_width =3D 128, - .max_frame_width =3D 8192, - .min_frame_height =3D 128, - .max_frame_height =3D 8192, - .max_mbpf =3D 138240, - .mb_cycles_vsp =3D 25, - .mb_cycles_vpp =3D 200, - .max_frame_rate =3D MAXIMUM_FPS, - .max_operating_rate =3D MAXIMUM_FPS, -}; - -static const struct icc_info sm8250_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8250_clk_reset_table[] =3D { "bus", "core" }; - -static const struct bw_info sm8250_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 2403000 }, - { ((4096 * 2160) / 256) * 30, 1224000 }, - { ((1920 * 1080) / 256) * 60, 812000 }, - { ((1920 * 1080) / 256) * 30, 416000 }, -}; - -static const char * const sm8250_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; - -static const struct platform_clk_data sm8250_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8250_opp_clk_table[] =3D { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8250[] =3D { - { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, - }, -}; - static const u32 sm8250_vdec_input_config_param_default[] =3D { HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -357,65 +285,3 @@ const struct iris_firmware_data iris_hfi_gen1_data =3D= { .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; - -const struct iris_platform_data sm8250_data =3D { - .firmware_data =3D &iris_hfi_gen1_data, - .vpu_ops =3D &iris_vpu2_ops, - .icc_tbl =3D sm8250_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), - .clk_rst_tbl =3D sm8250_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8250_clk_reset_table), - .bw_tbl_dec =3D sm8250_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl =3D sm8250_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl =3D sm8250_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl =3D sm8250_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), - .opp_clk_tbl =3D sm8250_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu-1.0/venus.mbn", - .inst_iris_fmts =3D platform_fmts_sm8250_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps =3D &platform_inst_cap_sm8250, - .tz_cp_config_data =3D tz_cp_config_sm8250, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sc7280_data =3D { - .firmware_data =3D &iris_hfi_gen1_data, - .vpu_ops =3D &iris_vpu2_ops, - .icc_tbl =3D sm8250_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), - .bw_tbl_dec =3D sc7280_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl =3D sm8250_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), - .opp_pd_tbl =3D sc7280_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl =3D sc7280_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), - .opp_clk_tbl =3D sc7280_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu20_p1.mbn", - .inst_iris_fmts =3D platform_fmts_sm8250_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), - .inst_caps =3D &platform_inst_cap_sm8250, - .tz_cp_config_data =3D tz_cp_config_sm8250, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 1, - .no_aon =3D true, - .max_session_count =3D 16, - .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, - /* max spec for SC7280 is 4096x2176@60fps */ - .max_core_mbps =3D 4096 * 2176 / 256 * 60, -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_hfi_gen2.c similarity index 78% rename from drivers/media/platform/qcom/iris/iris_platform_gen2.c rename to drivers/media/platform/qcom/iris/iris_hfi_gen2.c index a83f6910f8b7..9897864a0b3b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c @@ -4,40 +4,14 @@ * Copyright (c) 2025 Linaro Ltd */ =20 -#include "iris_core.h" #include "iris_ctrls.h" #include "iris_hfi_gen2.h" #include "iris_hfi_gen2_defines.h" #include "iris_platform_common.h" #include "iris_vpu_buffer.h" -#include "iris_vpu_common.h" =20 -#include "iris_platform_qcs8300.h" -#include "iris_platform_sm8650.h" -#include "iris_platform_sm8750.h" - -#define VIDEO_ARCH_LX 1 #define BITRATE_MAX 245000000 =20 -static struct iris_fmt platform_fmts_sm8550_dec[] =3D { - [IRIS_FMT_H264] =3D { - .pixfmt =3D V4L2_PIX_FMT_H264, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_HEVC] =3D { - .pixfmt =3D V4L2_PIX_FMT_HEVC, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_VP9] =3D { - .pixfmt =3D V4L2_PIX_FMT_VP9, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, - [IRIS_FMT_AV1] =3D { - .pixfmt =3D V4L2_PIX_FMT_AV1, - .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, - }, -}; - static const struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, @@ -742,58 +716,6 @@ static const struct platform_inst_fw_cap inst_fw_cap_s= m8550_enc[] =3D { }, }; =20 -static struct platform_inst_caps platform_inst_cap_sm8550 =3D { - .min_frame_width =3D 96, - .max_frame_width =3D 8192, - .min_frame_height =3D 96, - .max_frame_height =3D 8192, - .max_mbpf =3D (8192 * 4352) / 256, - .mb_cycles_vpp =3D 200, - .mb_cycles_fw =3D 489583, - .mb_cycles_fw_vpp =3D 66234, - .num_comv =3D 0, - .max_frame_rate =3D MAXIMUM_FPS, - .max_operating_rate =3D MAXIMUM_FPS, -}; - -static const struct icc_info sm8550_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8550_clk_reset_table[] =3D { "bus" }; - -static const struct bw_info sm8550_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 1608000 }, - { ((4096 * 2160) / 256) * 30, 826000 }, - { ((1920 * 1080) / 256) * 60, 567000 }, - { ((1920 * 1080) / 256) * 30, 294000 }, -}; - -static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; - -static const struct platform_clk_data sm8550_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - -static const char * const sm8550_opp_clk_table[] =3D { - "vcodec0_core", - NULL, -}; - -static const struct tz_cp_config tz_cp_config_sm8550[] =3D { - { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, - }, -}; - static const u32 sm8550_vdec_input_config_params_default[] =3D { HFI_PROP_BITSTREAM_RESOLUTION, HFI_PROP_CROP_OFFSETS, @@ -1035,144 +957,3 @@ const struct iris_firmware_data iris_hfi_gen2_vpu33_= data =3D { .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; - -const struct iris_platform_data sm8550_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data =3D { - .firmware_data =3D &iris_hfi_gen2_vpu33_data, - .vpu_ops =3D &iris_vpu33_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8650_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl =3D sm8650_controller_reset_table, - .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -const struct iris_platform_data sm8750_data =3D { - .firmware_data =3D &iris_hfi_gen2_vpu33_data, - .vpu_ops =3D &iris_vpu35_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8750_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8750_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu35_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, -}; - -/* - * Shares most of SM8550 data except: - * - inst_caps to platform_inst_cap_qcs8300 - */ -const struct iris_platform_data qcs8300_data =3D { - .firmware_data =3D &iris_hfi_gen2_data, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_qcs8300, - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 2, - .max_session_count =3D 16, - .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, - .max_core_mbps =3D (((3840 * 2176) / 256) * 120), -}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 1a870fec4f31..5be028af5ec6 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -40,6 +40,10 @@ enum pipe_type { PIPE_4 =3D 4, }; =20 +extern const struct iris_firmware_data iris_hfi_gen1_data; +extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_firmware_data iris_hfi_gen2_vpu33_data; + extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.h new file mode 100644 index 000000000000..50306043eb8e --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __IRIS_PLATFORM_SM8250_H__ +#define __IRIS_PLATFORM_SM8250_H__ + +static const struct bw_info sm8250_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 2403000 }, + { ((4096 * 2160) / 256) * 30, 1224000 }, + { ((1920 * 1080) / 256) * 60, 812000 }, + { ((1920 * 1080) / 256) * 30, 416000 }, +}; + +static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; + +static const struct platform_clk_data sm8250_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static const char * const sm8250_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.h new file mode 100644 index 000000000000..a9d9709c2e35 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_SM8550_H__ +#define __IRIS_PLATFORM_SM8550_H__ + +static const char * const sm8550_clk_reset_table[] =3D { "bus" }; + +static const struct platform_clk_data sm8550_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8550 =3D { + .min_frame_width =3D 96, + .max_frame_width =3D 8192, + .min_frame_height =3D 96, + .max_frame_height =3D 8192, + .max_mbpf =3D (8192 * 4352) / 256, + .mb_cycles_vpp =3D 200, + .mb_cycles_fw =3D 489583, + .mb_cycles_fw_vpp =3D 66234, + .num_comv =3D 0, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c new file mode 100644 index 000000000000..74c8f38e849b --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_platform_common.h" +#include "iris_resources.h" +#include "iris_hfi_gen1.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" +#include "iris_instance.h" + +#include "iris_platform_sc7280.h" +#include "iris_platform_sm8250.h" + +static struct iris_fmt platform_fmts_sm8250_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8250 =3D { + .min_frame_width =3D 128, + .max_frame_width =3D 8192, + .min_frame_height =3D 128, + .max_frame_height =3D 8192, + .max_mbpf =3D 138240, + .mb_cycles_vsp =3D 25, + .mb_cycles_vpp =3D 200, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, +}; + +static const struct icc_info sm8250_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const sm8250_clk_reset_table[] =3D { "bus", "core" }; + +static const char * const sm8250_pmdomain_table[] =3D { "venus", "vcodec0"= }; + +static const struct tz_cp_config tz_cp_config_sm8250[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +const struct iris_platform_data sc7280_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, + .vpu_ops =3D &iris_vpu2_ops, + .icc_tbl =3D sm8250_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), + .bw_tbl_dec =3D sc7280_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), + .pmdomain_tbl =3D sm8250_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl =3D sc7280_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), + .clk_tbl =3D sc7280_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), + .opp_clk_tbl =3D sc7280_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu20_p1.mbn", + .inst_iris_fmts =3D platform_fmts_sm8250_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), + .inst_caps =3D &platform_inst_cap_sm8250, + .tz_cp_config_data =3D tz_cp_config_sm8250, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 1, + .no_aon =3D true, + .max_session_count =3D 16, + .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, + /* max spec for SC7280 is 4096x2176@60fps */ + .max_core_mbps =3D 4096 * 2176 / 256 * 60, +}; + +const struct iris_platform_data sm8250_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, + .vpu_ops =3D &iris_vpu2_ops, + .icc_tbl =3D sm8250_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), + .clk_rst_tbl =3D sm8250_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8250_clk_reset_table), + .bw_tbl_dec =3D sm8250_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), + .pmdomain_tbl =3D sm8250_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8250_pmdomain_table), + .opp_pd_tbl =3D sm8250_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), + .clk_tbl =3D sm8250_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), + .opp_clk_tbl =3D sm8250_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu-1.0/venus.mbn", + .inst_iris_fmts =3D platform_fmts_sm8250_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), + .inst_caps =3D &platform_inst_cap_sm8250, + .tz_cp_config_data =3D tz_cp_config_sm8250, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu3.c new file mode 100644 index 000000000000..2c0e5be72920 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Linaro Ltd + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_hfi_gen2.h" +#include "iris_hfi_gen2_defines.h" +#include "iris_platform_common.h" +#include "iris_vpu_buffer.h" +#include "iris_vpu_common.h" + +#include "iris_platform_qcs8300.h" +#include "iris_platform_sm8550.h" +#include "iris_platform_sm8650.h" +#include "iris_platform_sm8750.h" + +#define VIDEO_ARCH_LX 1 + +static struct iris_fmt platform_fmts_sm8550_dec[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_VP9] =3D { + .pixfmt =3D V4L2_PIX_FMT_VP9, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, + [IRIS_FMT_AV1] =3D { + .pixfmt =3D V4L2_PIX_FMT_AV1, + .type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + }, +}; + +static const struct icc_info sm8550_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const struct bw_info sm8550_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; + +static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; + +static const char * const sm8550_opp_clk_table[] =3D { + "vcodec0_core", + NULL, +}; + +static const struct tz_cp_config tz_cp_config_sm8550[] =3D { + { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, + }, +}; + +/* + * Shares most of SM8550 data except: + * - inst_caps to platform_inst_cap_qcs8300 + */ +const struct iris_platform_data qcs8300_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_qcs8300, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 2, + .max_session_count =3D 16, + .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, + .max_core_mbps =3D (((3840 * 2176) / 256) * 120), +}; + +const struct iris_platform_data sm8550_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .vpu_ops =3D &iris_vpu33_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +const struct iris_platform_data sm8750_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .vpu_ops =3D &iris_vpu35_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8750_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8750_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu35_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; --=20 2.47.3