From nobody Tue Apr 7 14:25:33 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A1B134CFC4 for ; Fri, 13 Mar 2026 03:30:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773372657; cv=none; b=WIJlrq5EmuC03iVgH8B9IhYF9WTOzGNXULsMwtq/9MkBlPY3VaHJtstEzflLRNvME2xxl4hQvyoj3SngcGQ2qbhTZ6KLhjykxZlFCe6Nvt1k9R+ELF0H6IFFjIcyW/sFCvmXKzZzlNamjgskoRyI66Oz7Xf2cls6Dj5qUMpP+pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773372657; c=relaxed/simple; bh=mga+zqXjQbJ0PfzrD7ti6Z9CYd86oAWgGxgFX5M8R2I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uhMOeV/yUAgMT7rszrGBqtax9x0mRKZo+3Av/9aZ8Gu9gnrjZo7Kah50ief2NC2FPvjl++FfdodbJBi6rnWeXx62Meoh+5ALKT2dGGpcNaF/LSnkQ3EljiCNCjgBYcqIvZTs37EREZC4yW000AQHAZXMxshVFqJ4PWZwfoKonZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=HEHwMjzZ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=d6fK92JR; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="HEHwMjzZ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="d6fK92JR" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62CMJivP3178007 for ; Fri, 13 Mar 2026 03:30:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ABfgLuF49kb7gkskpj32VHDCCquSfEp8WWZcq8P64zc=; b=HEHwMjzZTn/Urllg SP2+BwuXn6fVzZ8DCzpA3Lc7C8iNH+D+1UhFXTOEM7GLghsv/ttcv2YXLTvFp0A4 buKvWMWhAxsdeRpzL8ZwR9QXwvvOfz/b5tAZvfgjHn+M/LK1alc2dEvL646degvt jEi89NHs25eKIrYnvaVsJXArkxByTr47QSJiAV2xxOMWHtvnKqiM4HFIDMx4mOMo xTnZ9hn7OYX7YFpzBa7A3XFvRxNvVxfL/VDHlmvWG9quY3JM6BcmMCLd8QS/zW9I //7oy5AruXBUigZlFBCHUcktN6le8LhiLGG7hNP0jxTaJpdKcgWcKmycjGqXCYB6 RTDChw== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cuh50v9vk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 13 Mar 2026 03:30:53 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-8cb706313beso255871285a.3 for ; Thu, 12 Mar 2026 20:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773372653; x=1773977453; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ABfgLuF49kb7gkskpj32VHDCCquSfEp8WWZcq8P64zc=; b=d6fK92JRTUMIsAx1nMxoWSgDDFV6LxjMUhI9Y9TsCfTh3B3Dr/+cRuAjgbNw4d6rQc 7pA9RFnrAksmrwXDq1hd8M998Ota6up8cCpKqc4s0uOKayXETJd1YzmvS1WyjQgnWfeN jAuCYFKkEe3tzVRgv8khPu5/WsGI8kTCDLuU9zIotDYt22fJqOFWZDLlhGfr9oY4cM4Q k02cnpQYEOfDLzvczjShqalCKajtNB+1Mux+QPr2A40hP9N87N7m9V0eX2CcNwfRViwd OCxegXuMxBzUtSXe/dUlnmPXatNcKIzWcjPY2IjwJHye7VWnUdLgYBFv2z4+QmlSzenb 14Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773372653; x=1773977453; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ABfgLuF49kb7gkskpj32VHDCCquSfEp8WWZcq8P64zc=; b=HhWISB4qe8FS8C5y02C+6mIXXTvf2Ph/Wc9A4olkNe5S6XXuS0fi6h5HIRP72gJBHf FNVMmqAgQ8wd6wvO4oHdS6HeP/XBjmCM/MBumS8ZdGPlN3qPxCzihhpexGOkmlhX4yqa HbrgXBwhgCfdTjhjOSGEz0XsQRDAsFWvBMUVvY7rAOz456CM1/+LJv/eX3mSbDluQ5b+ Y+vG+rdUohahuT5hmBj3J2Ems69E0Ij+j4dwTQRyw1M5LrpJ6x7vYgppK7UT+/sgQqKt G1HbqO4ZmF6w18Cfpxorass+cKGW9qRvIctHtBXZ3M/Oo8HkUXITjMbDeUFeepV1v+LR t9lQ== X-Forwarded-Encrypted: i=1; AJvYcCWrsQqDUfkYvS/b3dAaDVo7e57I9rX18uYQs4+texew9ca8vWYzLTV7wYDMFdLkcqpF3Hsn3aAdAyAJ6Ec=@vger.kernel.org X-Gm-Message-State: AOJu0YyCVQ1LkJvj0euAUK/XT5o+kxAI//4vvS5BYYMB76brcgbI80sO 6Pvhjnv6QwRtmNwNp0S/FIPSjsuko1IrRDY4fNQyHEqIRSQthorORXYz0PLLO4ByNEzZK3lprkR BwhZGef8RzruKWvVOpGHWw6BoFiLUCnMuUAEhCnvJ9qjfSd2r4aAu54VTQTi+1Z/68pU= X-Gm-Gg: ATEYQzyS3WV5eQ6mvvS5FQPnCOfbAmU0weGFx8ja8NwM2MBfZca1Ao2O8A7qByVGXbj Yy599QviwZml8DPSat3PGbbr+IWmz2YbH435UpH2eC/azurfJGnifvgzDMjFLUijyBxFfaOWLn2 4QtsykelQjPedp9651y6yAaCFAISlNlgWvNxc3d/bib4dA/WOAZKadmEkUNIYzONxioKxq5mwS1 k4ZzS+cgyG3o1agrXRrm/jQcIRoFNpWP8656gaytq8apikFeRliKZvBZtlZI91/bk0ZnleNjhfG YN9n4REvcixHLxwEQQHPjuuxYno+E3Tipj2NswX6AQsoPT6imvK7MqbOs8Az6Nl/u78ZLNWIqK/ jJHlo1yI8C9VZU5XGSDoJKSUy0yB8wllWOQXi+1KlozvvF6CzhZ2v4o1WIPZI2Gm+xjXuMOBOYD sJI8ZOUStbWA9TX4kXXBe7uL50rM253614kpc= X-Received: by 2002:a05:620a:171e:b0:8cd:81cc:556e with SMTP id af79cd13be357-8cdb5b0a283mr293488985a.40.1773372652180; Thu, 12 Mar 2026 20:30:52 -0700 (PDT) X-Received: by 2002:a05:620a:171e:b0:8cd:81cc:556e with SMTP id af79cd13be357-8cdb5b0a283mr293486085a.40.1773372651510; Thu, 12 Mar 2026 20:30:51 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38a67d93576sm11254901fa.11.2026.03.12.20.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 20:30:48 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 13 Mar 2026 05:30:24 +0200 Subject: [PATCH v4 7/8] media: qcom: iris: split firmware_data from raw platform data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-iris-platform-data-v4-7-14927df4906d@oss.qualcomm.com> References: <20260313-iris-platform-data-v4-0-14927df4906d@oss.qualcomm.com> In-Reply-To: <20260313-iris-platform-data-v4-0-14927df4906d@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=45943; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=mga+zqXjQbJ0PfzrD7ti6Z9CYd86oAWgGxgFX5M8R2I=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ+bmljMfbjW8jMv9LmHBn7azXvxzxI7AP4yBzo7Tjjdsd fj397RPJ6MxCwMjF4OsmCKLT0HL1JhNyWEfdkythxnEygQyhYGLUwAmsqyT/a/ktz615H23eS+c 21u3quDG+wQDNatoU0PmlgXaGVKFKllfQh+VLfl+fOuDk7eemm3XD9/Elbnaz2hhkHfkL6Wvwgv F00XEZu7tlVhxtS9ySu2maIH58d4zZxd/M/S/sGxq5BmP21fM7T6z/XZgk1KslOezNM0vKik5// jGH9Yuna6Tii27o6K1j/3Jd/z1OGSPbKvSXzEVLQ6m5od9lV1zmfXP6N4uvthu8v7E5JoWecn0N acmz9ZfGJC98XpwOEtCeDr3H2Xx1a0fPquFTsibksNjpHGgZt1Zr72SS38H/de7v59T70RJtYuj RNh2G/4PNjamhXut0jhmucw039H93XvzDfu8gCtaYl/FAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: LCTs4NtC510y62Ei3BMEIKIszsPyFkwz X-Authority-Analysis: v=2.4 cv=LvKfC3dc c=1 sm=1 tr=0 ts=69b384ed cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=coRdw7kJwGx05Zhg8iIA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: LCTs4NtC510y62Ei3BMEIKIszsPyFkwz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDAyNiBTYWx0ZWRfX4hXBnolHG3mn ILkSJh/tJC6uPza+0CHWXvy4jJHQduITgFJXcP8SDc4krLT/it60Yc/XmkWPVKYhwOuX9D0gV5j CcuCq/73hTdrdhTshVw7MOPPg+q4+rTXais1LBdX2p6KgaAOmDJLHKKYfh2n/7e8kINRrok1shp wtP6HjhW+fvd6hDJFBpnHMBaxDYeJ6c9Ntg35fQXnbod5OrWt4S/l8El8fxapWJvcg0fpBAalz7 6TYElLtTTLWcnp2Ki7SZSTqWbO5h58/2lxvUToucTop8vKIUEfz6lv8A3wYWYudxozGxVsqJewb 0c0cPorQreoapeiNotxziensBtfweKZf5ow2jD3SjXKAM9+5KmRgUwqx3M5zZu9Gk6RcnJFGXJg I9lf7kz+wkJcqNlwAq5Wrl0wxcG542mT6cQR8LHjNZnxEWXiVc82MxPWfnei/6IWgoJEg5PSJmo JfIz94V1IdtDHAO2FJA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_03,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130026 Having firmware-related fields in platform data results in the tying platform data to the HFI firmware data rather than the actual hardware. For example, SM8450 uses Gen2 firmware, so currently its platform data should be placed next to the other gen2 platforms, although it has the VPU2.0 core, similar to the one found on SM8250 and SC7280 and so the hardware-specific platform data is also close to those devices. Split firmware data to a separate struct, separating hardware-related data from the firmware interfaces. Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_buffer.c | 84 +++---- drivers/media/platform/qcom/iris/iris_core.h | 1 + drivers/media/platform/qcom/iris/iris_ctrls.c | 8 +- .../platform/qcom/iris/iris_hfi_gen1_command.c | 10 +- .../platform/qcom/iris/iris_hfi_gen2_command.c | 66 ++--- .../platform/qcom/iris/iris_platform_common.h | 79 +++--- .../media/platform/qcom/iris/iris_platform_gen1.c | 68 +++--- .../media/platform/qcom/iris/iris_platform_gen2.c | 268 +++++++----------= ---- drivers/media/platform/qcom/iris/iris_probe.c | 3 +- drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- 10 files changed, 246 insertions(+), 351 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index f55b7c608116..22596fc6d02f 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -295,37 +295,37 @@ static void iris_fill_internal_buf_info(struct iris_i= nst *inst, { struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; =20 - buffers->size =3D inst->core->iris_platform_data->get_vpu_buffer_size(ins= t, buffer_type); + buffers->size =3D inst->core->iris_firmware_data->get_vpu_buffer_size(ins= t, buffer_type); buffers->min_count =3D iris_vpu_buf_count(inst, buffer_type); } =20 void iris_get_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } @@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst= *inst, =20 int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; u32 internal_buffer_count, i, j; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *in= st, u32 plane) =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_in= st *inst, enum iris_buffe =20 int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buffer, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *ins= t, u32 plane) =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst= , struct iris_buffer *buf =20 static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane= , bool force) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_= inst *inst, u32 plane, bool =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - len =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + len =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - len =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + len =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - len =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + len =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - len =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + len =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -593,17 +593,17 @@ static int iris_release_internal_buffers(struct iris_= inst *inst, =20 static int iris_release_input_internal_buffers(struct iris_inst *inst) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; int ret; =20 if (inst->domain =3D=3D DECODER) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } =20 for (i =3D 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 1d9a435ee747..70322f40ec1d 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -98,6 +98,7 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; + const struct iris_firmware_data *iris_firmware_data; const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 5a24aa869b2d..ef7adac3764d 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core) const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; =20 - caps =3D core->iris_platform_data->inst_fw_caps_dec; - num_cap =3D core->iris_platform_data->inst_fw_caps_dec_size; + caps =3D core->iris_firmware_data->inst_fw_caps_dec; + num_cap =3D core->iris_firmware_data->inst_fw_caps_dec_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; @@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core) } } =20 - caps =3D core->iris_platform_data->inst_fw_caps_enc; - num_cap =3D core->iris_platform_data->inst_fw_caps_enc_size; + caps =3D core->iris_firmware_data->inst_fw_caps_enc; + num_cap =3D core->iris_firmware_data->inst_fw_caps_enc_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 0017ade4adbd..fd491ad75d00 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -918,7 +918,7 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst *= inst, u32 plane) =20 if (iris_split_mode_enabled(inst)) { bufsz.type =3D HFI_BUFFER_OUTPUT; - bufsz.size =3D inst->core->iris_platform_data->get_vpu_buffer_size(inst,= BUF_DPB); + bufsz.size =3D inst->core->iris_firmware_data->get_vpu_buffer_size(inst,= BUF_DPB); =20 ret =3D hfi_gen1_set_property(inst, ptype, &bufsz, sizeof(bufsz)); if (ret) @@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p }; =20 if (inst->domain =3D=3D DECODER) { - config_params =3D core->iris_platform_data->dec_input_config_params_defa= ult; - config_params_size =3D core->iris_platform_data->dec_input_config_params= _default_size; + config_params =3D core->iris_firmware_data->dec_input_config_params_defa= ult; + config_params_size =3D core->iris_firmware_data->dec_input_config_params= _default_size; if (V4L2_TYPE_IS_OUTPUT(plane)) { handler =3D vdec_prop_type_handle_inp_arr; handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_inp_arr); @@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_out_arr); } } else { - config_params =3D core->iris_platform_data->enc_input_config_params; - config_params_size =3D core->iris_platform_data->enc_input_config_params= _size; + config_params =3D core->iris_firmware_data->enc_input_config_params; + config_params_size =3D core->iris_firmware_data->enc_input_config_params= _size; handler =3D venc_prop_type_handle_inp_arr; handler_size =3D ARRAY_SIZE(venc_prop_type_handle_inp_arr); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 639b75fca1ab..c90b22a75bc5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -601,7 +601,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_in= st *inst, u32 plane) =20 static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { - const struct iris_platform_data *pdata =3D inst->core->iris_platform_data; + const struct iris_firmware_data *fdata =3D inst->core->iris_firmware_data; u32 config_params_size =3D 0, i, j; const u32 *config_params =3D NULL; int ret; @@ -630,31 +630,31 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - config_params =3D pdata->dec_input_config_params_default; - config_params_size =3D pdata->dec_input_config_params_default_size; + config_params =3D fdata->dec_input_config_params_default; + config_params_size =3D fdata->dec_input_config_params_default_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { - config_params =3D pdata->dec_input_config_params_hevc; - config_params_size =3D pdata->dec_input_config_params_hevc_size; + config_params =3D fdata->dec_input_config_params_hevc; + config_params_size =3D fdata->dec_input_config_params_hevc_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) { - config_params =3D pdata->dec_input_config_params_vp9; - config_params_size =3D pdata->dec_input_config_params_vp9_size; + config_params =3D fdata->dec_input_config_params_vp9; + config_params_size =3D fdata->dec_input_config_params_vp9_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { - config_params =3D pdata->dec_input_config_params_av1; - config_params_size =3D pdata->dec_input_config_params_av1_size; + config_params =3D fdata->dec_input_config_params_av1; + config_params_size =3D fdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params =3D pdata->dec_output_config_params; - config_params_size =3D pdata->dec_output_config_params_size; + config_params =3D fdata->dec_output_config_params; + config_params_size =3D fdata->dec_output_config_params_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params =3D pdata->enc_input_config_params; - config_params_size =3D pdata->enc_input_config_params_size; + config_params =3D fdata->enc_input_config_params; + config_params_size =3D fdata->enc_input_config_params_size; } else { - config_params =3D pdata->enc_output_config_params; - config_params_size =3D pdata->enc_output_config_params_size; + config_params =3D fdata->enc_output_config_params; + config_params_size =3D fdata->enc_output_config_params_size; } } =20 @@ -849,24 +849,24 @@ static int iris_hfi_gen2_subscribe_change_param(struc= t iris_inst *inst, u32 plan =20 switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param =3D core->iris_platform_data->dec_input_config_params_defau= lt; + change_param =3D core->iris_firmware_data->dec_input_config_params_defau= lt; change_param_size =3D - core->iris_platform_data->dec_input_config_params_default_size; + core->iris_firmware_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param =3D core->iris_platform_data->dec_input_config_params_hevc; + change_param =3D core->iris_firmware_data->dec_input_config_params_hevc; change_param_size =3D - core->iris_platform_data->dec_input_config_params_hevc_size; + core->iris_firmware_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param =3D core->iris_platform_data->dec_input_config_params_vp9; + change_param =3D core->iris_firmware_data->dec_input_config_params_vp9; change_param_size =3D - core->iris_platform_data->dec_input_config_params_vp9_size; + core->iris_firmware_data->dec_input_config_params_vp9_size; break; case V4L2_PIX_FMT_AV1: - change_param =3D core->iris_platform_data->dec_input_config_params_av1; + change_param =3D core->iris_firmware_data->dec_input_config_params_av1; change_param_size =3D - core->iris_platform_data->dec_input_config_params_av1_size; + core->iris_firmware_data->dec_input_config_params_av1_size; break; } =20 @@ -996,29 +996,29 @@ static int iris_hfi_gen2_subscribe_property(struct ir= is_inst *inst, u32 plane) return 0; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { - subscribe_prop_size =3D core->iris_platform_data->dec_input_prop_size; - subcribe_prop =3D core->iris_platform_data->dec_input_prop; + subscribe_prop_size =3D core->iris_firmware_data->dec_input_prop_size; + subcribe_prop =3D core->iris_firmware_data->dec_input_prop; } else { switch (inst->codec) { case V4L2_PIX_FMT_H264: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_avc; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_avc; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_avc_size; + core->iris_firmware_data->dec_output_prop_avc_size; break; case V4L2_PIX_FMT_HEVC: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_hevc; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_hevc; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_hevc_size; + core->iris_firmware_data->dec_output_prop_hevc_size; break; case V4L2_PIX_FMT_VP9: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_vp9; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_vp9; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_vp9_size; + core->iris_firmware_data->dec_output_prop_vp9_size; break; case V4L2_PIX_FMT_AV1: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_av1; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_av1; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_av1_size; + core->iris_firmware_data->dec_output_prop_av1_size; break; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index d1daef2d874b..1a870fec4f31 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -201,45 +201,16 @@ enum platform_pm_domain_type { IRIS_APV_HW_POWER_DOMAIN, }; =20 -struct iris_platform_data { +struct iris_firmware_data { void (*init_hfi_ops)(struct iris_core *core); + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); - const struct vpu_ops *vpu_ops; - const struct icc_info *icc_tbl; - unsigned int icc_tbl_size; - const struct bw_info *bw_tbl_dec; - unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; - const char * const *opp_pd_tbl; - unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; - const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; - const char * const *clk_rst_tbl; - unsigned int clk_rst_tbl_size; - const char * const *controller_rst_tbl; - unsigned int controller_rst_tbl_size; - u64 dma_mask; - const char *fwname; - struct iris_fmt *inst_iris_fmts; - u32 inst_iris_fmts_size; - struct platform_inst_caps *inst_caps; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - const struct tz_cp_config *tz_cp_config_data; - u32 tz_cp_config_data_size; - u32 core_arch; - u32 hw_response_timeout; - u32 num_vpp_pipe; - bool no_aon; - u32 max_session_count; - /* max number of macroblocks per frame supported */ - u32 max_core_mbpf; - /* max number of macroblocks per second supported */ - u32 max_core_mbps; + const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -254,6 +225,7 @@ struct iris_platform_data { unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; unsigned int enc_output_config_params_size; + const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; @@ -264,6 +236,7 @@ struct iris_platform_data { unsigned int dec_output_prop_vp9_size; const u32 *dec_output_prop_av1; unsigned int dec_output_prop_av1_size; + const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; @@ -274,4 +247,44 @@ struct iris_platform_data { unsigned int enc_op_int_buf_tbl_size; }; =20 +struct iris_platform_data { + /* + * XXX: remove firmware_data pointer once we have platforms supporting + * both firmware kinds. + */ + const struct iris_firmware_data *firmware_data; + const struct vpu_ops *vpu_ops; + const struct icc_info *icc_tbl; + unsigned int icc_tbl_size; + const struct bw_info *bw_tbl_dec; + unsigned int bw_tbl_dec_size; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; + const char * const *opp_pd_tbl; + unsigned int opp_pd_tbl_size; + const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; + unsigned int clk_tbl_size; + const char * const *clk_rst_tbl; + unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; + u64 dma_mask; + const char *fwname; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; + struct platform_inst_caps *inst_caps; + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; + u32 core_arch; + u32 hw_response_timeout; + u32 num_vpp_pipe; + bool no_aon; + u32 max_session_count; + /* max number of macroblocks per frame supported */ + u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 9925a893b404..27f2ef04cffe 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -332,9 +332,34 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -const struct iris_platform_data sm8250_data =3D { +const struct iris_firmware_data iris_hfi_gen1_data =3D { .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, + + .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), + + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; + +const struct iris_platform_data sm8250_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), @@ -355,10 +380,6 @@ const struct iris_platform_data sm8250_data =3D { .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D tz_cp_config_sm8250, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, @@ -366,26 +387,10 @@ const struct iris_platform_data sm8250_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params =3D sm8250_venc_input_config_param, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; =20 const struct iris_platform_data sc7280_data =3D { - .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu_buf_size, + .firmware_data =3D &iris_hfi_gen1_data, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8250_icc_table), @@ -404,10 +409,6 @@ const struct iris_platform_data sc7280_data =3D { .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D tz_cp_config_sm8250, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, @@ -417,19 +418,4 @@ const struct iris_platform_data sc7280_data =3D { .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ .max_core_mbps =3D 4096 * 2176 / 256 * 60, - .dec_input_config_params_default =3D - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params =3D sm8250_venc_input_config_param, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 10a972f96cbe..a83f6910f8b7 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -906,41 +906,15 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -const struct iris_platform_data sm8550_data =3D { +const struct iris_firmware_data iris_hfi_gen2_data =3D { .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size =3D @@ -997,50 +971,15 @@ const struct iris_platform_data sm8550_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 -/* - * Shares most of SM8550 data except: - * - vpu_ops to iris_vpu33_ops - * - clk_rst_tbl to sm8650_clk_reset_table - * - controller_rst_tbl to sm8650_controller_reset_table - * - fwname to "qcom/vpu/vpu33_p4.mbn" - */ -const struct iris_platform_data sm8650_data =3D { +const struct iris_firmware_data iris_hfi_gen2_vpu33_data =3D { .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, .get_vpu_buffer_size =3D iris_vpu33_buf_size, - .vpu_ops =3D &iris_vpu33_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8650_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), - .controller_rst_tbl =3D sm8650_controller_reset_table, - .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu33_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size =3D @@ -1097,9 +1036,81 @@ const struct iris_platform_data sm8650_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 +const struct iris_platform_data sm8550_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +const struct iris_platform_data sm8650_data =3D { + .firmware_data =3D &iris_hfi_gen2_vpu33_data, + .vpu_ops =3D &iris_vpu33_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + const struct iris_platform_data sm8750_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu33_buf_size, + .firmware_data =3D &iris_hfi_gen2_vpu33_data, .vpu_ops =3D &iris_vpu35_ops, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), @@ -1120,10 +1131,6 @@ const struct iris_platform_data sm8750_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, @@ -1132,60 +1139,6 @@ const struct iris_platform_data sm8750_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 /* @@ -1193,8 +1146,7 @@ const struct iris_platform_data sm8750_data =3D { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu_buf_size, + .firmware_data =3D &iris_hfi_gen2_data, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D sm8550_icc_table, .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), @@ -1215,10 +1167,6 @@ const struct iris_platform_data qcs8300_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_qcs8300, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), .core_arch =3D VIDEO_ARCH_LX, @@ -1227,58 +1175,4 @@ const struct iris_platform_data qcs8300_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index fa561f6a736c..dd87504c2e67 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -251,6 +251,7 @@ static int iris_probe(struct platform_device *pdev) return core->irq; =20 core->iris_platform_data =3D of_device_get_match_data(core->dev); + core->iris_firmware_data =3D core->iris_platform_data->firmware_data; =20 core->ubwc_cfg =3D qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) @@ -264,7 +265,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); =20 iris_init_ops(core); - core->iris_platform_data->init_hfi_ops(core); + core->iris_firmware_data->init_hfi_ops(core); =20 ret =3D iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index ecd8a20fedbf..807c9a20b6ba 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -243,7 +243,7 @@ static void iris_session_close(struct iris_inst *inst) =20 static void iris_check_num_queued_internal_buffers(struct iris_inst *inst,= u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -251,11 +251,11 @@ static void iris_check_num_queued_internal_buffers(st= ruct iris_inst *inst, u32 p u32 count =3D 0; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } =20 for (i =3D 0; i < internal_buffer_count; i++) { --=20 2.47.3