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Thu, 12 Mar 2026 23:49:44 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c73eb97b41dsm936160a12.5.2026.03.12.23.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 23:49:43 -0700 (PDT) From: Sumit Kumar Date: Fri, 13 Mar 2026 12:19:26 +0530 Subject: [PATCH 2/3] PCI: epf-mhi: Add batched DMA read support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-dma_multi_sg-v1-2-8fabb0d1a759@oss.qualcomm.com> References: <20260313-dma_multi_sg-v1-0-8fabb0d1a759@oss.qualcomm.com> In-Reply-To: <20260313-dma_multi_sg-v1-0-8fabb0d1a759@oss.qualcomm.com> To: Krishna Chaitanya Chundru , Veerabhadrarao Badiganti , Subramanian Ananthanarayanan , Akhil Vinod , Manivannan Sadhasivam , Vinod Koul , Marek Szyprowski , Robin Murphy , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pci@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Implement two variants of the read_batch() callback: - pci_epf_mhi_edma_read_batch(): DMA-optimized implementation using dmaengine_prep_batch_sg_dma() to transfer multiple buffers in a single DMA transaction. - pci_epf_mhi_iatu_read_batch(): CPU-copy fallback that sequentially processes buffers using IATU. This enables the MHI endpoint stack to efficiently cache ring data, particularly for wraparound scenarios where ring data spans two non-contiguous memory regions. Signed-off-by: Sumit Kumar --- drivers/pci/endpoint/functions/Kconfig | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 120 +++++++++++++++++++++++= ++++ include/linux/mhi_ep.h | 3 + 3 files changed, 124 insertions(+) diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/= functions/Kconfig index 0c9cea0698d7bd3d8bd11aa1db0195978d9406b9..43131b6db8a2ca57b7a4f0eba8a= ffba3a77f9ad7 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -41,6 +41,7 @@ config PCI_EPF_VNTB config PCI_EPF_MHI tristate "PCI Endpoint driver for MHI bus" depends on PCI_ENDPOINT && MHI_BUS_EP + select NEED_SG_DMA_DST_ADDR help Enable this configuration option to enable the PCI Endpoint driver for Modem Host Interface (MHI) bus in Qualcomm Endpoint diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 6643a88c7a0ce38161bc6253c09d29f1c36ba394..198201d734cc2c6d09be229464a= 8efdafc3cd611 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -448,6 +448,124 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl= *mhi_cntrl, return ret; } =20 +static int pci_epf_mhi_iatu_read_batch(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info_array, + u32 num_buffers) +{ + int ret; + u32 i; + + for (i =3D 0; i < num_buffers; i++) { + ret =3D pci_epf_mhi_iatu_read(mhi_cntrl, &buf_info_array[i]); + if (ret < 0) + return ret; + } + + return 0; +} + +static int pci_epf_mhi_edma_read_batch(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info_array, + u32 num_buffers) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct dma_chan *chan =3D epf_mhi->dma_chan_rx; + struct device *dev =3D &epf_mhi->epf->dev; + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + DECLARE_COMPLETION_ONSTACK(complete); + struct scatterlist *sg; + dma_addr_t *dst_addrs; + dma_cookie_t cookie; + int ret; + u32 i; + + if (num_buffers =3D=3D 0) + return -EINVAL; + + mutex_lock(&epf_mhi->lock); + + sg =3D kcalloc(num_buffers, sizeof(*sg), GFP_KERNEL); + if (!sg) { + ret =3D -ENOMEM; + goto err_unlock; + } + + dst_addrs =3D kcalloc(num_buffers, sizeof(*dst_addrs), GFP_KERNEL); + if (!dst_addrs) { + ret =3D -ENOMEM; + goto err_free_sg; + } + + sg_init_table(sg, num_buffers); + + for (i =3D 0; i < num_buffers; i++) { + dst_addrs[i] =3D dma_map_single(dma_dev, buf_info_array[i].dev_addr, + buf_info_array[i].size, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(dma_dev, dst_addrs[i]); + if (ret) { + dev_err(dev, "Failed to map buffer %u\n", i); + goto err_unmap; + } + + sg_dma_address(&sg[i]) =3D buf_info_array[i].host_addr; + sg_dma_dst_address(&sg[i]) =3D dst_addrs[i]; + sg_dma_len(&sg[i]) =3D buf_info_array[i].size; + } + + config.direction =3D DMA_DEV_TO_MEM; + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unmap; + } + + desc =3D dmaengine_prep_batch_sg_dma(chan, sg, num_buffers, + DMA_DEV_TO_MEM, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare batch sg DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + desc->callback =3D pci_epf_mhi_dma_callback; + desc->callback_param =3D &complete; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to submit DMA\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + + ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + if (!ret) { + dev_err(dev, "DMA transfer timeout\n"); + dmaengine_terminate_sync(chan); + ret =3D -ETIMEDOUT; + goto err_unmap; + } + + ret =3D 0; + +err_unmap: + for (i =3D 0; i < num_buffers; i++) { + if (dst_addrs[i]) + dma_unmap_single(dma_dev, dst_addrs[i], + buf_info_array[i].size, DMA_FROM_DEVICE); + } + kfree(dst_addrs); +err_free_sg: + kfree(sg); +err_unlock: + mutex_unlock(&epf_mhi->lock); + return ret; +} + static void pci_epf_mhi_dma_worker(struct work_struct *work) { struct pci_epf_mhi *epf_mhi =3D container_of(work, struct pci_epf_mhi, dm= a_work); @@ -803,11 +921,13 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; mhi_cntrl->read_sync =3D mhi_cntrl->read_async =3D pci_epf_mhi_iatu_read; mhi_cntrl->write_sync =3D mhi_cntrl->write_async =3D pci_epf_mhi_iatu_wri= te; + mhi_cntrl->read_batch =3D pci_epf_mhi_iatu_read_batch; if (info->flags & MHI_EPF_USE_DMA) { mhi_cntrl->read_sync =3D pci_epf_mhi_edma_read; mhi_cntrl->write_sync =3D pci_epf_mhi_edma_write; mhi_cntrl->read_async =3D pci_epf_mhi_edma_read_async; mhi_cntrl->write_async =3D pci_epf_mhi_edma_write_async; + mhi_cntrl->read_batch =3D pci_epf_mhi_edma_read_batch; } =20 /* Register the MHI EP controller */ diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 7b40fc8cbe77ab8419d167e89264b69a817b9fb1..15554f966e4be1aea1f3129c5f2= 6253f5087edba 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -107,6 +107,7 @@ struct mhi_ep_buf_info { * @write_sync: CB function for writing to host memory synchronously * @read_async: CB function for reading from host memory asynchronously * @write_async: CB function for writing to host memory asynchronously + * @read_batch: CB function for reading from host memory in batches synchr= onously * @mhi_state: MHI Endpoint state * @max_chan: Maximum channels supported by the endpoint controller * @mru: MRU (Maximum Receive Unit) value of the endpoint controller @@ -164,6 +165,8 @@ struct mhi_ep_cntrl { int (*write_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); int (*read_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); int (*write_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info= *buf_info); + int (*read_batch)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info_array, + u32 num_buffers); =20 enum mhi_state mhi_state; =20 --=20 2.34.1