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Each scatter-gather entry specifies both source and destination addresses. This allows multiple non-contiguous memory regions to be transferred in a single DMA transaction instead of separate operations, significantly reducing submission overhead and interrupt overhead. Extends struct scatterlist with optional dma_dst_address field and implements support in dw-edma driver. Signed-off-by: Sumit Kumar --- drivers/dma/dw-edma/Kconfig | 1 + drivers/dma/dw-edma/dw-edma-core.c | 40 ++++++++++++++++++++++++++++++++++= ---- drivers/dma/dw-edma/dw-edma-core.h | 3 ++- include/linux/dmaengine.h | 29 ++++++++++++++++++++++++++- include/linux/scatterlist.h | 7 +++++++ kernel/dma/Kconfig | 3 +++ 6 files changed, 77 insertions(+), 6 deletions(-) diff --git a/drivers/dma/dw-edma/Kconfig b/drivers/dma/dw-edma/Kconfig index 2b6f2679508d93b94b7efecd4e36d5902f7b4c99..0472a6554ff38d4cf172a90b6bf= 0bdaa9e7f4b95 100644 --- a/drivers/dma/dw-edma/Kconfig +++ b/drivers/dma/dw-edma/Kconfig @@ -5,6 +5,7 @@ config DW_EDMA depends on PCI && PCI_MSI select DMA_ENGINE select DMA_VIRTUAL_CHANNELS + select NEED_SG_DMA_DST_ADDR help Support the Synopsys DesignWare eDMA controller, normally implemented on endpoints SoCs. diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 8e5f7defa6b678eefe0f312ebc59f654677c744f..04314cfd82edbed6ed3665eb4c8= e6b428339c207 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -411,6 +411,9 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) return NULL; if (!xfer->xfer.il->src_inc || !xfer->xfer.il->dst_inc) return NULL; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_ADDR_SG) { + if (xfer->xfer.sg.len < 1) + return NULL; } else { return NULL; } @@ -438,7 +441,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) =20 if (xfer->type =3D=3D EDMA_XFER_CYCLIC) { cnt =3D xfer->xfer.cyclic.cnt; - } else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER) { + } else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER || xfer->type =3D= =3D EDMA_XFER_DUAL_ADDR_SG) { cnt =3D xfer->xfer.sg.len; sg =3D xfer->xfer.sg.sgl; } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { @@ -447,7 +450,8 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) } =20 for (i =3D 0; i < cnt; i++) { - if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER && !sg) + if ((xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER || + xfer->type =3D=3D EDMA_XFER_DUAL_ADDR_SG) && !sg) break; =20 if (chunk->bursts_alloc =3D=3D chan->ll_max) { @@ -462,7 +466,8 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) =20 if (xfer->type =3D=3D EDMA_XFER_CYCLIC) burst->sz =3D xfer->xfer.cyclic.len; - else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER) + else if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER || + xfer->type =3D=3D EDMA_XFER_DUAL_ADDR_SG) burst->sz =3D sg_dma_len(sg); else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) burst->sz =3D xfer->xfer.il->sgl[i % fsz].size; @@ -486,6 +491,9 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) */ } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { burst->dar =3D dst_addr; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_ADDR_SG) { + burst->sar =3D dw_edma_get_pci_address(chan, sg_dma_address(sg)); + burst->dar =3D sg_dma_dst_address(sg); } } else { burst->dar =3D dst_addr; @@ -503,10 +511,14 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) */ } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { burst->sar =3D src_addr; + } else if (xfer->type =3D=3D EDMA_XFER_DUAL_ADDR_SG) { + burst->sar =3D sg_dma_address(sg); + burst->dar =3D dw_edma_get_pci_address(chan, sg_dma_dst_address(sg)); } } =20 - if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER) { + if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER || + xfer->type =3D=3D EDMA_XFER_DUAL_ADDR_SG) { sg =3D sg_next(sg); } else if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { struct dma_interleaved_template *il =3D xfer->xfer.il; @@ -603,6 +615,25 @@ static void dw_hdma_set_callback_result(struct virt_dm= a_desc *vd, res->residue =3D residue; } =20 +static struct dma_async_tx_descriptor * +dw_edma_device_prep_batch_sg_dma(struct dma_chan *dchan, + struct scatterlist *sg, + unsigned int nents, + enum dma_transfer_direction direction, + unsigned long flags) +{ + struct dw_edma_transfer xfer; + + xfer.dchan =3D dchan; + xfer.direction =3D direction; + xfer.xfer.sg.sgl =3D sg; + xfer.xfer.sg.len =3D nents; + xfer.flags =3D flags; + xfer.type =3D EDMA_XFER_DUAL_ADDR_SG; + + return dw_edma_device_transfer(&xfer); +} + static void dw_edma_done_interrupt(struct dw_edma_chan *chan) { struct dw_edma_desc *desc; @@ -818,6 +849,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) dma->device_prep_slave_sg =3D dw_edma_device_prep_slave_sg; dma->device_prep_dma_cyclic =3D dw_edma_device_prep_dma_cyclic; dma->device_prep_interleaved_dma =3D dw_edma_device_prep_interleaved_dma; + dma->device_prep_batch_sg_dma =3D dw_edma_device_prep_batch_sg_dma; =20 dma_set_max_seg_size(dma->dev, U32_MAX); =20 diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 71894b9e0b1539c636171738963e80a0a5ef43a4..1a266dc58315edb3d5fd9eddb19= fc350f1ed9a1b 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -36,7 +36,8 @@ enum dw_edma_status { enum dw_edma_xfer_type { EDMA_XFER_SCATTER_GATHER =3D 0, EDMA_XFER_CYCLIC, - EDMA_XFER_INTERLEAVED + EDMA_XFER_INTERLEAVED, + EDMA_XFER_DUAL_ADDR_SG, }; =20 struct dw_edma_chan; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 99efe2b9b4ea9844ca6161208362ef18ef111d96..fdba75b5c40f805904a6697fce3= 062303fea762a 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -939,7 +939,11 @@ struct dma_device { size_t period_len, enum dma_transfer_direction direction, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( - struct dma_chan *chan, struct dma_interleaved_template *xt, + struct dma_chan *chan, struct dma_interleaved_template *xt, + unsigned long flags); + struct dma_async_tx_descriptor *(*device_prep_batch_sg_dma) + (struct dma_chan *chan, struct scatterlist *sg, unsigned int nents, + enum dma_transfer_direction direction, unsigned long flags); =20 void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); @@ -1060,6 +1064,29 @@ static inline struct dma_async_tx_descriptor *dmaeng= ine_prep_interleaved_dma( return chan->device->device_prep_interleaved_dma(chan, xt, flags); } =20 +/** + * dmaengine_prep_batch_sg_dma() - Prepare single DMA transfer for multipl= e independent buffers. + * @chan: DMA channel + * @sg: Scatter-gather list with both source (dma_address) and destination= (dma_dst_address) + * @nents: Number of entries in the list + * @direction: Transfer direction (DMA_MEM_TO_MEM, DMA_DEV_TO_MEM, DMA_MEM= _TO_DEV) + * @flags: DMA engine flags + * + * Each SG entry contains both source (sg_dma_address) and destination (sg= _dma_dst_address). + * This allows multiple independent transfers in a single DMA transaction. + * Requires CONFIG_NEED_SG_DMA_DST_ADDR to be enabled. + */ +static inline struct dma_async_tx_descriptor *dmaengine_prep_batch_sg_dma + (struct dma_chan *chan, struct scatterlist *sg, unsigned int nents, + enum dma_transfer_direction direction, unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_batch_sg_dma || + !sg || !nents) + return NULL; + + return chan->device->device_prep_batch_sg_dma(chan, sg, nents, direction,= flags); +} + /** * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor. * @chan: The channel to be used for this descriptor diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h index 29f6ceb98d74b118d08b6a3d4eb7f62dcde0495d..20b65ffcd5e2a65ec5026a29344= caf6baa09700b 100644 --- a/include/linux/scatterlist.h +++ b/include/linux/scatterlist.h @@ -19,6 +19,9 @@ struct scatterlist { #ifdef CONFIG_NEED_SG_DMA_FLAGS unsigned int dma_flags; #endif +#ifdef CONFIG_NEED_SG_DMA_DST_ADDR + dma_addr_t dma_dst_address; +#endif }; =20 /* @@ -36,6 +39,10 @@ struct scatterlist { #define sg_dma_len(sg) ((sg)->length) #endif =20 +#ifdef CONFIG_NEED_SG_DMA_DST_ADDR +#define sg_dma_dst_address(sg) ((sg)->dma_dst_address) +#endif + struct sg_table { struct scatterlist *sgl; /* the list */ unsigned int nents; /* number of mapped entries */ diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig index 31cfdb6b4bc3e33c239111955d97b3ec160baafa..3539b5b1efe27be7ccbfebb358d= bb9cad2868f11 100644 --- a/kernel/dma/Kconfig +++ b/kernel/dma/Kconfig @@ -32,6 +32,9 @@ config NEED_SG_DMA_LENGTH config NEED_DMA_MAP_STATE bool =20 +config NEED_SG_DMA_DST_ADDR + bool + config ARCH_DMA_ADDR_T_64BIT def_bool 64BIT || PHYS_ADDR_T_64BIT =20 --=20 2.34.1 From nobody Tue Apr 7 13:09:45 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6ED33563DD for ; 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Thu, 12 Mar 2026 23:49:44 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c73eb97b41dsm936160a12.5.2026.03.12.23.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 23:49:43 -0700 (PDT) From: Sumit Kumar Date: Fri, 13 Mar 2026 12:19:26 +0530 Subject: [PATCH 2/3] PCI: epf-mhi: Add batched DMA read support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-dma_multi_sg-v1-2-8fabb0d1a759@oss.qualcomm.com> References: <20260313-dma_multi_sg-v1-0-8fabb0d1a759@oss.qualcomm.com> In-Reply-To: <20260313-dma_multi_sg-v1-0-8fabb0d1a759@oss.qualcomm.com> To: Krishna Chaitanya Chundru , Veerabhadrarao Badiganti , Subramanian Ananthanarayanan , Akhil Vinod , Manivannan Sadhasivam , Vinod Koul , Marek Szyprowski , Robin Murphy , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pci@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Implement two variants of the read_batch() callback: - pci_epf_mhi_edma_read_batch(): DMA-optimized implementation using dmaengine_prep_batch_sg_dma() to transfer multiple buffers in a single DMA transaction. - pci_epf_mhi_iatu_read_batch(): CPU-copy fallback that sequentially processes buffers using IATU. This enables the MHI endpoint stack to efficiently cache ring data, particularly for wraparound scenarios where ring data spans two non-contiguous memory regions. Signed-off-by: Sumit Kumar --- drivers/pci/endpoint/functions/Kconfig | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 120 +++++++++++++++++++++++= ++++ include/linux/mhi_ep.h | 3 + 3 files changed, 124 insertions(+) diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/= functions/Kconfig index 0c9cea0698d7bd3d8bd11aa1db0195978d9406b9..43131b6db8a2ca57b7a4f0eba8a= ffba3a77f9ad7 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -41,6 +41,7 @@ config PCI_EPF_VNTB config PCI_EPF_MHI tristate "PCI Endpoint driver for MHI bus" depends on PCI_ENDPOINT && MHI_BUS_EP + select NEED_SG_DMA_DST_ADDR help Enable this configuration option to enable the PCI Endpoint driver for Modem Host Interface (MHI) bus in Qualcomm Endpoint diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 6643a88c7a0ce38161bc6253c09d29f1c36ba394..198201d734cc2c6d09be229464a= 8efdafc3cd611 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -448,6 +448,124 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl= *mhi_cntrl, return ret; } =20 +static int pci_epf_mhi_iatu_read_batch(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info_array, + u32 num_buffers) +{ + int ret; + u32 i; + + for (i =3D 0; i < num_buffers; i++) { + ret =3D pci_epf_mhi_iatu_read(mhi_cntrl, &buf_info_array[i]); + if (ret < 0) + return ret; + } + + return 0; +} + +static int pci_epf_mhi_edma_read_batch(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info_array, + u32 num_buffers) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct dma_chan *chan =3D epf_mhi->dma_chan_rx; + struct device *dev =3D &epf_mhi->epf->dev; + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + DECLARE_COMPLETION_ONSTACK(complete); + struct scatterlist *sg; + dma_addr_t *dst_addrs; + dma_cookie_t cookie; + int ret; + u32 i; + + if (num_buffers =3D=3D 0) + return -EINVAL; + + mutex_lock(&epf_mhi->lock); + + sg =3D kcalloc(num_buffers, sizeof(*sg), GFP_KERNEL); + if (!sg) { + ret =3D -ENOMEM; + goto err_unlock; + } + + dst_addrs =3D kcalloc(num_buffers, sizeof(*dst_addrs), GFP_KERNEL); + if (!dst_addrs) { + ret =3D -ENOMEM; + goto err_free_sg; + } + + sg_init_table(sg, num_buffers); + + for (i =3D 0; i < num_buffers; i++) { + dst_addrs[i] =3D dma_map_single(dma_dev, buf_info_array[i].dev_addr, + buf_info_array[i].size, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(dma_dev, dst_addrs[i]); + if (ret) { + dev_err(dev, "Failed to map buffer %u\n", i); + goto err_unmap; + } + + sg_dma_address(&sg[i]) =3D buf_info_array[i].host_addr; + sg_dma_dst_address(&sg[i]) =3D dst_addrs[i]; + sg_dma_len(&sg[i]) =3D buf_info_array[i].size; + } + + config.direction =3D DMA_DEV_TO_MEM; + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unmap; + } + + desc =3D dmaengine_prep_batch_sg_dma(chan, sg, num_buffers, + DMA_DEV_TO_MEM, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare batch sg DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + desc->callback =3D pci_epf_mhi_dma_callback; + desc->callback_param =3D &complete; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to submit DMA\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + + ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + if (!ret) { + dev_err(dev, "DMA transfer timeout\n"); + dmaengine_terminate_sync(chan); + ret =3D -ETIMEDOUT; + goto err_unmap; + } + + ret =3D 0; + +err_unmap: + for (i =3D 0; i < num_buffers; i++) { + if (dst_addrs[i]) + dma_unmap_single(dma_dev, dst_addrs[i], + buf_info_array[i].size, DMA_FROM_DEVICE); + } + kfree(dst_addrs); +err_free_sg: + kfree(sg); +err_unlock: + mutex_unlock(&epf_mhi->lock); + return ret; +} + static void pci_epf_mhi_dma_worker(struct work_struct *work) { struct pci_epf_mhi *epf_mhi =3D container_of(work, struct pci_epf_mhi, dm= a_work); @@ -803,11 +921,13 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; mhi_cntrl->read_sync =3D mhi_cntrl->read_async =3D pci_epf_mhi_iatu_read; mhi_cntrl->write_sync =3D mhi_cntrl->write_async =3D pci_epf_mhi_iatu_wri= te; + mhi_cntrl->read_batch =3D pci_epf_mhi_iatu_read_batch; if (info->flags & MHI_EPF_USE_DMA) { mhi_cntrl->read_sync =3D pci_epf_mhi_edma_read; mhi_cntrl->write_sync =3D pci_epf_mhi_edma_write; mhi_cntrl->read_async =3D pci_epf_mhi_edma_read_async; mhi_cntrl->write_async =3D pci_epf_mhi_edma_write_async; + mhi_cntrl->read_batch =3D pci_epf_mhi_edma_read_batch; } =20 /* Register the MHI EP controller */ diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 7b40fc8cbe77ab8419d167e89264b69a817b9fb1..15554f966e4be1aea1f3129c5f2= 6253f5087edba 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -107,6 +107,7 @@ struct mhi_ep_buf_info { * @write_sync: CB function for writing to host memory synchronously * @read_async: CB function for reading from host memory asynchronously * @write_async: CB function for writing to host memory asynchronously + * @read_batch: CB function for reading from host memory in batches synchr= onously * @mhi_state: MHI Endpoint state * @max_chan: Maximum channels supported by the endpoint controller * @mru: MRU (Maximum Receive Unit) value of the endpoint controller @@ -164,6 +165,8 @@ struct mhi_ep_cntrl { int (*write_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); 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Signed-off-by: Sumit Kumar --- drivers/bus/mhi/ep/ring.c | 43 +++++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/bus/mhi/ep/ring.c b/drivers/bus/mhi/ep/ring.c index 26357ee68dee984d70ae5bf39f8f09f2cbcafe30..03c60c579e12c3bad100c7e1b6a= 75ae0e5646281 100644 --- a/drivers/bus/mhi/ep/ring.c +++ b/drivers/bus/mhi/ep/ring.c @@ -30,7 +30,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) { struct mhi_ep_cntrl *mhi_cntrl =3D ring->mhi_cntrl; struct device *dev =3D &mhi_cntrl->mhi_dev->dev; - struct mhi_ep_buf_info buf_info =3D {}; + struct mhi_ep_buf_info buf_info[2] =3D {}; size_t start; int ret; =20 @@ -44,35 +44,38 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring= , size_t end) =20 start =3D ring->wr_offset; if (start < end) { - buf_info.size =3D (end - start) * sizeof(struct mhi_ring_element); - buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); - buf_info.dev_addr =3D &ring->ring_cache[start]; + /* No wraparound */ + buf_info[0].size =3D (end - start) * sizeof(struct mhi_ring_element); + buf_info[0].host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_= element)); + buf_info[0].dev_addr =3D &ring->ring_cache[start]; =20 - ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->read_batch(mhi_cntrl, buf_info, 1); if (ret < 0) return ret; + + dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, + buf_info[0].size); } else { - buf_info.size =3D (ring->ring_size - start) * sizeof(struct mhi_ring_ele= ment); - buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); - buf_info.dev_addr =3D &ring->ring_cache[start]; + /* Wraparound */ + + /* Buffer 0: Tail portion (start =E2=86=92 ring_size) */ + buf_info[0].size =3D (ring->ring_size - start) * sizeof(struct mhi_ring_= element); + buf_info[0].host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_= element)); + buf_info[0].dev_addr =3D &ring->ring_cache[start]; =20 - ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); + /* Buffer 1: Head portion (0 =E2=86=92 end) */ + buf_info[1].size =3D end * sizeof(struct mhi_ring_element); + buf_info[1].host_addr =3D ring->rbase; + buf_info[1].dev_addr =3D &ring->ring_cache[0]; + + ret =3D mhi_cntrl->read_batch(mhi_cntrl, buf_info, 2); if (ret < 0) return ret; =20 - if (end) { - buf_info.host_addr =3D ring->rbase; - buf_info.dev_addr =3D &ring->ring_cache[0]; - buf_info.size =3D end * sizeof(struct mhi_ring_element); - - ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); - if (ret < 0) - return ret; - } + dev_dbg(dev, "Cached ring (batched): start %zu end %zu tail_size %zu hea= d_size %zu\n", + start, end, buf_info[0].size, buf_info[1].size); } =20 - dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, buf= _info.size); - return 0; } =20 --=20 2.34.1