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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:12 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:14 -0400 Subject: [PATCH v6 7/7] clk: test: introduce additional test case showing v2 rate change + LCM parent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-7-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4977; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=h2KdQwSzIlZcDjCLpoMS0OLH1GkGmmRBcuj91M9nvrU=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J1XCJS/r7Py2rKqbFGHVVc/s4Q/lbTZ8bzun0VK4 m0VJe0lHaUsDGJcDLJiiixLco0KIlJX2d67o8kCM4eVCWQIAxenAEwkWY3hDxcT//fbZ7SYuLXb PHc990i5nfHMJDVrhT2X1oxA18rW+Qz/fX8aVn1gWXrz8kfmeUeTFkc6/Ylhi0g88jjyMMfDy5P v8gMA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case that uses the clk divider with the v2 rate negotiation logic, plus the Lowest Common Multiple (LCM) to calculate the optimal parent rate. The test ensures that the parent clk rate is set to a rate that's acceptable to both children, and the sibling clock is not affected. The test in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree ends up with the correct state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz div=3D3 div=3D4 Additionally, add a note about why clk_dummy_div_lcm_ops + friends are still needed. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++= +++ 1 file changed, 49 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 40bc01a0259d8d49ca4c1983b6c10a3684a95f0b..00511afe5faa8b2631633ab796e= ce1bfe6944fb5 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -181,6 +181,14 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +/* + * drivers/clk/clk-divider.c has support for v2 rate negotiation, and sett= ing + * the parent based on the LCM, however we need to be able to test just se= tting + * the parent rate based on the LCM, and not set the v2 rate negotiation f= lag. + * This is to demonstrate existing functionality in the clk core, and ensu= re it + * stays the same. That's why we need to keep clk_dummy_div_lcm_ops, and c= an't + * just use clk_dummy_div_ops. + */ static int clk_dummy_div_lcm_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { @@ -709,6 +717,18 @@ clk_rate_change_sibling_div_div_test_lcm_ops_v1_params= [] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_lcm_ops_v1, clk_rate_change_sibling_div_div_test_lcm_ops_v1_params, desc) =20 +static const struct clk_rate_change_sibling_div_div_test_param +clk_rate_change_sibling_div_div_test_regular_ops_v2_params[] =3D { + { + .desc =3D "regular_ops_v2", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D CLK_V2_RATE_NEGOTIATION, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_regular_ops_v2, + clk_rate_change_sibling_div_div_test_regular_ops_v2_params, desc) + static int clk_rate_change_sibling_div_div_test_init(struct kunit *test) { const struct clk_rate_change_sibling_div_div_test_param *param =3D test->= param_value; @@ -836,6 +856,31 @@ static void clk_test_rate_change_sibling_div_div_3_v1(= struct kunit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is not affected, and maintains it's rate. + */ +static void clk_test_rate_change_sibling_div_div_4_v2(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based parent + v2 rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz (div=3D3), and child2 + * at 24 MHz (div=3D4). + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 4); +} + static struct kunit_case clk_rate_change_sibling_div_div_cases[] =3D { KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_1, clk_rate_change_sibling_div_div_test_regular_ops_gen_params), @@ -843,6 +888,10 @@ static struct kunit_case clk_rate_change_sibling_div_d= iv_cases[] =3D { clk_rate_change_sibling_div_div_test_regular_ops_gen_params), KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_3_v1, clk_rate_change_sibling_div_div_test_lcm_ops_v1_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_1, + clk_rate_change_sibling_div_div_test_regular_ops_v2_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_4_v2, + clk_rate_change_sibling_div_div_test_regular_ops_v2_gen_params), {} }; =20 --=20 2.53.0