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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:03 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:08 -0400 Subject: [PATCH v6 1/7] clk: test: introduce clk_dummy_div for a mock divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-1-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2200; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=7MaJmt+J8vsEg1l63G/wlfY1QJg69trFaQ3v7+1mC38=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32B0+FO/OJdn57smPZpMZMrFPtR2Sle8ed7s0Y+qNo uPL5y3X6ChlYRDjYpAVU2RZkmtUEJG6yvbeHU0WmDmsTCBDGLg4BWAiIl4Mf2Ui5Zns/+VPmLev pv/NPoe6OreHtYJZWpZs+7LzShu72RkZNr02bvmfxL7l+aqSB6qf51zZOe//Ge5Z7GcmXej+HmW ZyggA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 This is used to mock up a divider in the clk kunit tests. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney Reviewed-by: Maxime Ripard --- drivers/clk/clk_test.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index a268d7b5d4cb28ec1f029f828c31107f8e130556..88e35f4419c958983578750356a= 97c0a45effb55 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -136,6 +136,50 @@ static const struct clk_ops clk_dummy_single_parent_op= s =3D { .get_parent =3D clk_dummy_single_get_parent, }; =20 +/* 4 ought to be enough for anybody */ +#define CLK_DUMMY_DIV_WIDTH 4 +#define CLK_DUMMY_DIV_FLAGS (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLO= SEST) + +struct clk_dummy_div { + struct clk_hw hw; + unsigned int div; +}; + +static unsigned long clk_dummy_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + return divider_recalc_rate(hw, parent_rate, div->div, NULL, + CLK_DUMMY_DIV_FLAGS, CLK_DUMMY_DIV_WIDTH); +} + +static int clk_dummy_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && req->best_parent_rat= e < req->rate) + return -EINVAL; + + return divider_determine_rate(hw, req, NULL, CLK_DUMMY_DIV_WIDTH, CLK_DUM= MY_DIV_FLAGS); +} + +static int clk_dummy_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + div->div =3D divider_get_val(rate, parent_rate, NULL, CLK_DUMMY_DIV_WIDTH, + CLK_DUMMY_DIV_FLAGS); + + return 0; +} + +static const struct clk_ops clk_dummy_div_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .determine_rate =3D clk_dummy_div_determine_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + struct clk_multiple_parent_ctx { struct clk_dummy_context parents_ctx[2]; struct clk_hw hw; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:04 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:09 -0400 Subject: [PATCH v6 2/7] clk: test: introduce test suite for sibling rate changes on a divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-2-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7367; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=6RjRp0BMKBvqwmUs2I0l3tLNfJ+lEfqmjaaBafYyByA=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J2w9Ll7frtT36aff1+Wsd1uOno6Zc/1ySHlv67P+ LDq3aaMeR2lLAxiXAyyYoosS3KNCiJSV9neu6PJAjOHlQlkCAMXpwBMRCqWkeHHyau/P3revy16 i7WUV7SH3Y3j0r/lC6qXf0uxObFVm7GF4X/Gq3kSnJuzrS+dyAw40t4cZK/1kXelx71mS4UTy+/ 2ZPEDAA== X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Introduce a kunit test suite that demonstrates the current behavior of how a clock can unknowingly change the rate of it's siblings. Some boards are unknowingly dependent on this behavior, and per discussions at the 2025 Linux Plumbers Conference in Tokyo, we can't break the existing behavior. So let's add kunit tests with the current behavior so that we can be made aware if that functionality changes in the future. The tests in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 146 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 146 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 88e35f4419c958983578750356a97c0a45effb55..325da7c84ab2ecdcf6b7a023ce4= c2c4ef2d49862 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -7,6 +7,7 @@ #include #include #include +#include =20 /* Needed for clk_hw_get_clk() */ #include "clk.h" @@ -652,6 +653,150 @@ clk_multiple_parents_mux_test_suite =3D { .test_cases =3D clk_multiple_parents_mux_test_cases, }; =20 +struct clk_rate_change_sibling_div_div_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1, child2; + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +struct clk_rate_change_sibling_div_div_test_param { + const char *desc; + const struct clk_ops *ops; + unsigned int extra_child_flags; +}; + +static const struct clk_rate_change_sibling_div_div_test_param +clk_rate_change_sibling_div_div_test_regular_ops_params[] =3D { + { + .desc =3D "regular_ops", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D 0, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_regular_ops, + clk_rate_change_sibling_div_div_test_regular_ops_params, desc) + +static int clk_rate_change_sibling_div_div_test_init(struct kunit *test) +{ + const struct clk_rate_change_sibling_div_div_test_param *param =3D test->= param_value; + struct clk_rate_change_sibling_div_div_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D 24 * HZ_PER_MHZ; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + if (ret) + return ret; + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, + param->ops, + CLK_SET_RATE_PARENT | param->extra_child_flags); + ctx->child1.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ret; + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, + param->ops, + CLK_SET_RATE_PARENT | param->extra_child_flags); + ctx->child2.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + if (ret) + return ret; + + ctx->parent_clk =3D clk_hw_get_clk(&ctx->parent.hw, NULL); + ctx->child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->child2_clk =3D clk_hw_get_clk(&ctx->child2.hw, NULL); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + + return 0; +} + +static void clk_rate_change_sibling_div_div_test_exit(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + + clk_put(ctx->parent_clk); + clk_put(ctx->child1_clk); + clk_put(ctx->child2_clk); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT set + * and one requests a rate compatible with the existing parent rate, the p= arent and + * sibling rates are not affected. + */ +static void clk_test_rate_change_sibling_div_div_1(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, 6 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 6 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 4); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is also affected. This preserves existing behavior in the = clk + * core that some drivers may be unknowingly dependent on. + */ +static void clk_test_rate_change_sibling_div_div_2_v1(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * The last sibling rate change is the one that was successful, and + * wins. The parent, and two children are all changed to 32 MHz. This + * keeps the long-standing behavior of the clk core that some drivers + * may be unknowingly dependent on. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +static struct kunit_case clk_rate_change_sibling_div_div_cases[] =3D { + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_1, + clk_rate_change_sibling_div_div_test_regular_ops_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_2_v1, + clk_rate_change_sibling_div_div_test_regular_ops_gen_params), + {} +}; + +/* + * Test suite that creates a parent with two divider-only children, and + * documents the behavior of what happens to the sibling clock when one ch= ild + * changes its rate. + */ +static struct kunit_suite clk_rate_change_sibling_div_div_test_suite =3D { + .name =3D "clk-rate-change-sibling-div-div", + .init =3D clk_rate_change_sibling_div_div_test_init, + .exit =3D clk_rate_change_sibling_div_div_test_exit, + .test_cases =3D clk_rate_change_sibling_div_div_cases, +}; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:06 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:10 -0400 Subject: [PATCH v6 3/7] clk: introduce new helper clk_hw_get_children_lcm() to calculate LCM of all child rates Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-3-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3798; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=e6VNEFE5OKDlGjgl9TvkE/uAdwoIcDCMi2TMuH/63MM=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J36uUm3NURfuTvh+BHTEN15Qk/ittYecl5aaHeVc eK6dTx1HaUsDGJcDLJiiixLco0KIlJX2d67o8kCM4eVCWQIAxenAEzEfx/D/+ofYu/XrvdNqNMt ez318bu8R3//TePlKTXiejP/Xq90UDbDP4sPqX7aDOsef7GosTshFCn5I+hTSvvf297fdGQiAxy dWAA= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Introduce a new helper that recursively walks through all children and their descendants, calculating the lowest common multiple (LCM) of their rates. For the requesting child, it uses the requested rate; for other children, it uses their current rate. This is useful for determining what parent rate can satisfy all children through simple integer dividers. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney Reviewed-by: Maxime Ripard --- drivers/clk/clk.c | 48 ++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 50 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 47093cda9df32223c1120c3710261296027c4cd3..051fe755e3bf1b0a06db254b92f= 8a02889456db9 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -838,6 +839,53 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned= long min_rate, } EXPORT_SYMBOL_GPL(clk_hw_set_rate_range); =20 +/** + * clk_hw_get_children_lcm - Calculate LCM of all children's rates recursi= vely + * @hw: The parent clock hardware + * @requesting_hw: The child clock that is requesting a rate change (can b= e NULL) + * @requesting_rate: The target rate for the requesting clock + * + * This helper recursively walks through all children and their descendant= s, + * calculating the lowest common multiple (LCM) of their rates. For the + * requesting child, it uses the requested rate; for other children, it us= es their + * current rate. This is useful for determining what parent rate can satis= fy all + * children through simple integer dividers. + * + * Returns: The LCM of all non-zero rates found in the subtree, or 0 if no= valid rates. + */ +unsigned long clk_hw_get_children_lcm(struct clk_hw *hw, struct clk_hw *re= questing_hw, + unsigned long requesting_rate) +{ + unsigned long lcm_rate =3D 0; + unsigned long child_rate; + struct clk_core *child; + + hlist_for_each_entry(child, &hw->core->children, child_node) { + /* Use requesting rate for the requesting child, current rate for others= */ + if (child->hw =3D=3D requesting_hw) + child_rate =3D requesting_rate; + else + child_rate =3D clk_hw_get_rate(child->hw); + + if (child_rate =3D=3D 0) + continue; + + if (lcm_rate =3D=3D 0) + lcm_rate =3D child_rate; + else + lcm_rate =3D lcm(lcm_rate, child_rate); + + /* Recursively get LCM of this child's children */ + child_rate =3D clk_hw_get_children_lcm(child->hw, requesting_hw, + requesting_rate); + if (child_rate > 0) + lcm_rate =3D lcm(lcm_rate, child_rate); + } + + return lcm_rate; +} +EXPORT_SYMBOL_GPL(clk_hw_get_children_lcm); + /* * __clk_mux_determine_rate - clk_ops::determine_rate implementation for a= mux type clk * @hw: mux type clk to determine rate on diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 630705a47129453c241f1b1755f2c2f2a7ed8f77..2699b9759e13d0c1f0b54f4fa4f= 7f7bdd42e8dde 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1430,6 +1430,8 @@ void clk_hw_get_rate_range(struct clk_hw *hw, unsigne= d long *min_rate, unsigned long *max_rate); void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate); +unsigned long clk_hw_get_children_lcm(struct clk_hw *hw, struct clk_hw *re= questing_hw, + unsigned long requesting_rate); =20 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { --=20 2.53.0 From nobody Tue Apr 7 09:47:38 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9100C3C7DED for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:07 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:11 -0400 Subject: [PATCH v6 4/7] clk: test: introduce additional test case showing sibling clock rate change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-4-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5295; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=Bm7pp+07qGJu1B0VUFy7Z/f2WSbgupLCXm/OyTHO3Qc=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J2ujmM6mWyXsXG6l1hJ67ZHdzWvVbp0e7EJrZghN ck32WdCRykLgxgXg6yYIsuSXKOCiNRVtvfuaLLAzGFlAhnCwMUpABMpv8zI8K1OZ77Fx79ntGV3 /vy4Yzbf6vNaz6+E7m4N6vAvD2tvWcTw3+dH84OaFcJsi/gErdX3RO7+fexx8J17HgVbw84m859 v4QIA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case where the parent clk rate is set to a rate that's acceptable to both children, however the sibling clk rate is affected. The tests in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree should end up with the state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz However, child2 ends up with it's parent rate due to the way the clk core currently calculates handles rate changes. parent 96 MHz / \ child1 child2 32 MHz 96 MHz ^^^^^^ Incorrect. Should be 24 MHz. Let's document this behavior with a kunit test since some boards are unknowingly dependent on this behavior. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 325da7c84ab2ecdcf6b7a023ce4c2c4ef2d49862..40bc01a0259d8d49ca4c1983b6c= 10a3684a95f0b 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -181,6 +181,26 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +static int clk_dummy_div_lcm_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *parent_hw =3D clk_hw_get_parent(hw); + + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && req->best_parent_rat= e < req->rate) + return -EINVAL; + + req->best_parent_rate =3D clk_hw_get_children_lcm(parent_hw, hw, req->rat= e); + req->best_parent_hw =3D parent_hw; + + return divider_determine_rate(hw, req, NULL, CLK_DUMMY_DIV_WIDTH, CLK_DUM= MY_DIV_FLAGS); +} + +static const struct clk_ops clk_dummy_div_lcm_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .determine_rate =3D clk_dummy_div_lcm_determine_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + struct clk_multiple_parent_ctx { struct clk_dummy_context parents_ctx[2]; struct clk_hw hw; @@ -677,6 +697,18 @@ clk_rate_change_sibling_div_div_test_regular_ops_param= s[] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_regular_ops, clk_rate_change_sibling_div_div_test_regular_ops_params, desc) =20 +static const struct clk_rate_change_sibling_div_div_test_param +clk_rate_change_sibling_div_div_test_lcm_ops_v1_params[] =3D { + { + .desc =3D "lcm_ops_v1", + .ops =3D &clk_dummy_div_lcm_ops, + .extra_child_flags =3D 0, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_lcm_ops_v1, + clk_rate_change_sibling_div_div_test_lcm_ops_v1_params, desc) + static int clk_rate_change_sibling_div_div_test_init(struct kunit *test) { const struct clk_rate_change_sibling_div_div_test_param *param =3D test->= param_value; @@ -777,11 +809,40 @@ static void clk_test_rate_change_sibling_div_div_2_v1= (struct kunit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is also affected. This preserves existing behavior in the = clk + * core that some drivers may be unknowingly dependent on. + */ +static void clk_test_rate_change_sibling_div_div_3_v1(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based coordinated rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz (div=3D3), and child2 + * at 24 MHz (div=3D4). However, the clk core by default will clobber + * the sibling clk rate, so the sibling gets the parent rate. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + static struct kunit_case clk_rate_change_sibling_div_div_cases[] =3D { KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_1, clk_rate_change_sibling_div_div_test_regular_ops_gen_params), KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_2_v1, clk_rate_change_sibling_div_div_test_regular_ops_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_3_v1, + clk_rate_change_sibling_div_div_test_lcm_ops_v1_gen_params), {} }; =20 --=20 2.53.0 From nobody Tue Apr 7 09:47:38 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED2443C7DEE for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:09 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:12 -0400 Subject: [PATCH v6 5/7] clk: introduce new flag CLK_V2_RATE_NEGOTIATION for sensitive clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-5-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7718; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=3HZ34b5RxjZz3yxu8VhkXggn5qS1EdNU7N/d70jV8Lo=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J1ZtXDtV+ve6dXSq3iMeJLiF8t8YNzTscN05YRoe 8FunvfLOkpZGMS4GGTFFFmW5BoVRKSusr13R5MFZg4rE8gQBi5OAZiI8WyGfzorb0x6m/pjweLz c/guFJV/22vtsXw2n7Zg3Y23l9nk3G8zMjTJSVy+IfAyZYX/YZaUrBuiHOeu8HmxW2bOusflmOu czQsA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 As demonstrated by the kunit tests, clk_calc_subtree() in the clk core can overwrite a sibling clk with the parent rate. Clocks that are used for some subsystems like DRM and sound are particularly sensitive to this issue. I consider this to be a logic bug in the clk subsystem, however this functionality has existed since the clk core was introduced with commit b2476490ef11 ("clk: introduce the common clock framework"), and some boards are unknowingly dependent on this behavior. Let's add support for a v2 rate negotiation logic that addresses the logic error. Clks can opt into this new behavior by adding the flag CLK_V2_RATE_NEGOTIATION, or globally on all clks with the kernel parameter clk_v2_rate_negotiation. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk.c | 70 ++++++++++++++++++++++++++++++++++++----= ---- include/linux/clk-provider.h | 3 ++ 2 files changed, 60 insertions(+), 13 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 051fe755e3bf1b0a06db254b92f8a02889456db9..64c6de5ff5df2117b8d1aca663d= 40b41d974bf92 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -886,6 +886,43 @@ unsigned long clk_hw_get_children_lcm(struct clk_hw *h= w, struct clk_hw *requesti } EXPORT_SYMBOL_GPL(clk_hw_get_children_lcm); =20 +static bool clk_v2_rate_negotiation_enabled; +static int __init clk_v2_rate_negotiation_setup(char *__unused) +{ + clk_v2_rate_negotiation_enabled =3D true; + return 1; +} +__setup("clk_v2_rate_negotiation", clk_v2_rate_negotiation_setup); + +/** + * clk_has_v2_rate_negotiation - Check if a clk should use v2 rate negotia= tion + * @core: The clock core to check + * + * This function recursively checks if the clk or any of its descendants h= ave + * the CLK_V2_RATE_NEGOTIATION flag set. The v2 behavior can also be enabl= ed + * globally by adding clk_v2_rate_negotiation to the kernel command line. + * + * Returns: true if the v2 logic should be used; false otherwise + */ +bool clk_has_v2_rate_negotiation(const struct clk_core *core) +{ + struct clk_core *child; + + if (clk_v2_rate_negotiation_enabled) + return true; + + if (core->flags & CLK_V2_RATE_NEGOTIATION) + return true; + + hlist_for_each_entry(child, &core->children, child_node) { + if (clk_has_v2_rate_negotiation(child)) + return true; + } + + return false; +} +EXPORT_SYMBOL_GPL(clk_has_v2_rate_negotiation); + /* * __clk_mux_determine_rate - clk_ops::determine_rate implementation for a= mux type clk * @hw: mux type clk to determine rate on @@ -2293,7 +2330,8 @@ static int __clk_speculate_rates(struct clk_core *cor= e, } =20 static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate, - struct clk_core *new_parent, u8 p_index) + struct clk_core *new_parent, u8 p_index, + struct clk_core *initiating_clk) { struct clk_core *child; =20 @@ -2306,8 +2344,12 @@ static void clk_calc_subtree(struct clk_core *core, = unsigned long new_rate, new_parent->new_child =3D core; =20 hlist_for_each_entry(child, &core->children, child_node) { - child->new_rate =3D clk_recalc(child, new_rate); - clk_calc_subtree(child, child->new_rate, NULL, 0); + if (child !=3D initiating_clk && clk_has_v2_rate_negotiation(child)) + child->new_rate =3D child->rate; + else + child->new_rate =3D clk_recalc(child, new_rate); + + clk_calc_subtree(child, child->new_rate, NULL, 0, initiating_clk); } } =20 @@ -2316,7 +2358,8 @@ static void clk_calc_subtree(struct clk_core *core, u= nsigned long new_rate, * changed. */ static struct clk_core *clk_calc_new_rates(struct clk_core *core, - unsigned long rate) + unsigned long rate, + struct clk_core *initiating_clk) { struct clk_core *top =3D core; struct clk_core *old_parent, *parent; @@ -2364,7 +2407,7 @@ static struct clk_core *clk_calc_new_rates(struct clk= _core *core, return NULL; } else { /* pass-through clock with adjustable parent */ - top =3D clk_calc_new_rates(parent, rate); + top =3D clk_calc_new_rates(parent, rate, initiating_clk); new_rate =3D parent->new_rate; goto out; } @@ -2389,10 +2432,10 @@ static struct clk_core *clk_calc_new_rates(struct c= lk_core *core, =20 if ((core->flags & CLK_SET_RATE_PARENT) && parent && best_parent_rate !=3D parent->rate) - top =3D clk_calc_new_rates(parent, best_parent_rate); + top =3D clk_calc_new_rates(parent, best_parent_rate, initiating_clk); =20 out: - clk_calc_subtree(core, new_rate, parent, p_index); + clk_calc_subtree(core, new_rate, parent, p_index, initiating_clk); =20 return top; } @@ -2440,7 +2483,7 @@ static struct clk_core *clk_propagate_rate_change(str= uct clk_core *core, * walk down a subtree and set the new rates notifying the rate * change on the way */ -static void clk_change_rate(struct clk_core *core) +static void clk_change_rate(struct clk_core *core, struct clk_core *initia= ting_clk) { struct clk_core *child; struct hlist_node *tmp; @@ -2509,7 +2552,7 @@ static void clk_change_rate(struct clk_core *core) __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate); =20 if (core->flags & CLK_RECALC_NEW_RATES) - (void)clk_calc_new_rates(core, core->new_rate); + (void)clk_calc_new_rates(core, core->new_rate, initiating_clk); =20 /* * Use safe iteration, as change_rate can actually swap parents @@ -2519,12 +2562,12 @@ static void clk_change_rate(struct clk_core *core) /* Skip children who will be reparented to another clock */ if (child->new_parent && child->new_parent !=3D core) continue; - clk_change_rate(child); + clk_change_rate(child, initiating_clk); } =20 /* handle the new child who might not be in core->children yet */ if (core->new_child) - clk_change_rate(core->new_child); + clk_change_rate(core->new_child, initiating_clk); =20 clk_pm_runtime_put(core); } @@ -2580,7 +2623,7 @@ static int clk_core_set_rate_nolock(struct clk_core *= core, return -EBUSY; =20 /* calculate new rates and get the topmost changed clock */ - top =3D clk_calc_new_rates(core, req_rate); + top =3D clk_calc_new_rates(core, req_rate, core); if (!top) return -EINVAL; =20 @@ -2599,7 +2642,7 @@ static int clk_core_set_rate_nolock(struct clk_core *= core, } =20 /* change the rates */ - clk_change_rate(top); + clk_change_rate(top, core); =20 core->req_rate =3D req_rate; err: @@ -3586,6 +3629,7 @@ static const struct { ENTRY(CLK_IS_CRITICAL), ENTRY(CLK_OPS_PARENT_ENABLE), ENTRY(CLK_DUTY_CYCLE_PARENT), + ENTRY(CLK_V2_RATE_NEGOTIATION), #undef ENTRY }; =20 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2699b9759e13d0c1f0b54f4fa4f7f7bdd42e8dde..e0fc0bd347e5920e999ac96dbed= 9fc247f9443fa 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -32,6 +32,8 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +/* clock participates in v2 rate negotiation */ +#define CLK_V2_RATE_NEGOTIATION BIT(14) =20 struct clk; struct clk_hw; @@ -1432,6 +1434,7 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigne= d long min_rate, unsigned long max_rate); unsigned long clk_hw_get_children_lcm(struct clk_hw *hw, struct clk_hw *re= questing_hw, unsigned long requesting_rate); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:10 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:13 -0400 Subject: [PATCH v6 6/7] clk: divider: enable optional support for v2 rate negotiation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-6-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2617; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=zKXv8T0pDXUYDds5ohnk6vvqdTfTZGnDkfT+a9khpbQ=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J1dyrM1SqkmKL9+rVvBHW6WhwymiWsVekQUVoZO/ hExYfaqjlIWBjEuBlkxRZYluUYFEamrbO/d0WSBmcPKBDKEgYtTACbysYHhD3/yiUdpkaKdk3gs L8zOFdsgfTPGfH1Hs/9Vowo1hRfS+YwMG/n61ztFp2jnuwZoJd48cmBF3JvZSjEaj4tPFj9+rsP IAgA= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 If the v2 rate negotiation logic is enabled in this portion of the clk subtree, then use the Lowest Common Multiple (LCM) of all of the child rates to determine what the parent rate should be. Make this change for clk_divider_bestdiv (used by clk_divider_determine_rate), and divider_ro_determine_rate. Note that the v2 rate negotiation logic is disabled by default, unless a clk in this portion of the subtree has the flag CLK_V2_RATE_NEGOTIATION, or globally on all clks with the kernel parameter clk_v2_rate_negotiation. This change was tested on a Thinkpad x13s laptop. Some clks used this new code, however this needs to be tested on more real systems. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney Reviewed-by: Maxime Ripard --- drivers/clk/clk-divider.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 45e7ebde4a8b4d6572aa9d867a6f12f6caf8aae4..17646a06420e099b5fa3ec99d92= 175356c65afa0 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -315,6 +315,19 @@ static int clk_divider_bestdiv(struct clk_hw *hw, stru= ct clk_hw *parent, return bestdiv; } =20 + if (clk_has_v2_rate_negotiation(parent->core)) { + unsigned long lcm_rate; + + lcm_rate =3D clk_hw_get_children_lcm(parent, hw, rate); + if (lcm_rate > 0) { + *best_parent_rate =3D lcm_rate; + bestdiv =3D _div_round(table, lcm_rate, rate, flags); + bestdiv =3D bestdiv =3D=3D 0 ? 1 : bestdiv; + bestdiv =3D bestdiv > maxdiv ? maxdiv : bestdiv; + return bestdiv; + } + } + /* * The maximum divider we can use without overflowing * unsigned long in rate * i below @@ -377,8 +390,19 @@ int divider_ro_determine_rate(struct clk_hw *hw, struc= t clk_rate_request *req, if (!req->best_parent_hw) return -EINVAL; =20 - req->best_parent_rate =3D clk_hw_round_rate(req->best_parent_hw, - req->rate * div); + if (clk_has_v2_rate_negotiation(req->best_parent_hw->core)) { + unsigned long lcm_rate; + + lcm_rate =3D clk_hw_get_children_lcm(req->best_parent_hw, hw, req->rate= ); + if (lcm_rate > 0) + req->best_parent_rate =3D lcm_rate; + else + req->best_parent_rate =3D clk_hw_round_rate(req->best_parent_hw, + req->rate * div); + } else { + req->best_parent_rate =3D clk_hw_round_rate(req->best_parent_hw, + req->rate * div); + } } =20 req->rate =3D DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); --=20 2.53.0 From nobody Tue Apr 7 09:47:38 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9310B3C9EE1 for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cda215c2a9sm587964785a.46.2026.03.13.09.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:44:12 -0700 (PDT) From: Brian Masney Date: Fri, 13 Mar 2026 12:43:14 -0400 Subject: [PATCH v6 7/7] clk: test: introduce additional test case showing v2 rate change + LCM parent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260313-clk-scaling-v6-7-ce89968c5247@redhat.com> References: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> In-Reply-To: <20260313-clk-scaling-v6-0-ce89968c5247@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4977; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=h2KdQwSzIlZcDjCLpoMS0OLH1GkGmmRBcuj91M9nvrU=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDK32J1XCJS/r7Py2rKqbFGHVVc/s4Q/lbTZ8bzun0VK4 m0VJe0lHaUsDGJcDLJiiixLco0KIlJX2d67o8kCM4eVCWQIAxenAEwkWY3hDxcT//fbZ7SYuLXb PHc990i5nfHMJDVrhT2X1oxA18rW+Qz/fX8aVn1gWXrz8kfmeUeTFkc6/Ylhi0g88jjyMMfDy5P v8gMA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case that uses the clk divider with the v2 rate negotiation logic, plus the Lowest Common Multiple (LCM) to calculate the optimal parent rate. The test ensures that the parent clk rate is set to a rate that's acceptable to both children, and the sibling clock is not affected. The test in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree ends up with the correct state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz div=3D3 div=3D4 Additionally, add a note about why clk_dummy_div_lcm_ops + friends are still needed. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++= +++ 1 file changed, 49 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 40bc01a0259d8d49ca4c1983b6c10a3684a95f0b..00511afe5faa8b2631633ab796e= ce1bfe6944fb5 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -181,6 +181,14 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +/* + * drivers/clk/clk-divider.c has support for v2 rate negotiation, and sett= ing + * the parent based on the LCM, however we need to be able to test just se= tting + * the parent rate based on the LCM, and not set the v2 rate negotiation f= lag. + * This is to demonstrate existing functionality in the clk core, and ensu= re it + * stays the same. That's why we need to keep clk_dummy_div_lcm_ops, and c= an't + * just use clk_dummy_div_ops. + */ static int clk_dummy_div_lcm_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { @@ -709,6 +717,18 @@ clk_rate_change_sibling_div_div_test_lcm_ops_v1_params= [] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_lcm_ops_v1, clk_rate_change_sibling_div_div_test_lcm_ops_v1_params, desc) =20 +static const struct clk_rate_change_sibling_div_div_test_param +clk_rate_change_sibling_div_div_test_regular_ops_v2_params[] =3D { + { + .desc =3D "regular_ops_v2", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D CLK_V2_RATE_NEGOTIATION, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_sibling_div_div_test_regular_ops_v2, + clk_rate_change_sibling_div_div_test_regular_ops_v2_params, desc) + static int clk_rate_change_sibling_div_div_test_init(struct kunit *test) { const struct clk_rate_change_sibling_div_div_test_param *param =3D test->= param_value; @@ -836,6 +856,31 @@ static void clk_test_rate_change_sibling_div_div_3_v1(= struct kunit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is not affected, and maintains it's rate. + */ +static void clk_test_rate_change_sibling_div_div_4_v2(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based parent + v2 rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz (div=3D3), and child2 + * at 24 MHz (div=3D4). + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 4); +} + static struct kunit_case clk_rate_change_sibling_div_div_cases[] =3D { KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_1, clk_rate_change_sibling_div_div_test_regular_ops_gen_params), @@ -843,6 +888,10 @@ static struct kunit_case clk_rate_change_sibling_div_d= iv_cases[] =3D { clk_rate_change_sibling_div_div_test_regular_ops_gen_params), KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_3_v1, clk_rate_change_sibling_div_div_test_lcm_ops_v1_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_1, + clk_rate_change_sibling_div_div_test_regular_ops_v2_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_div_div_4_v2, + clk_rate_change_sibling_div_div_test_regular_ops_v2_gen_params), {} }; =20 --=20 2.53.0